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-rw-r--r--arch/arm/boot/dts/Makefile53
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts17
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi4
-rw-r--r--arch/arm/boot/dts/am335x-lxm.dts362
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi32
-rw-r--r--arch/arm/boot/dts/am4372.dtsi48
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts34
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts12
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts405
-rw-r--r--arch/arm/boot/dts/arm-realview-pb1176.dts412
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts106
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts25
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts101
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn104.dts64
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts73
-rw-r--r--arch/arm/boot/dts/armada-370-synology-ds213j.dts316
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi11
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi190
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi12
-rw-r--r--arch/arm/boot/dts/armada-385-db.dts2
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi6
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts57
-rw-r--r--arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts75
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi15
-rw-r--r--arch/arm/boot/dts/armada-xp-netgear-rn2120.dts166
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts14
-rw-r--r--arch/arm/boot/dts/armada-xp-synology-ds414.dts330
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi66
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi19
-rw-r--r--arch/arm/boot/dts/at91sam9x25.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x35.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi12
-rw-r--r--arch/arm/boot/dts/at91sam9x5_can.dtsi50
-rw-r--r--arch/arm/boot/dts/at91sam9x5_usart3.dtsi3
-rw-r--r--arch/arm/boot/dts/atlas6.dtsi15
-rw-r--r--arch/arm/boot/dts/bcm-cygnus-clock.dtsi91
-rw-r--r--arch/arm/boot/dts/bcm-cygnus.dtsi140
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b-plus.dts30
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi-b.dts46
-rw-r--r--arch/arm/boot/dts/bcm2835-rpi.dtsi51
-rw-r--r--arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts64
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6250.dts59
-rw-r--r--arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts84
-rw-r--r--arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts78
-rw-r--r--arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts57
-rw-r--r--arch/arm/boot/dts/bcm47081.dtsi26
-rw-r--r--arch/arm/boot/dts/bcm5301x.dtsi51
-rw-r--r--arch/arm/boot/dts/bcm911360_entphn.dts53
-rw-r--r--arch/arm/boot/dts/bcm911360k.dts53
-rw-r--r--arch/arm/boot/dts/bcm958300k.dts53
-rw-r--r--arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts16
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi110
-rw-r--r--arch/arm/boot/dts/berlin2cd-google-chromecast.dts30
-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi82
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts61
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi96
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts133
-rw-r--r--arch/arm/boot/dts/dra7.dtsi202
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts319
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi22
-rw-r--r--arch/arm/boot/dts/exynos3250-monk.dts579
-rw-r--r--arch/arm/boot/dts/exynos3250-pinctrl.dtsi16
-rw-r--r--arch/arm/boot/dts/exynos3250-rinato.dts682
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts16
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts16
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi17
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi17
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi26
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts412
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi29
-rw-r--r--arch/arm/boot/dts/exynos4415-pinctrl.dtsi573
-rw-r--r--arch/arm/boot/dts/exynos4415.dtsi604
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi16
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts907
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts618
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts266
-rw-r--r--arch/arm/boot/dts/exynos5250-spring.dts566
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi20
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts7
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts7
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2-dkb.dts33
-rw-r--r--arch/arm/boot/dts/hisi-x5hd2.dtsi390
-rw-r--r--arch/arm/boot/dts/imx51.dtsi12
-rw-r--r--arch/arm/boot/dts/imx53.dtsi25
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi8
-rw-r--r--arch/arm/boot/dts/imx6q-tbs2910.dts432
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi131
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi97
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi4
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi14
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts4
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts66
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi8
-rw-r--r--arch/arm/boot/dts/k2e-evm.dts12
-rw-r--r--arch/arm/boot/dts/k2e.dtsi45
-rw-r--r--arch/arm/boot/dts/k2l-evm.dts12
-rw-r--r--arch/arm/boot/dts/keystone.dtsi45
-rw-r--r--arch/arm/boot/dts/kirkwood-dir665.dts278
-rw-r--r--arch/arm/boot/dts/kirkwood-synology.dtsi2
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts240
-rw-r--r--arch/arm/boot/dts/ls1021a-twr.dts127
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi408
-rw-r--r--arch/arm/boot/dts/meson.dtsi37
-rw-r--r--arch/arm/boot/dts/meson6-atv1200.dts2
-rw-r--r--arch/arm/boot/dts/meson6.dtsi2
-rw-r--r--arch/arm/boot/dts/meson8.dtsi92
-rw-r--r--arch/arm/boot/dts/mt6592-evb.dts26
-rw-r--r--arch/arm/boot/dts/mt6592.dtsi98
-rw-r--r--arch/arm/boot/dts/mt8127-moose.dts25
-rw-r--r--arch/arm/boot/dts/mt8127.dtsi94
-rw-r--r--arch/arm/boot/dts/mt8135-evbp1.dts25
-rw-r--r--arch/arm/boot/dts/mt8135.dtsi116
-rw-r--r--arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi41
-rw-r--r--arch/arm/boot/dts/omap-zoom-common.dtsi62
-rw-r--r--arch/arm/boot/dts/omap2420-n8x0-common.dtsi4
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi1
-rw-r--r--arch/arm/boot/dts/omap2430-sdp.dts28
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3517.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3530.dts11
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3730.dts24
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x.dtsi151
-rw-r--r--arch/arm/boot/dts/omap3-cm-t3x30.dtsi18
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts4
-rw-r--r--arch/arm/boot/dts/omap3-evm-37xx.dts5
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dtsi86
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi103
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-common.dtsi246
-rw-r--r--arch/arm/boot/dts/omap3-igep0020-rev-f.dts45
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts285
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-common.dtsi60
-rw-r--r--arch/arm/boot/dts/omap3-igep0030-rev-g.dts67
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts123
-rw-r--r--arch/arm/boot/dts/omap3-ldp.dts3
-rw-r--r--arch/arm/boot/dts/omap3-lilly-a83x.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts51
-rw-r--r--arch/arm/boot/dts/omap3-n950-n9.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-sb-t35.dtsi126
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3517.dts15
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3530.dts15
-rw-r--r--arch/arm/boot/dts/omap3-sbc-t3730.dts15
-rw-r--r--arch/arm/boot/dts/omap3-tao3530.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts8
-rw-r--r--arch/arm/boot/dts/omap4-duovero-parlor.dts1
-rw-r--r--arch/arm/boot/dts/omap4.dtsi1
-rw-r--r--arch/arm/boot/dts/omap5.dtsi1
-rw-r--r--arch/arm/boot/dts/prima2.dtsi33
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts4
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi37
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts6
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi44
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts4
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts131
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi189
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts11
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts99
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi186
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts2
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi29
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts4
-rw-r--r--arch/arm/boot/dts/rk3066a-marsboard.dts206
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi115
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts23
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi45
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts6
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi6
-rw-r--r--arch/arm/boot/dts/rk3288-thermal.dtsi74
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi99
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi17
-rw-r--r--arch/arm/boot/dts/s3c6410-mini6410.dts4
-rw-r--r--arch/arm/boot/dts/s3c64xx.dtsi1
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts8
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi10
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi27
-rw-r--r--arch/arm/boot/dts/socfpga_arria10.dtsi374
-rwxr-xr-xarch/arm/boot/dts/socfpga_arria10_socdk.dts48
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5.dtsi4
-rw-r--r--arch/arm/boot/dts/ste-nomadik-nhk15.dts151
-rw-r--r--arch/arm/boot/dts/ste-nomadik-s8815.dts56
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi45
-rw-r--r--arch/arm/boot/dts/stih407-b2120.dts55
-rw-r--r--arch/arm/boot/dts/stih407-clock.dtsi293
-rw-r--r--arch/arm/boot/dts/stih407-family.dtsi (renamed from arch/arm/boot/dts/stih407.dtsi)35
-rw-r--r--arch/arm/boot/dts/stih410-b2120.dts29
-rw-r--r--arch/arm/boot/dts/stih410-clock.dtsi338
-rw-r--r--arch/arm/boot/dts/stih410-pinctrl.dtsi34
-rw-r--r--arch/arm/boot/dts/stih410.dtsi14
-rw-r--r--arch/arm/boot/dts/stih415-pinctrl.dtsi361
-rw-r--r--arch/arm/boot/dts/stih415.dtsi12
-rw-r--r--arch/arm/boot/dts/stih416-b2020.dts22
-rw-r--r--arch/arm/boot/dts/stih416-b2020e.dts26
-rw-r--r--arch/arm/boot/dts/stih416-pinctrl.dtsi415
-rw-r--r--arch/arm/boot/dts/stih416.dtsi209
-rw-r--r--arch/arm/boot/dts/stih41x-b2000.dtsi6
-rw-r--r--arch/arm/boot/dts/stih41x-b2020.dtsi10
-rw-r--r--arch/arm/boot/dts/stih41x-b2020x.dtsi4
-rw-r--r--arch/arm/boot/dts/stihxxx-b2120.dtsi59
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet97fv2.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts46
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi14
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts46
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts46
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi14
-rw-r--r--arch/arm/boot/dts/sun5i-a13-hsg-h702.dts6
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts48
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-app4-evb1.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts46
-rw-r--r--arch/arm/boot/dts/sun6i-a31-m9.dts103
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi46
-rw-r--r--arch/arm/boot/dts/sun7i-a20-bananapi.dts214
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts14
-rw-r--r--arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20-m3.dts168
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts228
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3.dts46
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi45
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts46
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi6
-rw-r--r--arch/arm/boot/dts/sun9i-a80-optimus.dts119
-rw-r--r--arch/arm/boot/dts/sun9i-a80.dtsi514
-rw-r--r--arch/arm/boot/dts/sunxi-common-regulators.dtsi66
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi2
-rw-r--r--arch/arm/boot/dts/vf-colibri-eval-v3.dtsi96
-rw-r--r--arch/arm/boot/dts/vf-colibri.dtsi186
-rw-r--r--arch/arm/boot/dts/vf500-colibri-eval-v3.dts17
-rw-r--r--arch/arm/boot/dts/vf500-colibri.dtsi20
-rw-r--r--arch/arm/boot/dts/vf500.dtsi171
-rw-r--r--arch/arm/boot/dts/vf610-colibri-eval-v3.dts33
-rw-r--r--arch/arm/boot/dts/vf610-colibri.dtsi100
-rw-r--r--arch/arm/boot/dts/vf610-cosmic.dts14
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts46
-rw-r--r--arch/arm/boot/dts/vf610.dtsi486
-rw-r--r--arch/arm/boot/dts/vfxxx.dtsi437
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi1
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts1
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zc706.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zed.dts4
-rw-r--r--arch/arm/boot/dts/zynq-zybo.dts52
259 files changed, 19993 insertions, 3295 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index fe92f5df9d3c..6a3d9a6c4497 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,8 +54,17 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 56dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
57dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb 57dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb
58dtb-$(CONFIG_ARCH_BCM_5301X) += \
59 bcm4708-buffalo-wzr-1750dhp.dtb \
60 bcm4708-netgear-r6250.dtb \
61 bcm4708-netgear-r6300-v2.dtb \
62 bcm47081-asus-rt-n18u.dtb \
63 bcm47081-buffalo-wzr-600dhp2.dtb
58dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb 64dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
65dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \
66 bcm911360k.dtb \
67 bcm958300k.dtb
59dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ 68dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
60 bcm21664-garnet.dtb 69 bcm21664-garnet.dtb
61dtb-$(CONFIG_ARCH_BERLIN) += \ 70dtb-$(CONFIG_ARCH_BERLIN) += \
@@ -67,7 +76,9 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \
67dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 76dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
68 da850-evm.dtb 77 da850-evm.dtb
69dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb 78dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
70dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 79dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \
80 exynos3250-rinato.dtb \
81 exynos4210-origen.dtb \
71 exynos4210-smdkv310.dtb \ 82 exynos4210-smdkv310.dtb \
72 exynos4210-trats.dtb \ 83 exynos4210-trats.dtb \
73 exynos4210-universal_c210.dtb \ 84 exynos4210-universal_c210.dtb \
@@ -81,6 +92,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
81 exynos5250-arndale.dtb \ 92 exynos5250-arndale.dtb \
82 exynos5250-smdk5250.dtb \ 93 exynos5250-smdk5250.dtb \
83 exynos5250-snow.dtb \ 94 exynos5250-snow.dtb \
95 exynos5250-spring.dtb \
84 exynos5260-xyref5260.dtb \ 96 exynos5260-xyref5260.dtb \
85 exynos5410-smdk5410.dtb \ 97 exynos5410-smdk5410.dtb \
86 exynos5420-arndale-octa.dtb \ 98 exynos5420-arndale-octa.dtb \
@@ -104,6 +116,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
104 kirkwood-d2net.dtb \ 116 kirkwood-d2net.dtb \
105 kirkwood-db-88f6281.dtb \ 117 kirkwood-db-88f6281.dtb \
106 kirkwood-db-88f6282.dtb \ 118 kirkwood-db-88f6282.dtb \
119 kirkwood-dir665.dtb \
107 kirkwood-dns320.dtb \ 120 kirkwood-dns320.dtb \
108 kirkwood-dns325.dtb \ 121 kirkwood-dns325.dtb \
109 kirkwood-dockstar.dtb \ 122 kirkwood-dockstar.dtb \
@@ -240,6 +253,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
240 imx6q-sabrelite.dtb \ 253 imx6q-sabrelite.dtb \
241 imx6q-sabresd.dtb \ 254 imx6q-sabresd.dtb \
242 imx6q-sbc6x.dtb \ 255 imx6q-sbc6x.dtb \
256 imx6q-tbs2910.dtb \
243 imx6q-udoo.dtb \ 257 imx6q-udoo.dtb \
244 imx6q-wandboard.dtb \ 258 imx6q-wandboard.dtb \
245 imx6q-wandboard-revb1.dtb \ 259 imx6q-wandboard-revb1.dtb \
@@ -250,6 +264,9 @@ dtb-$(CONFIG_ARCH_MXC) += \
250 imx6q-tx6q-1110.dtb \ 264 imx6q-tx6q-1110.dtb \
251 imx6sl-evk.dtb \ 265 imx6sl-evk.dtb \
252 imx6sx-sdb.dtb \ 266 imx6sx-sdb.dtb \
267 ls1021a-qds.dtb \
268 ls1021a-twr.dtb \
269 vf500-colibri-eval-v3.dtb \
253 vf610-colibri-eval-v3.dtb \ 270 vf610-colibri-eval-v3.dtb \
254 vf610-cosmic.dtb \ 271 vf610-cosmic.dtb \
255 vf610-twr.dtb 272 vf610-twr.dtb
@@ -274,7 +291,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
274 imx28-m28evk.dtb \ 291 imx28-m28evk.dtb \
275 imx28-sps1.dtb \ 292 imx28-sps1.dtb \
276 imx28-tx28.dtb 293 imx28-tx28.dtb
277dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb 294dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \
295 ste-nomadik-nhk15.dtb
278dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ 296dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
279 nspire-tp.dtb \ 297 nspire-tp.dtb \
280 nspire-clp.dtb 298 nspire-clp.dtb
@@ -302,7 +320,9 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
302 omap3-ha.dtb \ 320 omap3-ha.dtb \
303 omap3-ha-lcd.dtb \ 321 omap3-ha-lcd.dtb \
304 omap3-igep0020.dtb \ 322 omap3-igep0020.dtb \
323 omap3-igep0020-rev-f.dtb \
305 omap3-igep0030.dtb \ 324 omap3-igep0030.dtb \
325 omap3-igep0030-rev-g.dtb \
306 omap3-ldp.dtb \ 326 omap3-ldp.dtb \
307 omap3-lilly-dbb056.dtb \ 327 omap3-lilly-dbb056.dtb \
308 omap3-n900.dtb \ 328 omap3-n900.dtb \
@@ -331,7 +351,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
331 am335x-evm.dtb \ 351 am335x-evm.dtb \
332 am335x-evmsk.dtb \ 352 am335x-evmsk.dtb \
333 am335x-nano.dtb \ 353 am335x-nano.dtb \
334 am335x-pepper.dtb 354 am335x-pepper.dtb \
355 am335x-lxm.dtb
335dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ 356dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
336 omap4-panda.dtb \ 357 omap4-panda.dtb \
337 omap4-panda-a4.dtb \ 358 omap4-panda-a4.dtb \
@@ -347,6 +368,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
347 omap5-sbc-t54.dtb \ 368 omap5-sbc-t54.dtb \
348 omap5-uevm.dtb 369 omap5-uevm.dtb
349dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ 370dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
371 am57xx-beagle-x15.dtb \
350 dra72-evm.dtb 372 dra72-evm.dtb
351dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ 373dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
352 orion5x-lacie-ethernet-disk-mini-v2.dtb \ 374 orion5x-lacie-ethernet-disk-mini-v2.dtb \
@@ -363,8 +385,10 @@ dtb-$(CONFIG_ARCH_QCOM) += \
363 qcom-msm8660-surf.dtb \ 385 qcom-msm8660-surf.dtb \
364 qcom-msm8960-cdp.dtb \ 386 qcom-msm8960-cdp.dtb \
365 qcom-msm8974-sony-xperia-honami.dtb 387 qcom-msm8974-sony-xperia-honami.dtb
388dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb
366dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 389dtb-$(CONFIG_ARCH_ROCKCHIP) += \
367 rk3066a-bqcurie2.dtb \ 390 rk3066a-bqcurie2.dtb \
391 rk3066a-marsboard.dtb \
368 rk3188-radxarock.dtb \ 392 rk3188-radxarock.dtb \
369 rk3288-evb-act8846.dtb \ 393 rk3288-evb-act8846.dtb \
370 rk3288-evb-rk808.dtb 394 rk3288-evb-rk808.dtb
@@ -396,6 +420,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
396 r8a7791-koelsch.dtb \ 420 r8a7791-koelsch.dtb \
397 r8a7794-alt.dtb 421 r8a7794-alt.dtb
398dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ 422dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
423 socfpga_arria10_socdk.dtb \
399 socfpga_cyclone5_socdk.dtb \ 424 socfpga_cyclone5_socdk.dtb \
400 socfpga_cyclone5_sockit.dtb \ 425 socfpga_cyclone5_sockit.dtb \
401 socfpga_cyclone5_socrates.dtb \ 426 socfpga_cyclone5_socrates.dtb \
@@ -408,6 +433,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
408 spear320-hmi.dtb 433 spear320-hmi.dtb
409dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb 434dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
410dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ 435dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
436 stih410-b2120.dtb \
411 stih415-b2000.dtb \ 437 stih415-b2000.dtb \
412 stih415-b2020.dtb \ 438 stih415-b2020.dtb \
413 stih416-b2000.dtb \ 439 stih416-b2000.dtb \
@@ -434,15 +460,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \
434 sun6i-a31-hummingbird.dtb \ 460 sun6i-a31-hummingbird.dtb \
435 sun6i-a31-m9.dtb 461 sun6i-a31-m9.dtb
436dtb-$(CONFIG_MACH_SUN7I) += \ 462dtb-$(CONFIG_MACH_SUN7I) += \
463 sun7i-a20-bananapi.dtb \
437 sun7i-a20-cubieboard2.dtb \ 464 sun7i-a20-cubieboard2.dtb \
438 sun7i-a20-cubietruck.dtb \ 465 sun7i-a20-cubietruck.dtb \
439 sun7i-a20-hummingbird.dtb \ 466 sun7i-a20-hummingbird.dtb \
440 sun7i-a20-i12-tvbox.dtb \ 467 sun7i-a20-i12-tvbox.dtb \
468 sun7i-a20-m3.dtb \
441 sun7i-a20-olinuxino-lime.dtb \ 469 sun7i-a20-olinuxino-lime.dtb \
470 sun7i-a20-olinuxino-lime2.dtb \
442 sun7i-a20-olinuxino-micro.dtb \ 471 sun7i-a20-olinuxino-micro.dtb \
443 sun7i-a20-pcduino3.dtb 472 sun7i-a20-pcduino3.dtb
444dtb-$(CONFIG_MACH_SUN8I) += \ 473dtb-$(CONFIG_MACH_SUN8I) += \
445 sun8i-a23-ippo-q8h-v5.dtb 474 sun8i-a23-ippo-q8h-v5.dtb
475dtb-$(CONFIG_MACH_SUN9I) += \
476 sun9i-a80-optimus.dtb
446dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 477dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
447 tegra20-iris-512.dtb \ 478 tegra20-iris-512.dtb \
448 tegra20-medcom-wide.dtb \ 479 tegra20-medcom-wide.dtb \
@@ -488,13 +519,15 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
488 zynq-parallella.dtb \ 519 zynq-parallella.dtb \
489 zynq-zc702.dtb \ 520 zynq-zc702.dtb \
490 zynq-zc706.dtb \ 521 zynq-zc706.dtb \
491 zynq-zed.dtb 522 zynq-zed.dtb \
523 zynq-zybo.dtb
492dtb-$(CONFIG_MACH_ARMADA_370) += \ 524dtb-$(CONFIG_MACH_ARMADA_370) += \
493 armada-370-db.dtb \ 525 armada-370-db.dtb \
494 armada-370-mirabox.dtb \ 526 armada-370-mirabox.dtb \
495 armada-370-netgear-rn102.dtb \ 527 armada-370-netgear-rn102.dtb \
496 armada-370-netgear-rn104.dtb \ 528 armada-370-netgear-rn104.dtb \
497 armada-370-rd.dtb 529 armada-370-rd.dtb \
530 armada-370-synology-ds213j.dtb
498dtb-$(CONFIG_MACH_ARMADA_375) += \ 531dtb-$(CONFIG_MACH_ARMADA_375) += \
499 armada-375-db.dtb 532 armada-375-db.dtb
500dtb-$(CONFIG_MACH_ARMADA_38X) += \ 533dtb-$(CONFIG_MACH_ARMADA_38X) += \
@@ -507,14 +540,18 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
507 armada-xp-lenovo-ix4-300d.dtb \ 540 armada-xp-lenovo-ix4-300d.dtb \
508 armada-xp-matrix.dtb \ 541 armada-xp-matrix.dtb \
509 armada-xp-netgear-rn2120.dtb \ 542 armada-xp-netgear-rn2120.dtb \
510 armada-xp-openblocks-ax3-4.dtb 543 armada-xp-openblocks-ax3-4.dtb \
544 armada-xp-synology-ds414.dtb
511dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ 545dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
512 dove-cubox.dtb \ 546 dove-cubox.dtb \
513 dove-cubox-es.dtb \ 547 dove-cubox-es.dtb \
514 dove-d2plug.dtb \ 548 dove-d2plug.dtb \
515 dove-d3plug.dtb \ 549 dove-d3plug.dtb \
516 dove-dove-db.dtb 550 dove-dove-db.dtb
517dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb 551dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \
552 mt6592-evb.dtb \
553 mt8127-moose.dtb \
554 mt8135-evbp1.dtb
518 555
519endif 556endif
520 557
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index c4b968f0feb5..54f118c08db8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -307,6 +307,13 @@
307 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 307 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
308 >; 308 >;
309 }; 309 };
310
311 dcan1_pins_default: dcan1_pins_default {
312 pinctrl-single,pins = <
313 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
314 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
315 >;
316 };
310}; 317};
311 318
312&uart0 { 319&uart0 {
@@ -437,9 +444,9 @@
437 status = "okay"; 444 status = "okay";
438 pinctrl-names = "default"; 445 pinctrl-names = "default";
439 pinctrl-0 = <&nandflash_pins_s0>; 446 pinctrl-0 = <&nandflash_pins_s0>;
440 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 447 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
441 nand@0,0 { 448 nand@0,0 {
442 reg = <0 0 0>; /* CS0, offset 0 */ 449 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
443 ti,nand-ecc-opt = "bch8"; 450 ti,nand-ecc-opt = "bch8";
444 ti,elm-id = <&elm>; 451 ti,elm-id = <&elm>;
445 nand-bus-width = <8>; 452 nand-bus-width = <8>;
@@ -664,3 +671,9 @@
664&aes { 671&aes {
665 status = "okay"; 672 status = "okay";
666}; 673};
674
675&dcan1 {
676 status = "disabled"; /* Enable only if Profile 1 is selected */
677 pinctrl-names = "default";
678 pinctrl-0 = <&dcan1_pins_default>;
679};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index a1a0cc5eb35c..c0e1135256cc 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -126,10 +126,10 @@
126 pinctrl-names = "default"; 126 pinctrl-names = "default";
127 pinctrl-0 = <&nandflash_pins>; 127 pinctrl-0 = <&nandflash_pins>;
128 128
129 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 129 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
130 130
131 nand@0,0 { 131 nand@0,0 {
132 reg = <0 0 0>; /* CS0, offset 0 */ 132 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
133 nand-bus-width = <8>; 133 nand-bus-width = <8>;
134 ti,nand-ecc-opt = "bch8"; 134 ti,nand-ecc-opt = "bch8";
135 gpmc,device-width = <1>; 135 gpmc,device-width = <1>;
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
new file mode 100644
index 000000000000..7266a00aab2e
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -0,0 +1,362 @@
1/*
2 * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11
12/ {
13 model = "NovaTech OrionLXm";
14 compatible = "novatech,am335x-lxm", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x20000000>; /* 512 MB */
25 };
26
27 /* Power supply provides a fixed 5V @2A */
28 vbat: fixedregulator@0 {
29 compatible = "regulator-fixed";
30 regulator-name = "vbat";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 regulator-boot-on;
34 };
35
36 /* Power supply provides a fixed 3.3V @3A */
37 vmmcsd_fixed: fixedregulator@1 {
38 compatible = "regulator-fixed";
39 regulator-name = "vmmcsd_fixed";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42 regulator-boot-on;
43 };
44};
45
46&am33xx_pinmux {
47 mmc1_pins: pinmux_mmc1_pins {
48 pinctrl-single,pins = <
49 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
50 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
51 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
52 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
53 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
54 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
55 >;
56 };
57
58 i2c0_pins: pinmux_i2c0_pins {
59 pinctrl-single,pins = <
60 0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
61 0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
62 >;
63 };
64
65 cpsw_default: cpsw_default {
66 pinctrl-single,pins = <
67 /* Slave 1 */
68 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
69 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */
70 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */
71 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
72 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
73 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
74 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */
75 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */
76 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */
77
78 /* Slave 2 */
79 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
80 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
81 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
82 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
83 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
84 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
85 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
86 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
87 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
88 >;
89 };
90
91 cpsw_sleep: cpsw_sleep {
92 pinctrl-single,pins = <
93 /* Slave 1 reset value */
94 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
95 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */
96 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */
97 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */
98 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */
99 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */
100 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */
101 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */
102 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */
103
104 /* Slave 2 reset value*/
105 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */
106 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */
107 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */
108 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */
109 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */
110 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */
111 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */
112 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
113 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */
114 >;
115 };
116
117 davinci_mdio_default: davinci_mdio_default {
118 pinctrl-single,pins = <
119 /* MDIO */
120 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
121 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
122 >;
123 };
124
125 davinci_mdio_sleep: davinci_mdio_sleep {
126 pinctrl-single,pins = <
127 /* MDIO reset value */
128 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 >;
131 };
132
133 emmc_pins: pinmux_emmc_pins {
134 pinctrl-single,pins = <
135 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
136 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
137 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
138 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
139 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
140 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
141 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
142 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
143 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
144 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
145 >;
146 };
147
148 uart0_pins: pinmux_uart0_pins {
149 pinctrl-single,pins = <
150 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
151 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
152 >;
153 };
154};
155
156&i2c0 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&i2c0_pins>;
159
160 status = "okay";
161 clock-frequency = <400000>;
162
163 serial_config1: serial_config1@20 {
164 compatible = "nxp,pca9539";
165 reg = <0x20>;
166 };
167
168 serial_config2: serial_config2@21 {
169 compatible = "nxp,pca9539";
170 reg = <0x21>;
171 };
172
173 tps: tps@2d {
174 compatible = "ti,tps65910";
175 reg = <0x2d>;
176 };
177};
178
179/include/ "tps65910.dtsi"
180
181&tps {
182 vcc1-supply = <&vbat>;
183 vcc2-supply = <&vbat>;
184 vcc3-supply = <&vbat>;
185 vcc4-supply = <&vbat>;
186 vcc5-supply = <&vbat>;
187 vcc6-supply = <&vbat>;
188 vcc7-supply = <&vbat>;
189 vccio-supply = <&vbat>;
190
191 regulators {
192 /* vrtc - unused */
193
194 vio_reg: regulator@1 {
195 regulator-name = "vio_1v5,ddr";
196 regulator-min-microvolt = <1500000>;
197 regulator-max-microvolt = <1500000>;
198 regulator-boot-on;
199 regulator-always-on;
200 };
201
202 vdd1_reg: regulator@2 {
203 regulator-name = "vdd1,mpu";
204 regulator-min-microvolt = <600000>;
205 regulator-max-microvolt = <1500000>;
206 regulator-boot-on;
207 regulator-always-on;
208 };
209
210 vdd2_reg: regulator@3 {
211 regulator-name = "vdd2_1v1,core";
212 regulator-min-microvolt = <1100000>;
213 regulator-max-microvolt = <1100000>;
214 regulator-boot-on;
215 regulator-always-on;
216 };
217
218 /* vdd3 - unused */
219
220 /* vdig1 - unused */
221
222 vdig2_reg: regulator@6 {
223 regulator-name = "vdig2_1v8,vdds_pll";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <1800000>;
226 regulator-boot-on;
227 regulator-always-on;
228 };
229
230 /* vpll - unused */
231
232 vdac_reg: regulator@8 {
233 regulator-name = "vdac_1v8,vdds";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-boot-on;
237 regulator-always-on;
238 };
239
240 vaux1_reg: regulator@9 {
241 regulator-name = "vaux1_1v8,usb";
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <1800000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247
248 vaux2_reg: regulator@10 {
249 regulator-name = "vaux2_3v3,io";
250 regulator-min-microvolt = <3300000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-boot-on;
253 regulator-always-on;
254 };
255
256 vaux33_reg: regulator@11 {
257 regulator-name = "vaux33_3v3,usb";
258 regulator-min-microvolt = <3300000>;
259 regulator-max-microvolt = <3300000>;
260 regulator-boot-on;
261 regulator-always-on;
262 };
263
264 vmmc_reg: regulator@12 {
265 regulator-name = "vmmc_3v3,io";
266 regulator-min-microvolt = <3300000>;
267 regulator-max-microvolt = <3300000>;
268 regulator-boot-on;
269 regulator-always-on;
270 };
271 };
272};
273
274&sham {
275 status = "okay";
276};
277
278&aes {
279 status = "okay";
280};
281
282&uart0 {
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart0_pins>;
285
286 status = "okay";
287};
288
289&usb {
290 status = "okay";
291};
292
293&usb_ctrl_mod {
294 status = "okay";
295};
296
297&usb0_phy {
298 status = "okay";
299};
300
301&usb1_phy {
302 status = "okay";
303};
304
305&usb0 {
306 status = "okay";
307 dr_mode = "host";
308};
309
310&usb1 {
311 status = "okay";
312 dr_mode = "host";
313};
314
315&cppi41dma {
316 status = "okay";
317};
318
319&cpsw_emac0 {
320 phy_id = <&davinci_mdio>, <5>;
321 phy-mode = "rmii";
322 dual_emac_res_vlan = <2>;
323};
324
325&cpsw_emac1 {
326 phy_id = <&davinci_mdio>, <4>;
327 phy-mode = "rmii";
328 dual_emac_res_vlan = <3>;
329};
330
331&mac {
332 pinctrl-names = "default", "sleep";
333 pinctrl-0 = <&cpsw_default>;
334 pinctrl-1 = <&cpsw_sleep>;
335 dual_emac = <1>;
336 status = "okay";
337};
338
339&davinci_mdio {
340 pinctrl-names = "default", "sleep";
341 pinctrl-0 = <&davinci_mdio_default>;
342 pinctrl-1 = <&davinci_mdio_sleep>;
343 status = "okay";
344};
345
346&mmc1 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&mmc1_pins>;
349 vmmc-supply = <&vmmcsd_fixed>;
350 bus-width = <4>;
351 status = "okay";
352};
353
354&mmc2 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&emmc_pins>;
357 vmmc-supply = <&vmmcsd_fixed>;
358 bus-width = <8>;
359 ti,non-removable;
360 status = "okay";
361};
362
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 831810583823..befe713b3e1b 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -83,6 +83,11 @@
83 }; 83 };
84 }; 84 };
85 85
86 am33xx_control_module: control_module@4a002000 {
87 compatible = "syscon";
88 reg = <0x44e10000 0x7fc>;
89 };
90
86 am33xx_pinmux: pinmux@44e10800 { 91 am33xx_pinmux: pinmux@44e10800 {
87 compatible = "pinctrl-single"; 92 compatible = "pinctrl-single";
88 reg = <0x44e10800 0x0238>; 93 reg = <0x44e10800 0x0238>;
@@ -204,6 +209,8 @@
204 reg = <0x44e09000 0x2000>; 209 reg = <0x44e09000 0x2000>;
205 interrupts = <72>; 210 interrupts = <72>;
206 status = "disabled"; 211 status = "disabled";
212 dmas = <&edma 26>, <&edma 27>;
213 dma-names = "tx", "rx";
207 }; 214 };
208 215
209 uart1: serial@48022000 { 216 uart1: serial@48022000 {
@@ -213,6 +220,8 @@
213 reg = <0x48022000 0x2000>; 220 reg = <0x48022000 0x2000>;
214 interrupts = <73>; 221 interrupts = <73>;
215 status = "disabled"; 222 status = "disabled";
223 dmas = <&edma 28>, <&edma 29>;
224 dma-names = "tx", "rx";
216 }; 225 };
217 226
218 uart2: serial@48024000 { 227 uart2: serial@48024000 {
@@ -222,6 +231,8 @@
222 reg = <0x48024000 0x2000>; 231 reg = <0x48024000 0x2000>;
223 interrupts = <74>; 232 interrupts = <74>;
224 status = "disabled"; 233 status = "disabled";
234 dmas = <&edma 30>, <&edma 31>;
235 dma-names = "tx", "rx";
225 }; 236 };
226 237
227 uart3: serial@481a6000 { 238 uart3: serial@481a6000 {
@@ -333,20 +344,24 @@
333 interrupts = <91>; 344 interrupts = <91>;
334 }; 345 };
335 346
336 dcan0: d_can@481cc000 { 347 dcan0: can@481cc000 {
337 compatible = "bosch,d_can"; 348 compatible = "ti,am3352-d_can";
338 ti,hwmods = "d_can0"; 349 ti,hwmods = "d_can0";
339 reg = <0x481cc000 0x2000 350 reg = <0x481cc000 0x2000>;
340 0x44e10644 0x4>; 351 clocks = <&dcan0_fck>;
352 clock-names = "fck";
353 syscon-raminit = <&am33xx_control_module 0x644 0>;
341 interrupts = <52>; 354 interrupts = <52>;
342 status = "disabled"; 355 status = "disabled";
343 }; 356 };
344 357
345 dcan1: d_can@481d0000 { 358 dcan1: can@481d0000 {
346 compatible = "bosch,d_can"; 359 compatible = "ti,am3352-d_can";
347 ti,hwmods = "d_can1"; 360 ti,hwmods = "d_can1";
348 reg = <0x481d0000 0x2000 361 reg = <0x481d0000 0x2000>;
349 0x44e10644 0x4>; 362 clocks = <&dcan1_fck>;
363 clock-names = "fck";
364 syscon-raminit = <&am33xx_control_module 0x644 1>;
350 interrupts = <55>; 365 interrupts = <55>;
351 status = "disabled"; 366 status = "disabled";
352 }; 367 };
@@ -356,6 +371,7 @@
356 reg = <0x480C8000 0x200>; 371 reg = <0x480C8000 0x200>;
357 interrupts = <77>; 372 interrupts = <77>;
358 ti,hwmods = "mailbox"; 373 ti,hwmods = "mailbox";
374 #mbox-cells = <1>;
359 ti,mbox-num-users = <4>; 375 ti,mbox-num-users = <4>;
360 ti,mbox-num-fifos = <8>; 376 ti,mbox-num-fifos = <8>;
361 mbox_wkupm3: wkup_m3 { 377 mbox_wkupm3: wkup_m3 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 46660ffd2b65..d42d7865dd53 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -57,6 +57,11 @@
57 cache-level = <2>; 57 cache-level = <2>;
58 }; 58 };
59 59
60 am43xx_control_module: control_module@4a002000 {
61 compatible = "syscon";
62 reg = <0x44e10000 0x7f4>;
63 };
64
60 am43xx_pinmux: pinmux@44e10800 { 65 am43xx_pinmux: pinmux@44e10800 {
61 compatible = "ti,am437-padconf", "pinctrl-single"; 66 compatible = "ti,am437-padconf", "pinctrl-single";
62 reg = <0x44e10800 0x31c>; 67 reg = <0x44e10800 0x31c>;
@@ -168,6 +173,7 @@
168 reg = <0x480C8000 0x200>; 173 reg = <0x480C8000 0x200>;
169 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
170 ti,hwmods = "mailbox"; 175 ti,hwmods = "mailbox";
176 #mbox-cells = <1>;
171 ti,mbox-num-users = <4>; 177 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <8>; 178 ti,mbox-num-fifos = <8>;
173 mbox_wkupm3: wkup_m3 { 179 mbox_wkupm3: wkup_m3 {
@@ -667,6 +673,26 @@
667 }; 673 };
668 }; 674 };
669 675
676 tscadc: tscadc@44e0d000 {
677 compatible = "ti,am3359-tscadc";
678 reg = <0x44e0d000 0x1000>;
679 ti,hwmods = "adc_tsc";
680 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&adc_tsc_fck>;
682 clock-names = "fck";
683 status = "disabled";
684
685 tsc {
686 compatible = "ti,am3359-tsc";
687 };
688
689 adc {
690 #io-channel-cells = <1>;
691 compatible = "ti,am3359-adc";
692 };
693
694 };
695
670 sham: sham@53100000 { 696 sham: sham@53100000 {
671 compatible = "ti,omap5-sham"; 697 compatible = "ti,omap5-sham";
672 ti,hwmods = "sham"; 698 ti,hwmods = "sham";
@@ -896,6 +922,28 @@
896 compatible = "mmio-sram"; 922 compatible = "mmio-sram";
897 reg = <0x40300000 0x40000>; /* 256k */ 923 reg = <0x40300000 0x40000>; /* 256k */
898 }; 924 };
925
926 dcan0: can@481cc000 {
927 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
928 ti,hwmods = "d_can0";
929 clocks = <&dcan0_fck>;
930 clock-names = "fck";
931 reg = <0x481cc000 0x2000>;
932 syscon-raminit = <&am43xx_control_module 0x644 0>;
933 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
934 status = "disabled";
935 };
936
937 dcan1: can@481d0000 {
938 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
939 ti,hwmods = "d_can1";
940 clocks = <&dcan1_fck>;
941 clock-names = "fck";
942 reg = <0x481d0000 0x2000>;
943 syscon-raminit = <&am43xx_control_module 0x644 1>;
944 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
945 status = "disabled";
946 };
899 }; 947 };
900}; 948};
901 949
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a521ac0a7d5a..7eaae4cf9f89 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -254,6 +254,20 @@
254 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) 254 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
255 >; 255 >;
256 }; 256 };
257
258 dcan0_default: dcan0_default_pins {
259 pinctrl-single,pins = <
260 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
261 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
262 >;
263 };
264
265 dcan1_default: dcan1_default_pins {
266 pinctrl-single,pins = <
267 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
268 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
269 >;
270 };
257}; 271};
258 272
259&i2c0 { 273&i2c0 {
@@ -343,6 +357,14 @@
343 status = "okay"; 357 status = "okay";
344}; 358};
345 359
360&tscadc {
361 status = "okay";
362
363 adc {
364 ti,adc-channels = <0 1 2 3 4 5 6 7>;
365 };
366};
367
346&ecap0 { 368&ecap0 {
347 status = "okay"; 369 status = "okay";
348 pinctrl-names = "default"; 370 pinctrl-names = "default";
@@ -511,3 +533,15 @@
511 }; 533 };
512 }; 534 };
513}; 535};
536
537&dcan0 {
538 pinctrl-names = "default";
539 pinctrl-0 = <&dcan0_default>;
540 status = "okay";
541};
542
543&dcan1 {
544 pinctrl-names = "default";
545 pinctrl-0 = <&dcan1_default>;
546 status = "okay";
547};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index f7e9bba10bd6..662261d6b2ca 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -438,9 +438,9 @@
438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 438 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
439 pinctrl-names = "default"; 439 pinctrl-names = "default";
440 pinctrl-0 = <&nand_flash_x8>; 440 pinctrl-0 = <&nand_flash_x8>;
441 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 441 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
442 nand@0,0 { 442 nand@0,0 {
443 reg = <0 0 0>; /* CS0, offset 0 */ 443 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
444 ti,nand-ecc-opt = "bch16"; 444 ti,nand-ecc-opt = "bch16";
445 ti,elm-id = <&elm>; 445 ti,elm-id = <&elm>;
446 nand-bus-width = <8>; 446 nand-bus-width = <8>;
@@ -519,6 +519,14 @@
519 status = "okay"; 519 status = "okay";
520}; 520};
521 521
522&tscadc {
523 status = "okay";
524
525 adc {
526 ti,adc-channels = <0 1 2 3 4 5 6 7>;
527 };
528};
529
522&ecap0 { 530&ecap0 {
523 status = "okay"; 531 status = "okay";
524 pinctrl-names = "default"; 532 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
new file mode 100644
index 000000000000..49edbda68cd5
--- /dev/null
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -0,0 +1,405 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/clk/ti-dra7-atl.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 model = "TI AM5728 BeagleBoard-X15";
17 compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 aliases {
20 rtc0 = &mcp_rtc;
21 rtc1 = &tps659038_rtc;
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x80000000>;
27 };
28
29 vdd_3v3: fixedregulator-vdd_3v3 {
30 compatible = "regulator-fixed";
31 regulator-name = "vdd_3v3";
32 vin-supply = <&regen1>;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 };
36
37 vtt_fixed: fixedregulator-vtt {
38 /* TPS51200 */
39 compatible = "regulator-fixed";
40 regulator-name = "vtt_fixed";
41 vin-supply = <&smps3_reg>;
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 regulator-always-on;
45 regulator-boot-on;
46 enable-active-high;
47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&leds_pins_default>;
54
55 led@0 {
56 label = "beagle-x15:usr0";
57 gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
58 linux,default-trigger = "heartbeat";
59 default-state = "off";
60 };
61
62 led@1 {
63 label = "beagle-x15:usr1";
64 gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
65 linux,default-trigger = "cpu0";
66 default-state = "off";
67 };
68
69 led@2 {
70 label = "beagle-x15:usr2";
71 gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
72 linux,default-trigger = "mmc0";
73 default-state = "off";
74 };
75
76 led@3 {
77 label = "beagle-x15:usr3";
78 gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
79 linux,default-trigger = "ide-disk";
80 default-state = "off";
81 };
82 };
83};
84
85&dra7_pmx_core {
86 leds_pins_default: leds_pins_default {
87 pinctrl-single,pins = <
88 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
89 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
90 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
91 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
92 >;
93 };
94
95 i2c1_pins_default: i2c1_pins_default {
96 pinctrl-single,pins = <
97 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
98 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
99 >;
100 };
101
102 i2c3_pins_default: i2c3_pins_default {
103 pinctrl-single,pins = <
104 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
105 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
106 >;
107 };
108
109 uart3_pins_default: uart3_pins_default {
110 pinctrl-single,pins = <
111 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
112 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
113 >;
114 };
115
116 mmc1_pins_default: mmc1_pins_default {
117 pinctrl-single,pins = <
118 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
119 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
120 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
121 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
122 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
123 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
124 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
125 >;
126 };
127
128 mmc2_pins_default: mmc2_pins_default {
129 pinctrl-single,pins = <
130 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
131 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
132 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
133 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
134 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
135 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
136 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
137 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
138 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
139 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
140 >;
141 };
142
143 tps659038_pins_default: tps659038_pins_default {
144 pinctrl-single,pins = <
145 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
146 >;
147 };
148
149 tmp102_pins_default: tmp102_pins_default {
150 pinctrl-single,pins = <
151 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
152 >;
153 };
154
155 mcp79410_pins_default: mcp79410_pins_default {
156 pinctrl-single,pins = <
157 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
158 >;
159 };
160
161 usb1_pins: pinmux_usb1_pins {
162 pinctrl-single,pins = <
163 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
164 >;
165 };
166
167};
168
169&i2c1 {
170 status = "okay";
171 pinctrl-names = "default";
172 pinctrl-0 = <&i2c1_pins_default>;
173 clock-frequency = <400000>;
174
175 tps659038: tps659038@58 {
176 compatible = "ti,tps659038";
177 reg = <0x58>;
178 interrupt-parent = <&gpio1>;
179 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
180
181 pinctrl-names = "default";
182 pinctrl-0 = <&tps659038_pins_default>;
183
184 #interrupt-cells = <2>;
185 interrupt-controller;
186
187 ti,system-power-controller;
188
189 tps659038_pmic {
190 compatible = "ti,tps659038-pmic";
191
192 regulators {
193 smps12_reg: smps12 {
194 /* VDD_MPU */
195 regulator-name = "smps12";
196 regulator-min-microvolt = < 850000>;
197 regulator-max-microvolt = <1250000>;
198 regulator-always-on;
199 regulator-boot-on;
200 };
201
202 smps3_reg: smps3 {
203 /* VDD_DDR */
204 regulator-name = "smps3";
205 regulator-min-microvolt = <1350000>;
206 regulator-max-microvolt = <1350000>;
207 regulator-always-on;
208 regulator-boot-on;
209 };
210
211 smps45_reg: smps45 {
212 /* VDD_DSPEVE, VDD_IVA, VDD_GPU */
213 regulator-name = "smps45";
214 regulator-min-microvolt = < 850000>;
215 regulator-max-microvolt = <1150000>;
216 regulator-always-on;
217 regulator-boot-on;
218 };
219
220 smps6_reg: smps6 {
221 /* VDD_CORE */
222 regulator-name = "smps6";
223 regulator-min-microvolt = <850000>;
224 regulator-max-microvolt = <1030000>;
225 regulator-always-on;
226 regulator-boot-on;
227 };
228
229 /* SMPS7 unused */
230
231 smps8_reg: smps8 {
232 /* VDD_1V8 */
233 regulator-name = "smps8";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239
240 /* SMPS9 unused */
241
242 ldo1_reg: ldo1 {
243 /* VDD_SD */
244 regulator-name = "ldo1";
245 regulator-min-microvolt = <1800000>;
246 regulator-max-microvolt = <3300000>;
247 regulator-boot-on;
248 };
249
250 ldo2_reg: ldo2 {
251 /* VDD_SHV5 */
252 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 ldo3_reg: ldo3 {
260 /* VDDA_1V8_PHY */
261 regulator-name = "ldo3";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267
268 ldo9_reg: ldo9 {
269 /* VDD_RTC */
270 regulator-name = "ldo9";
271 regulator-min-microvolt = <1050000>;
272 regulator-max-microvolt = <1050000>;
273 regulator-always-on;
274 regulator-boot-on;
275 };
276
277 ldoln_reg: ldoln {
278 /* VDDA_1V8_PLL */
279 regulator-name = "ldoln";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 regulator-always-on;
283 regulator-boot-on;
284 };
285
286 ldousb_reg: ldousb {
287 /* VDDA_3V_USB: VDDA_USBHS33 */
288 regulator-name = "ldousb";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-boot-on;
292 };
293
294 regen1: regen1 {
295 /* VDD_3V3_ON */
296 regulator-name = "regen1";
297 regulator-boot-on;
298 regulator-always-on;
299 };
300 };
301 };
302
303 tps659038_rtc: tps659038_rtc {
304 compatible = "ti,palmas-rtc";
305 interrupt-parent = <&tps659038>;
306 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
307 wakeup-source;
308 };
309
310 tps659038_pwr_button: tps659038_pwr_button {
311 compatible = "ti,palmas-pwrbutton";
312 interrupt-parent = <&tps659038>;
313 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
314 wakeup-source;
315 ti,palmas-long-press-seconds = <12>;
316 };
317 };
318
319 tmp102: tmp102@48 {
320 compatible = "ti,tmp102";
321 reg = <0x48>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&tmp102_pins_default>;
324 interrupt-parent = <&gpio7>;
325 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
326 };
327};
328
329&i2c3 {
330 status = "okay";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c3_pins_default>;
333 clock-frequency = <400000>;
334
335 mcp_rtc: rtc@6f {
336 compatible = "microchip,mcp7941x";
337 reg = <0x6f>;
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
340
341 pinctrl-names = "default";
342 pinctrl-0 = <&mcp79410_pins_default>;
343
344 vcc-supply = <&vdd_3v3>;
345 wakeup-source;
346 };
347};
348
349&gpio7 {
350 ti,no-reset-on-init;
351 ti,no-idle-on-init;
352};
353
354&cpu0 {
355 cpu0-supply = <&smps12_reg>;
356 voltage-tolerance = <1>;
357};
358
359&uart3 {
360 status = "okay";
361 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
362 <&dra7_pmx_core 0x248>;
363
364 pinctrl-names = "default";
365 pinctrl-0 = <&uart3_pins_default>;
366};
367
368&mmc1 {
369 status = "okay";
370
371 pinctrl-names = "default";
372 pinctrl-0 = <&mmc1_pins_default>;
373
374 vmmc-supply = <&ldo1_reg>;
375 vmmc_aux-supply = <&vdd_3v3>;
376 pbias-supply = <&pbias_mmc_reg>;
377 bus-width = <4>;
378 cd-gpios = <&gpio6 27 0>; /* gpio 219 */
379};
380
381&mmc2 {
382 status = "okay";
383
384 pinctrl-names = "default";
385 pinctrl-0 = <&mmc2_pins_default>;
386
387 vmmc-supply = <&vdd_3v3>;
388 bus-width = <8>;
389 ti,non-removable;
390 cap-mmc-dual-data-rate;
391};
392
393&sata {
394 status = "okay";
395};
396
397&usb2_phy1 {
398 phy-supply = <&ldousb_reg>;
399};
400
401&usb1 {
402 dr_mode = "host";
403 pinctrl-names = "default";
404 pinctrl-0 = <&usb1_pins>;
405};
diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts
new file mode 100644
index 000000000000..ff26c7ed8c41
--- /dev/null
+++ b/arch/arm/boot/dts/arm-realview-pb1176.dts
@@ -0,0 +1,412 @@
1/*
2 * Copyright 2014 Linaro Ltd
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23/dts-v1/;
24#include <dt-bindings/interrupt-controller/irq.h>
25#include <dt-bindings/gpio/gpio.h>
26#include "skeleton.dtsi"
27
28/ {
29 model = "ARM RealView PB1176";
30 compatible = "arm,realview-pb1176";
31
32 chosen { };
33
34 aliases {
35 serial0 = &pb1176_serial0;
36 serial1 = &pb1176_serial1;
37 serial2 = &pb1176_serial2;
38 serial3 = &pb1176_serial3;
39 serial4 = &fpga_serial;
40 };
41
42 memory {
43 /* 128 MiB memory @ 0x0 */
44 reg = <0x00000000 0x08000000>;
45 };
46
47 /* The voltage to the MMC card is hardwired at 3.3V */
48 vmmc: fixedregulator@0 {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 regulator-boot-on;
54 };
55
56 xtal24mhz: xtal24mhz@24M {
57 #clock-cells = <0>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61
62 timclk: timclk@1M {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
65 clock-div = <24>;
66 clock-mult = <1>;
67 clocks = <&xtal24mhz>;
68 };
69
70 mclk: mclk@24M {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clock-div = <1>;
74 clock-mult = <1>;
75 clocks = <&xtal24mhz>;
76 };
77
78 kmiclk: kmiclk@24M {
79 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
81 clock-div = <1>;
82 clock-mult = <1>;
83 clocks = <&xtal24mhz>;
84 };
85
86 sspclk: sspclk@24M {
87 #clock-cells = <0>;
88 compatible = "fixed-factor-clock";
89 clock-div = <1>;
90 clock-mult = <1>;
91 clocks = <&xtal24mhz>;
92 };
93
94 uartclk: uartclk@24M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&xtal24mhz>;
100 };
101
102 /* FIXME: this actually hangs off the PLL clocks */
103 pclk: pclk@0 {
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-frequency = <0>;
107 };
108
109 soc {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "arm,realview-pb1176-soc", "simple-bus";
113 regmap = <&syscon>;
114 ranges;
115
116 syscon: syscon@10000000 {
117 compatible = "arm,realview-pb1176-syscon", "syscon";
118 reg = <0x10000000 0x1000>;
119
120 led@08.0 {
121 compatible = "register-bit-led";
122 offset = <0x08>;
123 mask = <0x01>;
124 label = "versatile:0";
125 linux,default-trigger = "heartbeat";
126 default-state = "on";
127 };
128 led@08.1 {
129 compatible = "register-bit-led";
130 offset = <0x08>;
131 mask = <0x02>;
132 label = "versatile:1";
133 linux,default-trigger = "mmc0";
134 default-state = "off";
135 };
136 led@08.2 {
137 compatible = "register-bit-led";
138 offset = <0x08>;
139 mask = <0x04>;
140 label = "versatile:2";
141 linux,default-trigger = "cpu0";
142 default-state = "off";
143 };
144 led@08.3 {
145 compatible = "register-bit-led";
146 offset = <0x08>;
147 mask = <0x08>;
148 label = "versatile:3";
149 default-state = "off";
150 };
151 led@08.4 {
152 compatible = "register-bit-led";
153 offset = <0x08>;
154 mask = <0x10>;
155 label = "versatile:4";
156 default-state = "off";
157 };
158 led@08.5 {
159 compatible = "register-bit-led";
160 offset = <0x08>;
161 mask = <0x20>;
162 label = "versatile:5";
163 default-state = "off";
164 };
165 led@08.6 {
166 compatible = "register-bit-led";
167 offset = <0x08>;
168 mask = <0x40>;
169 label = "versatile:6";
170 default-state = "off";
171 };
172 led@08.7 {
173 compatible = "register-bit-led";
174 offset = <0x08>;
175 mask = <0x80>;
176 label = "versatile:7";
177 default-state = "off";
178 };
179 };
180
181 /* Primary DevChip GIC synthesized with the CPU */
182 intc_dc1176: interrupt-controller@10120000 {
183 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
184 #interrupt-cells = <3>;
185 #address-cells = <1>;
186 interrupt-controller;
187 reg = <0x10121000 0x1000>,
188 <0x10120000 0x100>;
189 };
190
191 L2: l2-cache {
192 compatible = "arm,l220-cache";
193 reg = <0x10110000 0x1000>;
194 interrupt-parent = <&intc_dc1176>;
195 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
196 cache-unified;
197 cache-level = <2>;
198 /*
199 * Override default cache size, sets and
200 * associativity as these may be erroneously set
201 * up by boot loader(s).
202 */
203 arm,override-auxreg;
204 cache-size = <131072>; // 128kB
205 cache-sets = <512>;
206 cache-line-size = <32>;
207 };
208
209 pmu {
210 compatible = "arm,arm1176-pmu";
211 interrupt-parent = <&intc_dc1176>;
212 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
213 };
214
215 timer01: timer@10104000 {
216 compatible = "arm,sp804", "arm,primecell";
217 reg = <0x10104000 0x1000>;
218 interrupt-parent = <&intc_dc1176>;
219 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&timclk>, <&timclk>, <&pclk>;
221 clock-names = "timer1", "timer2", "apb_pclk";
222 };
223
224 timer23: timer@10105000 {
225 compatible = "arm,sp804", "arm,primecell";
226 reg = <0x10105000 0x1000>;
227 interrupt-parent = <&intc_dc1176>;
228 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
229 arm,sp804-has-irq = <1>;
230 clocks = <&timclk>, <&timclk>, <&pclk>;
231 clock-names = "timer1", "timer2", "apb_pclk";
232 };
233
234 pb1176_rtc: rtc@10108000 {
235 compatible = "arm,pl031", "arm,primecell";
236 reg = <0x10108000 0x1000>;
237 interrupt-parent = <&intc_dc1176>;
238 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&pclk>;
240 clock-names = "apb_pclk";
241 };
242
243 pb1176_gpio0: gpio@1010a000 {
244 compatible = "arm,pl061", "arm,primecell";
245 reg = <0x1010a000 0x1000>;
246 gpio-controller;
247 interrupt-parent = <&intc_dc1176>;
248 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
252 clocks = <&pclk>;
253 clock-names = "apb_pclk";
254 };
255
256 pb1176_ssp: ssp@1010b000 {
257 compatible = "arm,pl022", "arm,primecell";
258 reg = <0x1010b000 0x1000>;
259 interrupt-parent = <&intc_dc1176>;
260 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&sspclk>, <&pclk>;
262 clock-names = "SSPCLK", "apb_pclk";
263 };
264
265 pb1176_serial0: serial@1010c000 {
266 compatible = "arm,pl011", "arm,primecell";
267 reg = <0x1010c000 0x1000>;
268 interrupt-parent = <&intc_dc1176>;
269 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&uartclk>, <&pclk>;
271 clock-names = "uartclk", "apb_pclk";
272 };
273
274 pb1176_serial1: serial@1010d000 {
275 compatible = "arm,pl011", "arm,primecell";
276 reg = <0x1010d000 0x1000>;
277 interrupt-parent = <&intc_dc1176>;
278 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&uartclk>, <&pclk>;
280 clock-names = "uartclk", "apb_pclk";
281 };
282
283 pb1176_serial2: serial@1010e000 {
284 compatible = "arm,pl011", "arm,primecell";
285 reg = <0x1010e000 0x1000>;
286 interrupt-parent = <&intc_dc1176>;
287 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&uartclk>, <&pclk>;
289 clock-names = "uartclk", "apb_pclk";
290 };
291
292 pb1176_serial3: serial@1010f000 {
293 compatible = "arm,pl011", "arm,primecell";
294 reg = <0x1010f000 0x1000>;
295 interrupt-parent = <&intc_dc1176>;
296 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&uartclk>, <&pclk>;
298 clock-names = "uartclk", "apb_pclk";
299 };
300 };
301
302 /* These peripherals are inside the FPGA rather than the DevChip */
303 fpga {
304 #address-cells = <1>;
305 #size-cells = <1>;
306 compatible = "simple-bus";
307 ranges;
308
309 fpga_mci: mmcsd@10005000 {
310 compatible = "arm,pl18x", "arm,primecell";
311 reg = <0x10005000 0x1000>;
312 interrupt-parent = <&intc_fpga1176>;
313 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
314 <0 2 IRQ_TYPE_LEVEL_HIGH>;
315 /* Due to frequent FIFO overruns, use just 500 kHz */
316 max-frequency = <500000>;
317 bus-width = <4>;
318 cap-sd-highspeed;
319 cap-mmc-highspeed;
320 clocks = <&mclk>, <&pclk>;
321 clock-names = "mclk", "apb_pclk";
322 vmmc-supply = <&vmmc>;
323 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
324 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
325 };
326
327 fpga_kmi0: kmi@10006000 {
328 compatible = "arm,pl050", "arm,primecell";
329 reg = <0x10006000 0x1000>;
330 interrupt-parent = <&intc_fpga1176>;
331 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&kmiclk>, <&pclk>;
333 clock-names = "KMIREFCLK", "apb_pclk";
334 };
335
336 fpga_kmi1: kmi@10007000 {
337 compatible = "arm,pl050", "arm,primecell";
338 reg = <0x10007000 0x1000>;
339 interrupt-parent = <&intc_fpga1176>;
340 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&kmiclk>, <&pclk>;
342 clock-names = "KMIREFCLK", "apb_pclk";
343 };
344
345 fpga_charlcd: charlcd@10008000 {
346 compatible = "arm,versatile-lcd";
347 reg = <0x10008000 0x1000>;
348 interrupt-parent = <&intc_fpga1176>;
349 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&pclk>;
351 clock-names = "apb_pclk";
352 };
353
354 fpga_serial: serial@10009000 {
355 compatible = "arm,pl011", "arm,primecell";
356 reg = <0x10009000 0x1000>;
357 interrupt-parent = <&intc_fpga1176>;
358 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&uartclk>, <&pclk>;
360 clock-names = "uartclk", "apb_pclk";
361 };
362
363 /* This GIC on the board is cascaded off the DevChip GIC */
364 intc_fpga1176: interrupt-controller@10040000 {
365 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
366 #interrupt-cells = <3>;
367 #address-cells = <1>;
368 interrupt-controller;
369 reg = <0x10041000 0x1000>,
370 <0x10040000 0x100>;
371 interrupt-parent = <&intc_dc1176>;
372 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
373 };
374
375 fpga_gpio0: gpio@10014000 {
376 compatible = "arm,pl061", "arm,primecell";
377 reg = <0x10014000 0x1000>;
378 gpio-controller;
379 interrupt-parent = <&intc_fpga1176>;
380 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 clocks = <&pclk>;
385 clock-names = "apb_pclk";
386 };
387
388 fpga_gpio1: gpio@10015000 {
389 compatible = "arm,pl061", "arm,primecell";
390 reg = <0x10015000 0x1000>;
391 gpio-controller;
392 interrupt-parent = <&intc_fpga1176>;
393 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
394 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 clocks = <&pclk>;
398 clock-names = "apb_pclk";
399 };
400
401 fpga_rtc: rtc@10017000 {
402 compatible = "arm,pl031", "arm,primecell";
403 reg = <0x10017000 0x1000>;
404 interrupt-parent = <&intc_fpga1176>;
405 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&pclk>;
407 clock-names = "apb_pclk";
408 };
409
410
411 };
412};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index a495e5821ab8..1466580be295 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -75,6 +75,7 @@
75 clock-frequency = <100000>; 75 clock-frequency = <100000>;
76 status = "okay"; 76 status = "okay";
77 audio_codec: audio-codec@4a { 77 audio_codec: audio-codec@4a {
78 #sound-dai-cells = <0>;
78 compatible = "cirrus,cs42l51"; 79 compatible = "cirrus,cs42l51";
79 reg = <0x4a>; 80 reg = <0x4a>;
80 }; 81 };
@@ -102,30 +103,6 @@
102 broken-cd; 103 broken-cd;
103 }; 104 };
104 105
105 pinctrl {
106 /*
107 * These pins might be muxed as I2S by
108 * the bootloader, but it conflicts
109 * with the real I2S pins that are
110 * muxed using i2s_pins. We must mux
111 * those pins to a function other than
112 * I2S.
113 */
114 pinctrl-0 = <&hog_pins1 &hog_pins2>;
115 pinctrl-names = "default";
116
117 hog_pins1: hog-pins1 {
118 marvell,pins = "mpp6", "mpp8", "mpp10",
119 "mpp12", "mpp13";
120 marvell,function = "gpio";
121 };
122
123 hog_pins2: hog-pins2 {
124 marvell,pins = "mpp5", "mpp7", "mpp9";
125 marvell,function = "gpo";
126 };
127 };
128
129 usb@50000 { 106 usb@50000 {
130 status = "okay"; 107 status = "okay";
131 }; 108 };
@@ -135,6 +112,8 @@
135 }; 112 };
136 113
137 spi0: spi@10600 { 114 spi0: spi@10600 {
115 pinctrl-0 = <&spi0_pins2>;
116 pinctrl-names = "default";
138 status = "okay"; 117 status = "okay";
139 118
140 spi-flash@0 { 119 spi-flash@0 {
@@ -167,17 +146,84 @@
167 }; 146 };
168 147
169 sound { 148 sound {
170 compatible = "marvell,a370db-audio"; 149 compatible = "simple-audio-card";
171 marvell,audio-controller = <&audio_controller>; 150 simple-audio-card,name = "Armada 370 DB Audio";
172 marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; 151 simple-audio-card,mclk-fs = <256>;
173 status = "okay"; 152 simple-audio-card,widgets =
153 "Headphone", "Out Jack",
154 "Line", "In Jack";
155 simple-audio-card,routing =
156 "Out Jack", "HPL",
157 "Out Jack", "HPR",
158 "AIN1L", "In Jack",
159 "AIN1L", "In Jack";
160 status = "okay";
161
162 simple-audio-card,dai-link@0 {
163 format = "i2s";
164 cpu {
165 sound-dai = <&audio_controller 0>;
166 };
167
168 codec {
169 sound-dai = <&audio_codec>;
170 };
171 };
172
173 simple-audio-card,dai-link@1 {
174 format = "i2s";
175 cpu {
176 sound-dai = <&audio_controller 1>;
177 };
178
179 codec {
180 sound-dai = <&spdif_out>;
181 };
182 };
183
184 simple-audio-card,dai-link@2 {
185 format = "i2s";
186 cpu {
187 sound-dai = <&audio_controller 1>;
188 };
189
190 codec {
191 sound-dai = <&spdif_in>;
192 };
193 };
174 }; 194 };
175 195
176 spdif_out: spdif-out { 196 spdif_out: spdif-out {
177 compatible = "linux,spdif-dit"; 197 #sound-dai-cells = <0>;
198 compatible = "linux,spdif-dit";
178 }; 199 };
179 200
180 spdif_in: spdif-in { 201 spdif_in: spdif-in {
181 compatible = "linux,spdif-dir"; 202 #sound-dai-cells = <0>;
203 compatible = "linux,spdif-dir";
204 };
205};
206
207&pinctrl {
208 /*
209 * These pins might be muxed as I2S by
210 * the bootloader, but it conflicts
211 * with the real I2S pins that are
212 * muxed using i2s_pins. We must mux
213 * those pins to a function other than
214 * I2S.
215 */
216 pinctrl-0 = <&hog_pins1 &hog_pins2>;
217 pinctrl-names = "default";
218
219 hog_pins1: hog-pins1 {
220 marvell,pins = "mpp6", "mpp8", "mpp10",
221 "mpp12", "mpp13";
222 marvell,function = "gpio";
223 };
224
225 hog_pins2: hog-pins2 {
226 marvell,pins = "mpp5", "mpp7", "mpp9";
227 marvell,function = "gpo";
182 }; 228 };
183}; 229};
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2b6d24e0d1e8..e1b0eb6b091f 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -54,18 +54,6 @@
54 status = "okay"; 54 status = "okay";
55 }; 55 };
56 56
57 pinctrl {
58 pwr_led_pin: pwr-led-pin {
59 marvell,pins = "mpp63";
60 marvell,function = "gpo";
61 };
62
63 stat_led_pins: stat-led-pins {
64 marvell,pins = "mpp64", "mpp65";
65 marvell,function = "gpio";
66 };
67 };
68
69 gpio_leds { 57 gpio_leds {
70 compatible = "gpio-leds"; 58 compatible = "gpio-leds";
71 pinctrl-names = "default"; 59 pinctrl-names = "default";
@@ -169,3 +157,16 @@
169 }; 157 };
170 }; 158 };
171}; 159};
160
161&pinctrl {
162 pwr_led_pin: pwr-led-pin {
163 marvell,pins = "mpp63";
164 marvell,function = "gpo";
165 };
166
167 stat_led_pins: stat-led-pins {
168 marvell,pins = "mpp64", "mpp65";
169 marvell,function = "gpio";
170 };
171};
172
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 3aebd93cc33c..4e24932c6e30 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -35,7 +35,7 @@
35 pcie-controller { 35 pcie-controller {
36 status = "okay"; 36 status = "okay";
37 37
38 /* Connected to Marvell SATA controller */ 38 /* Connected to Marvell 88SE9170 SATA controller */
39 pcie@1,0 { 39 pcie@1,0 {
40 /* Port 0, Lane 0 */ 40 /* Port 0, Lane 0 */
41 status = "okay"; 41 status = "okay";
@@ -53,53 +53,12 @@
53 status = "okay"; 53 status = "okay";
54 }; 54 };
55 55
56 /* eSATA interface */
56 sata@a0000 { 57 sata@a0000 {
57 nr-ports = <2>; 58 nr-ports = <1>;
58 status = "okay"; 59 status = "okay";
59 }; 60 };
60 61
61 pinctrl {
62 power_led_pin: power-led-pin {
63 marvell,pins = "mpp57";
64 marvell,function = "gpio";
65 };
66
67 sata1_led_pin: sata1-led-pin {
68 marvell,pins = "mpp15";
69 marvell,function = "gpio";
70 };
71
72 sata2_led_pin: sata2-led-pin {
73 marvell,pins = "mpp14";
74 marvell,function = "gpio";
75 };
76
77 backup_led_pin: backup-led-pin {
78 marvell,pins = "mpp56";
79 marvell,function = "gpio";
80 };
81
82 backup_button_pin: backup-button-pin {
83 marvell,pins = "mpp58";
84 marvell,function = "gpio";
85 };
86
87 power_button_pin: power-button-pin {
88 marvell,pins = "mpp62";
89 marvell,function = "gpio";
90 };
91
92 reset_button_pin: reset-button-pin {
93 marvell,pins = "mpp6";
94 marvell,function = "gpio";
95 };
96
97 poweroff: poweroff {
98 marvell,pins = "mpp8";
99 marvell,function = "gpio";
100 };
101 };
102
103 mdio { 62 mdio {
104 pinctrl-0 = <&mdio_pins>; 63 pinctrl-0 = <&mdio_pins>;
105 pinctrl-names = "default"; 64 pinctrl-names = "default";
@@ -204,20 +163,20 @@
204 default-state = "keep"; 163 default-state = "keep";
205 }; 164 };
206 165
207 green-sata1-led { 166 blue-sata1-led {
208 label = "rn102:green:sata1"; 167 label = "rn102:blue:sata1";
209 gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; 168 gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
210 default-state = "on"; 169 default-state = "on";
211 }; 170 };
212 171
213 green-sata2-led { 172 blue-sata2-led {
214 label = "rn102:green:sata2"; 173 label = "rn102:blue:sata2";
215 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 174 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
216 default-state = "on"; 175 default-state = "on";
217 }; 176 };
218 177
219 green-backup-led { 178 blue-backup-led {
220 label = "rn102:green:backup"; 179 label = "rn102:blue:backup";
221 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; 180 gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
222 default-state = "on"; 181 default-state = "on";
223 }; 182 };
@@ -256,3 +215,45 @@
256 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; 215 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
257 }; 216 };
258}; 217};
218
219&pinctrl {
220 power_led_pin: power-led-pin {
221 marvell,pins = "mpp57";
222 marvell,function = "gpio";
223 };
224
225 sata1_led_pin: sata1-led-pin {
226 marvell,pins = "mpp15";
227 marvell,function = "gpio";
228 };
229
230 sata2_led_pin: sata2-led-pin {
231 marvell,pins = "mpp14";
232 marvell,function = "gpio";
233 };
234
235 backup_led_pin: backup-led-pin {
236 marvell,pins = "mpp56";
237 marvell,function = "gpio";
238 };
239
240 backup_button_pin: backup-button-pin {
241 marvell,pins = "mpp58";
242 marvell,function = "gpio";
243 };
244
245 power_button_pin: power-button-pin {
246 marvell,pins = "mpp62";
247 marvell,function = "gpio";
248 };
249
250 reset_button_pin: reset-button-pin {
251 marvell,pins = "mpp6";
252 marvell,function = "gpio";
253 };
254
255 poweroff: poweroff {
256 marvell,pins = "mpp8";
257 marvell,function = "gpio";
258 };
259};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index c2f414bb9aba..30586e47986a 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -53,38 +53,6 @@
53 status = "okay"; 53 status = "okay";
54 }; 54 };
55 55
56 pinctrl {
57 poweroff: poweroff {
58 marvell,pins = "mpp60";
59 marvell,function = "gpio";
60 };
61
62 backup_button_pin: backup-button-pin {
63 marvell,pins = "mpp52";
64 marvell,function = "gpio";
65 };
66
67 power_button_pin: power-button-pin {
68 marvell,pins = "mpp62";
69 marvell,function = "gpio";
70 };
71
72 backup_led_pin: backup-led-pin {
73 marvell,pins = "mpp63";
74 marvell,function = "gpo";
75 };
76
77 power_led_pin: power-led-pin {
78 marvell,pins = "mpp64";
79 marvell,function = "gpio";
80 };
81
82 reset_button_pin: reset-button-pin {
83 marvell,pins = "mpp65";
84 marvell,function = "gpio";
85 };
86 };
87
88 mdio { 56 mdio {
89 pinctrl-0 = <&mdio_pins>; 57 pinctrl-0 = <&mdio_pins>;
90 pinctrl-names = "default"; 58 pinctrl-names = "default";
@@ -269,3 +237,35 @@
269 gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; 237 gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
270 }; 238 };
271}; 239};
240
241&pinctrl {
242 poweroff: poweroff {
243 marvell,pins = "mpp60";
244 marvell,function = "gpio";
245 };
246
247 backup_button_pin: backup-button-pin {
248 marvell,pins = "mpp52";
249 marvell,function = "gpio";
250 };
251
252 power_button_pin: power-button-pin {
253 marvell,pins = "mpp62";
254 marvell,function = "gpio";
255 };
256
257 backup_led_pin: backup-led-pin {
258 marvell,pins = "mpp63";
259 marvell,function = "gpo";
260 };
261
262 power_led_pin: power-led-pin {
263 marvell,pins = "mpp64";
264 marvell,function = "gpio";
265 };
266
267 reset_button_pin: reset-button-pin {
268 marvell,pins = "mpp65";
269 marvell,function = "gpio";
270 };
271};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index f57a8f841498..394308951ed9 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -59,18 +59,6 @@
59 }; 59 };
60 60
61 internal-regs { 61 internal-regs {
62 pinctrl {
63 fan_pins: fan-pins {
64 marvell,pins = "mpp8";
65 marvell,function = "gpio";
66 };
67
68 led_pins: led-pins {
69 marvell,pins = "mpp32";
70 marvell,function = "gpio";
71 };
72 };
73
74 serial@12000 { 62 serial@12000 {
75 status = "okay"; 63 status = "okay";
76 }; 64 };
@@ -85,10 +73,6 @@
85 phy0: ethernet-phy@0 { 73 phy0: ethernet-phy@0 {
86 reg = <0>; 74 reg = <0>;
87 }; 75 };
88
89 phy1: ethernet-phy@1 {
90 reg = <1>;
91 };
92 }; 76 };
93 77
94 ethernet@70000 { 78 ethernet@70000 {
@@ -100,8 +84,11 @@
100 pinctrl-0 = <&ge1_rgmii_pins>; 84 pinctrl-0 = <&ge1_rgmii_pins>;
101 pinctrl-names = "default"; 85 pinctrl-names = "default";
102 status = "okay"; 86 status = "okay";
103 phy = <&phy1>;
104 phy-mode = "rgmii-id"; 87 phy-mode = "rgmii-id";
88 fixed-link {
89 speed = <1000>;
90 full-duplex;
91 };
105 }; 92 };
106 93
107 mvsdio@d4000 { 94 mvsdio@d4000 {
@@ -173,4 +160,56 @@
173 }; 160 };
174 }; 161 };
175 }; 162 };
163
164 dsa@0 {
165 compatible = "marvell,dsa";
166 #address-cells = <2>;
167 #size-cells = <0>;
168
169 dsa,ethernet = <&eth1>;
170 dsa,mii-bus = <&mdio>;
171
172 switch@0 {
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
176
177 port@0 {
178 reg = <0>;
179 label = "lan0";
180 };
181
182 port@1 {
183 reg = <1>;
184 label = "lan1";
185 };
186
187 port@2 {
188 reg = <2>;
189 label = "lan2";
190 };
191
192 port@3 {
193 reg = <3>;
194 label = "lan3";
195 };
196
197 port@5 {
198 reg = <5>;
199 label = "cpu";
200 };
201 };
202 };
176 }; 203 };
204
205&pinctrl {
206 fan_pins: fan-pins {
207 marvell,pins = "mpp8";
208 marvell,function = "gpio";
209 };
210
211 led_pins: led-pins {
212 marvell,pins = "mpp32";
213 marvell,function = "gpio";
214 };
215};
diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
new file mode 100644
index 000000000000..70fecde76ccb
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts
@@ -0,0 +1,316 @@
1/*
2 * Device Tree file for Synology DS213j
3 *
4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Note: this Device Tree assumes that the bootloader has remapped the
12 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
14 * bootloaders provided by Marvell. It is used in recent versions of
15 * DSM software provided by Synology. Nonetheless, some earlier boards
16 * were delivered with an older version of u-boot that left internal
17 * registers mapped at 0xd0000000. If you have such a device you will
18 * not be able to directly boot a kernel based on this Device Tree. In
19 * that case, the preferred solution is to update your bootloader (e.g.
20 * by upgrading to latest version of DSM, or building a new one and
21 * installing it from u-boot prompt) or adjust the Devive Tree
22 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
23 */
24
25/dts-v1/;
26
27#include <dt-bindings/input/input.h>
28#include <dt-bindings/gpio/gpio.h>
29#include "armada-370.dtsi"
30
31/ {
32 model = "Synology DS213j";
33 compatible = "synology,ds213j", "marvell,armada370",
34 "marvell,armada-370-xp";
35
36 chosen {
37 bootargs = "console=ttyS0,115200 earlyprintk";
38 stdout-path = &uart0;
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x20000000>; /* 512 MB */
44 };
45
46 soc {
47 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
48 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
49
50 internal-regs {
51
52 /* RTC provided by Seiko S-35390A I2C RTC chip below */
53 rtc@10300 {
54 status = "disabled";
55 };
56
57 spi0: spi@10600 {
58 status = "okay";
59
60 spi-flash@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "micron,n25q064";
64 reg = <0>; /* Chip select 0 */
65 spi-max-frequency = <20000000>;
66
67 /*
68 * Warning!
69 *
70 * Synology u-boot uses its compiled-in environment
71 * and it seems Synology did not care to change u-boot
72 * default configuration in order to allow saving a
73 * modified environment at a sensible location. So,
74 * if you do a 'saveenv' under u-boot, your modified
75 * environment will be saved at 1MB after the start
76 * of the flash, i.e. in the middle of the uImage.
77 * For that reason, it is strongly advised not to
78 * change the default environment, unless you know
79 * what you are doing.
80 */
81 partition@00000000 { /* u-boot */
82 label = "RedBoot";
83 reg = <0x00000000 0x000c0000>; /* 768KB */
84 };
85
86 partition@000c0000 { /* uImage */
87 label = "zImage";
88 reg = <0x000c0000 0x002d0000>; /* 2880KB */
89 };
90
91 partition@00390000 { /* uInitramfs */
92 label = "rd.gz";
93 reg = <0x00390000 0x00440000>; /* 4250KB */
94 };
95
96 partition@007d0000 { /* MAC address and serial number */
97 label = "vendor";
98 reg = <0x007d0000 0x00010000>; /* 64KB */
99 };
100
101 partition@007e0000 {
102 label = "RedBoot config";
103 reg = <0x007e0000 0x00010000>; /* 64KB */
104 };
105
106 partition@007f0000 {
107 label = "FIS directory";
108 reg = <0x007f0000 0x00010000>; /* 64KB */
109 };
110 };
111 };
112
113 i2c@11000 {
114 compatible = "marvell,mv64xxx-i2c";
115 pinctrl-0 = <&i2c0_pins>;
116 pinctrl-names = "default";
117 clock-frequency = <400000>;
118 status = "okay";
119
120 /* Main device RTC chip */
121 s35390a: s35390a@30 {
122 compatible = "sii,s35390a";
123 reg = <0x30>;
124 };
125 };
126
127 /* Connected to a header on device's PCB */
128 serial@12000 {
129 status = "okay";
130 };
131
132 /* Connected to a TI MSP430F2111 for power control */
133 serial@12100 {
134 status = "okay";
135 };
136
137 poweroff@12100 {
138 compatible = "synology,power-off";
139 reg = <0x12100 0x100>;
140 clocks = <&coreclk 0>;
141 };
142
143 /* rear USB port, near reset button */
144 usb@50000 {
145 status = "okay";
146 };
147
148 /* rear USB port, near RJ45 port */
149 usb@51000 {
150 status = "okay";
151 };
152
153 mdio {
154 phy1: ethernet-phy@1 { /* Marvell 88E1512 */
155 reg = <1>;
156 };
157 };
158
159 ethernet@70000 {
160 status = "okay";
161 phy = <&phy1>;
162 phy-mode = "sgmii";
163 };
164
165 sata@a0000 {
166 nr-ports = <2>;
167 status = "okay";
168 };
169 };
170 };
171
172 gpio-fan-32-38 {
173 status = "okay";
174 compatible = "gpio-fan";
175 pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin
176 &fan_ctrl_high_pin &fan_alarm_pin>;
177 pinctrl-names = "default";
178 gpios = <&gpio1 31 GPIO_ACTIVE_HIGH
179 &gpio2 0 GPIO_ACTIVE_HIGH
180 &gpio2 1 GPIO_ACTIVE_HIGH>;
181 alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
182 gpio-fan,speed-map = < 0 0
183 1000 1
184 1150 2
185 1350 4
186 1500 3
187 1650 5
188 1750 6
189 1900 7 >;
190 };
191
192 gpio-leds {
193 compatible = "gpio-leds";
194 pinctrl-0 = <&disk1_led_pin
195 &disk2_led_pin>;
196 pinctrl-names = "default";
197
198 disk1-led-amber {
199 label = "synology:amber:disk1";
200 gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
201 default-state = "keep";
202 };
203
204 disk2-led-amber {
205 label = "synology:amber:disk2";
206 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
207 default-state = "keep";
208 };
209 };
210
211 regulators {
212 compatible = "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
216 pinctrl-names = "default";
217
218 sata1_regulator: sata1-regulator {
219 compatible = "regulator-fixed";
220 reg = <1>;
221 regulator-name = "SATA1 Power";
222 regulator-min-microvolt = <5000000>;
223 regulator-max-microvolt = <5000000>;
224 startup-delay-us = <2000000>;
225 enable-active-high;
226 regulator-always-on;
227 regulator-boot-on;
228 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
229 };
230
231 sata2_regulator: sata2-regulator {
232 compatible = "regulator-fixed";
233 reg = <2>;
234 regulator-name = "SATA2 Power";
235 regulator-min-microvolt = <5000000>;
236 regulator-max-microvolt = <5000000>;
237 startup-delay-us = <4000000>;
238 enable-active-high;
239 regulator-always-on;
240 regulator-boot-on;
241 gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
242 };
243 };
244};
245
246&pinctrl {
247 disk1_led_pin: disk1-led-pin {
248 marvell,pins = "mpp31";
249 marvell,function = "gpio";
250 };
251
252 disk2_led_pin: disk2-led-pin {
253 marvell,pins = "mpp32";
254 marvell,function = "gpio";
255 };
256
257 sata1_pwr_pin: sata1-pwr-pin {
258 marvell,pins = "mpp37";
259 marvell,function = "gpio";
260 };
261
262 sata2_pwr_pin: sata2-pwr-pin {
263 marvell,pins = "mpp62";
264 marvell,function = "gpio";
265 };
266
267 sata1_pres_pin: sata1-pres-pin {
268 marvell,pins = "mpp60";
269 marvell,function = "gpio";
270 };
271
272 sata2_pres_pin: sata2-pres-pin {
273 marvell,pins = "mpp48";
274 marvell,function = "gpio";
275 };
276
277 syno_id_bit0_pin: syno-id-bit0-pin {
278 marvell,pins = "mpp55";
279 marvell,function = "gpio";
280 };
281
282 syno_id_bit1_pin: syno-id-bit1-pin {
283 marvell,pins = "mpp56";
284 marvell,function = "gpio";
285 };
286
287 syno_id_bit2_pin: syno-id-bit2-pin {
288 marvell,pins = "mpp57";
289 marvell,function = "gpio";
290 };
291
292 syno_id_bit3_pin: syno-id-bit3-pin {
293 marvell,pins = "mpp58";
294 marvell,function = "gpio";
295 };
296
297 fan_ctrl_low_pin: fan-ctrl-low-pin {
298 marvell,pins = "mpp65";
299 marvell,function = "gpio";
300 };
301
302 fan_ctrl_mid_pin: fan-ctrl-mid-pin {
303 marvell,pins = "mpp64";
304 marvell,function = "gpio";
305 };
306
307 fan_ctrl_high_pin: fan-ctrl-high-pin {
308 marvell,pins = "mpp63";
309 marvell,function = "gpo";
310 };
311
312 fan_alarm_pin: fan-alarm-pin {
313 marvell,pins = "mpp38";
314 marvell,function = "gpio";
315 };
316};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90dba78554c8..1af428602748 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -151,7 +151,7 @@
151 status = "disabled"; 151 status = "disabled";
152 }; 152 };
153 153
154 serial@12000 { 154 uart0: serial@12000 {
155 compatible = "snps,dw-apb-uart"; 155 compatible = "snps,dw-apb-uart";
156 reg = <0x12000 0x100>; 156 reg = <0x12000 0x100>;
157 reg-shift = <2>; 157 reg-shift = <2>;
@@ -160,7 +160,8 @@
160 clocks = <&coreclk 0>; 160 clocks = <&coreclk 0>;
161 status = "disabled"; 161 status = "disabled";
162 }; 162 };
163 serial@12100 { 163
164 uart1: serial@12100 {
164 compatible = "snps,dw-apb-uart"; 165 compatible = "snps,dw-apb-uart";
165 reg = <0x12100 0x100>; 166 reg = <0x12100 0x100>;
166 reg-shift = <2>; 167 reg-shift = <2>;
@@ -170,6 +171,10 @@
170 status = "disabled"; 171 status = "disabled";
171 }; 172 };
172 173
174 pinctrl: pin-ctrl@18000 {
175 reg = <0x18000 0x38>;
176 };
177
173 coredivclk: corediv-clock@18740 { 178 coredivclk: corediv-clock@18740 {
174 compatible = "marvell,armada-370-corediv-clock"; 179 compatible = "marvell,armada-370-corediv-clock";
175 reg = <0x18740 0xc>; 180 reg = <0x18740 0xc>;
@@ -233,7 +238,7 @@
233 status = "disabled"; 238 status = "disabled";
234 }; 239 };
235 240
236 mdio { 241 mdio: mdio {
237 #address-cells = <1>; 242 #address-cells = <1>;
238 #size-cells = <0>; 243 #size-cells = <0>;
239 compatible = "marvell,orion-mdio"; 244 compatible = "marvell,orion-mdio";
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 6b3c23b1e138..fdb3c12a6139 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -95,81 +95,30 @@
95 compatible = "marvell,aurora-outer-cache"; 95 compatible = "marvell,aurora-outer-cache";
96 reg = <0x08000 0x1000>; 96 reg = <0x08000 0x1000>;
97 cache-id-part = <0x100>; 97 cache-id-part = <0x100>;
98 cache-unified;
98 wt-override; 99 wt-override;
99 }; 100 };
100 101
101 i2c0: i2c@11000 { 102 /*
102 reg = <0x11000 0x20>; 103 * Default SPI pinctrl setting, can be overwritten on
104 * board level if a different configuration is used.
105 */
106 spi0: spi@10600 {
107 pinctrl-0 = <&spi0_pins1>;
108 pinctrl-names = "default";
103 }; 109 };
104 110
105 i2c1: i2c@11100 { 111 spi1: spi@10680 {
106 reg = <0x11100 0x20>; 112 pinctrl-0 = <&spi1_pins>;
113 pinctrl-names = "default";
107 }; 114 };
108 115
109 system-controller@18200 { 116 i2c0: i2c@11000 {
110 compatible = "marvell,armada-370-xp-system-controller"; 117 reg = <0x11000 0x20>;
111 reg = <0x18200 0x100>;
112 }; 118 };
113 119
114 pinctrl { 120 i2c1: i2c@11100 {
115 compatible = "marvell,mv88f6710-pinctrl"; 121 reg = <0x11100 0x20>;
116 reg = <0x18000 0x38>;
117
118 sdio_pins1: sdio-pins1 {
119 marvell,pins = "mpp9", "mpp11", "mpp12",
120 "mpp13", "mpp14", "mpp15";
121 marvell,function = "sd0";
122 };
123
124 sdio_pins2: sdio-pins2 {
125 marvell,pins = "mpp47", "mpp48", "mpp49",
126 "mpp50", "mpp51", "mpp52";
127 marvell,function = "sd0";
128 };
129
130 sdio_pins3: sdio-pins3 {
131 marvell,pins = "mpp48", "mpp49", "mpp50",
132 "mpp51", "mpp52", "mpp53";
133 marvell,function = "sd0";
134 };
135
136 i2c0_pins: i2c0-pins {
137 marvell,pins = "mpp2", "mpp3";
138 marvell,function = "i2c0";
139 };
140
141 i2s_pins1: i2s-pins1 {
142 marvell,pins = "mpp5", "mpp6", "mpp7",
143 "mpp8", "mpp9", "mpp10",
144 "mpp12", "mpp13";
145 marvell,function = "audio";
146 };
147
148 i2s_pins2: i2s-pins2 {
149 marvell,pins = "mpp49", "mpp47", "mpp50",
150 "mpp59", "mpp57", "mpp61",
151 "mpp62", "mpp60", "mpp58";
152 marvell,function = "audio";
153 };
154
155 mdio_pins: mdio-pins {
156 marvell,pins = "mpp17", "mpp18";
157 marvell,function = "ge";
158 };
159
160 ge0_rgmii_pins: ge0-rgmii-pins {
161 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
162 "mpp9", "mpp10", "mpp11", "mpp12",
163 "mpp13", "mpp14", "mpp15", "mpp16";
164 marvell,function = "ge0";
165 };
166
167 ge1_rgmii_pins: ge1-rgmii-pins {
168 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
169 "mpp23", "mpp24", "mpp25", "mpp26",
170 "mpp27", "mpp28", "mpp29", "mpp30";
171 marvell,function = "ge1";
172 };
173 }; 122 };
174 123
175 gpio0: gpio@18100 { 124 gpio0: gpio@18100 {
@@ -205,6 +154,26 @@
205 interrupts = <91>; 154 interrupts = <91>;
206 }; 155 };
207 156
157 /*
158 * Default UART pinctrl setting without RTS/CTS, can
159 * be overwritten on board level if a different
160 * configuration is used.
161 */
162 uart0: serial@12000 {
163 pinctrl-0 = <&uart0_pins>;
164 pinctrl-names = "default";
165 };
166
167 uart1: serial@12100 {
168 pinctrl-0 = <&uart1_pins>;
169 pinctrl-names = "default";
170 };
171
172 system-controller@18200 {
173 compatible = "marvell,armada-370-xp-system-controller";
174 reg = <0x18200 0x100>;
175 };
176
208 gateclk: clock-gating-control@18220 { 177 gateclk: clock-gating-control@18220 {
209 compatible = "marvell,armada-370-gating-clock"; 178 compatible = "marvell,armada-370-gating-clock";
210 reg = <0x18220 0x4>; 179 reg = <0x18220 0x4>;
@@ -249,6 +218,7 @@
249 }; 218 };
250 219
251 audio_controller: audio-controller@30000 { 220 audio_controller: audio-controller@30000 {
221 #sound-dai-cells = <1>;
252 compatible = "marvell,armada370-audio"; 222 compatible = "marvell,armada370-audio";
253 reg = <0x30000 0x4000>; 223 reg = <0x30000 0x4000>;
254 interrupts = <93>; 224 interrupts = <93>;
@@ -305,3 +275,91 @@
305 }; 275 };
306 }; 276 };
307}; 277};
278
279&pinctrl {
280 compatible = "marvell,mv88f6710-pinctrl";
281
282 spi0_pins1: spi0-pins1 {
283 marvell,pins = "mpp33", "mpp34",
284 "mpp35", "mpp36";
285 marvell,function = "spi0";
286 };
287
288 spi0_pins2: spi0_pins2 {
289 marvell,pins = "mpp32", "mpp63",
290 "mpp64", "mpp65";
291 marvell,function = "spi0";
292 };
293
294 spi1_pins: spi1-pins {
295 marvell,pins = "mpp49", "mpp50",
296 "mpp51", "mpp52";
297 marvell,function = "spi1";
298 };
299
300 uart0_pins: uart0-pins {
301 marvell,pins = "mpp0", "mpp1";
302 marvell,function = "uart0";
303 };
304
305 uart1_pins: uart1-pins {
306 marvell,pins = "mpp41", "mpp42";
307 marvell,function = "uart1";
308 };
309
310 sdio_pins1: sdio-pins1 {
311 marvell,pins = "mpp9", "mpp11", "mpp12",
312 "mpp13", "mpp14", "mpp15";
313 marvell,function = "sd0";
314 };
315
316 sdio_pins2: sdio-pins2 {
317 marvell,pins = "mpp47", "mpp48", "mpp49",
318 "mpp50", "mpp51", "mpp52";
319 marvell,function = "sd0";
320 };
321
322 sdio_pins3: sdio-pins3 {
323 marvell,pins = "mpp48", "mpp49", "mpp50",
324 "mpp51", "mpp52", "mpp53";
325 marvell,function = "sd0";
326 };
327
328 i2c0_pins: i2c0-pins {
329 marvell,pins = "mpp2", "mpp3";
330 marvell,function = "i2c0";
331 };
332
333 i2s_pins1: i2s-pins1 {
334 marvell,pins = "mpp5", "mpp6", "mpp7",
335 "mpp8", "mpp9", "mpp10",
336 "mpp12", "mpp13";
337 marvell,function = "audio";
338 };
339
340 i2s_pins2: i2s-pins2 {
341 marvell,pins = "mpp49", "mpp47", "mpp50",
342 "mpp59", "mpp57", "mpp61",
343 "mpp62", "mpp60", "mpp58";
344 marvell,function = "audio";
345 };
346
347 mdio_pins: mdio-pins {
348 marvell,pins = "mpp17", "mpp18";
349 marvell,function = "ge";
350 };
351
352 ge0_rgmii_pins: ge0-rgmii-pins {
353 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
354 "mpp9", "mpp10", "mpp11", "mpp12",
355 "mpp13", "mpp14", "mpp15", "mpp16";
356 marvell,function = "ge0";
357 };
358
359 ge1_rgmii_pins: ge1-rgmii-pins {
360 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
361 "mpp23", "mpp24", "mpp25", "mpp26",
362 "mpp27", "mpp28", "mpp29", "mpp30";
363 marvell,function = "ge1";
364 };
365};
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index de6571445cef..9721e55384ce 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -36,6 +36,12 @@
36 #clock-cells = <0>; 36 #clock-cells = <0>;
37 clock-frequency = <2000000000>; 37 clock-frequency = <2000000000>;
38 }; 38 };
39 /* 25 MHz reference crystal */
40 refclk: oscillator {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
44 };
39 }; 45 };
40 46
41 cpus { 47 cpus {
@@ -366,13 +372,15 @@
366 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 372 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
367 <&mpic 5>, 373 <&mpic 5>,
368 <&mpic 6>; 374 <&mpic 6>;
369 clocks = <&coreclk 0>; 375 clocks = <&coreclk 0>, <&refclk>;
376 clock-names = "nbclk", "fixed";
370 }; 377 };
371 378
372 watchdog@20300 { 379 watchdog@20300 {
373 compatible = "marvell,armada-375-wdt"; 380 compatible = "marvell,armada-375-wdt";
374 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; 381 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
375 clocks = <&coreclk 0>; 382 clocks = <&coreclk 0>, <&refclk>;
383 clock-names = "nbclk", "fixed";
376 }; 384 };
377 385
378 cpurst@20800 { 386 cpurst@20800 {
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 1af886f1e486..2aaa9d2ac284 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -116,11 +116,11 @@
116 }; 116 };
117 117
118 sdhci@d8000 { 118 sdhci@d8000 {
119 clock-frequency = <200000000>;
120 broken-cd; 119 broken-cd;
121 wp-inverted; 120 wp-inverted;
122 bus-width = <8>; 121 bus-width = <8>;
123 status = "okay"; 122 status = "okay";
123 no-1-8-v;
124 }; 124 };
125 125
126 usb3@f0000 { 126 usb3@f0000 {
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 242d0ecc99f3..74391dace9e7 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -25,9 +25,9 @@
25 aliases { 25 aliases {
26 gpio0 = &gpio0; 26 gpio0 = &gpio0;
27 gpio1 = &gpio1; 27 gpio1 = &gpio1;
28 eth0 = &eth0; 28 ethernet0 = &eth0;
29 eth1 = &eth1; 29 ethernet1 = &eth1;
30 eth2 = &eth2; 30 ethernet2 = &eth2;
31 }; 31 };
32 32
33 soc { 33 soc {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index a55a97a70505..ca0200e20751 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,40 +60,6 @@
60 }; 60 };
61 61
62 internal-regs { 62 internal-regs {
63 pinctrl {
64 pinctrl-0 = <&pmx_phy_int>;
65 pinctrl-names = "default";
66
67 pmx_ge0: pmx-ge0 {
68 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
69 "mpp4", "mpp5", "mpp6", "mpp7",
70 "mpp8", "mpp9", "mpp10", "mpp11";
71 marvell,function = "ge0";
72 };
73
74 pmx_ge1: pmx-ge1 {
75 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
76 "mpp16", "mpp17", "mpp18", "mpp19",
77 "mpp20", "mpp21", "mpp22", "mpp23";
78 marvell,function = "ge1";
79 };
80
81 pmx_keys: pmx-keys {
82 marvell,pins = "mpp33";
83 marvell,function = "gpio";
84 };
85
86 pmx_spi: pmx-spi {
87 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
88 marvell,function = "spi";
89 };
90
91 pmx_phy_int: pmx-phy-int {
92 marvell,pins = "mpp32";
93 marvell,function = "gpio";
94 };
95 };
96
97 serial@12000 { 63 serial@12000 {
98 status = "okay"; 64 status = "okay";
99 }; 65 };
@@ -118,14 +84,14 @@
118 }; 84 };
119 85
120 ethernet@70000 { 86 ethernet@70000 {
121 pinctrl-0 = <&pmx_ge0>; 87 pinctrl-0 = <&ge0_rgmii_pins>;
122 pinctrl-names = "default"; 88 pinctrl-names = "default";
123 status = "okay"; 89 status = "okay";
124 phy = <&phy0>; 90 phy = <&phy0>;
125 phy-mode = "rgmii-id"; 91 phy-mode = "rgmii-id";
126 }; 92 };
127 ethernet@74000 { 93 ethernet@74000 {
128 pinctrl-0 = <&pmx_ge1>; 94 pinctrl-0 = <&ge1_rgmii_pins>;
129 pinctrl-names = "default"; 95 pinctrl-names = "default";
130 status = "okay"; 96 status = "okay";
131 phy = <&phy1>; 97 phy = <&phy1>;
@@ -134,8 +100,6 @@
134 100
135 spi0: spi@10600 { 101 spi0: spi@10600 {
136 status = "okay"; 102 status = "okay";
137 pinctrl-0 = <&pmx_spi>;
138 pinctrl-names = "default";
139 103
140 spi-flash@0 { 104 spi-flash@0 {
141 #address-cells = <1>; 105 #address-cells = <1>;
@@ -152,7 +116,7 @@
152 compatible = "gpio-keys"; 116 compatible = "gpio-keys";
153 #address-cells = <1>; 117 #address-cells = <1>;
154 #size-cells = <0>; 118 #size-cells = <0>;
155 pinctrl-0 = <&pmx_keys>; 119 pinctrl-0 = <&keys_pin>;
156 pinctrl-names = "default"; 120 pinctrl-names = "default";
157 121
158 button@1 { 122 button@1 {
@@ -162,3 +126,18 @@
162 }; 126 };
163 }; 127 };
164}; 128};
129
130&pinctrl {
131 pinctrl-0 = <&phy_int_pin>;
132 pinctrl-names = "default";
133
134 keys_pin: keys-pin {
135 marvell,pins = "mpp33";
136 marvell,function = "gpio";
137 };
138
139 phy_int_pin: phy-int-pin {
140 marvell,pins = "mpp32";
141 marvell,function = "gpio";
142 };
143};
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
index 469cf7137595..a2ef93c1eb10 100644
--- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -22,7 +22,7 @@
22 22
23 chosen { 23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk"; 24 bootargs = "console=ttyS0,115200 earlyprintk";
25 stdout-path = "/soc/internal-regs/serial@12000"; 25 stdout-path = &uart0;
26 }; 26 };
27 27
28 memory { 28 memory {
@@ -51,37 +51,6 @@
51 }; 51 };
52 52
53 internal-regs { 53 internal-regs {
54 pinctrl {
55 poweroff_pin: poweroff-pin {
56 marvell,pins = "mpp24";
57 marvell,function = "gpio";
58 };
59
60 power_button_pin: power-button-pin {
61 marvell,pins = "mpp44";
62 marvell,function = "gpio";
63 };
64
65 reset_button_pin: reset-button-pin {
66 marvell,pins = "mpp45";
67 marvell,function = "gpio";
68 };
69 select_button_pin: select-button-pin {
70 marvell,pins = "mpp41";
71 marvell,function = "gpio";
72 };
73
74 scroll_button_pin: scroll-button-pin {
75 marvell,pins = "mpp42";
76 marvell,function = "gpio";
77 };
78
79 hdd_led_pin: hdd-led-pin {
80 marvell,pins = "mpp26";
81 marvell,function = "gpio";
82 };
83 };
84
85 serial@12000 { 54 serial@12000 {
86 status = "okay"; 55 status = "okay";
87 }; 56 };
@@ -97,12 +66,16 @@
97 }; 66 };
98 67
99 ethernet@70000 { 68 ethernet@70000 {
69 pinctrl-0 = <&ge0_rgmii_pins>;
70 pinctrl-names = "default";
100 status = "okay"; 71 status = "okay";
101 phy = <&phy0>; 72 phy = <&phy0>;
102 phy-mode = "rgmii-id"; 73 phy-mode = "rgmii-id";
103 }; 74 };
104 75
105 ethernet@74000 { 76 ethernet@74000 {
77 pinctrl-0 = <&ge1_rgmii_pins>;
78 pinctrl-names = "default";
106 status = "okay"; 79 status = "okay";
107 phy = <&phy1>; 80 phy = <&phy1>;
108 phy-mode = "rgmii-id"; 81 phy-mode = "rgmii-id";
@@ -125,6 +98,11 @@
125 reg = <0x2e>; 98 reg = <0x2e>;
126 }; 99 };
127 100
101 eeprom@50 {
102 compatible = "atmel,24c64";
103 reg = <0x50>;
104 };
105
128 pcf8563@51 { 106 pcf8563@51 {
129 compatible = "nxp,pcf8563"; 107 compatible = "nxp,pcf8563";
130 reg = <0x51>; 108 reg = <0x51>;
@@ -226,7 +204,7 @@
226 gpio-controller; 204 gpio-controller;
227 #gpio-cells = <2>; 205 #gpio-cells = <2>;
228 reg = <0>; 206 reg = <0>;
229 registers-number = <2>; 207 registers-number = <1>;
230 spi-max-frequency = <100000>; 208 spi-max-frequency = <100000>;
231 }; 209 };
232 }; 210 };
@@ -282,3 +260,34 @@
282 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; 260 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
283 }; 261 };
284}; 262};
263
264&pinctrl {
265 poweroff_pin: poweroff-pin {
266 marvell,pins = "mpp24";
267 marvell,function = "gpio";
268 };
269
270 power_button_pin: power-button-pin {
271 marvell,pins = "mpp44";
272 marvell,function = "gpio";
273 };
274
275 reset_button_pin: reset-button-pin {
276 marvell,pins = "mpp45";
277 marvell,function = "gpio";
278 };
279 select_button_pin: select-button-pin {
280 marvell,pins = "mpp41";
281 marvell,function = "gpio";
282 };
283
284 scroll_button_pin: scroll-button-pin {
285 marvell,pins = "mpp42";
286 marvell,function = "gpio";
287 };
288
289 hdd_led_pin: hdd-led-pin {
290 marvell,pins = "mpp26";
291 marvell,function = "gpio";
292 };
293};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 2592e1c13560..281ccd24295c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -167,17 +167,6 @@
167 }; 167 };
168 168
169 internal-regs { 169 internal-regs {
170 pinctrl {
171 compatible = "marvell,mv78230-pinctrl";
172 reg = <0x18000 0x38>;
173
174 sdio_pins: sdio-pins {
175 marvell,pins = "mpp30", "mpp31", "mpp32",
176 "mpp33", "mpp34", "mpp35";
177 marvell,function = "sd0";
178 };
179 };
180
181 gpio0: gpio@18100 { 170 gpio0: gpio@18100 {
182 compatible = "marvell,orion-gpio"; 171 compatible = "marvell,orion-gpio";
183 reg = <0x18100 0x40>; 172 reg = <0x18100 0x40>;
@@ -202,3 +191,7 @@
202 }; 191 };
203 }; 192 };
204}; 193};
194
195&pinctrl {
196 compatible = "marvell,mv78230-pinctrl";
197};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 480e237a870f..d7a8d0b0f385 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -251,17 +251,6 @@
251 }; 251 };
252 252
253 internal-regs { 253 internal-regs {
254 pinctrl {
255 compatible = "marvell,mv78260-pinctrl";
256 reg = <0x18000 0x38>;
257
258 sdio_pins: sdio-pins {
259 marvell,pins = "mpp30", "mpp31", "mpp32",
260 "mpp33", "mpp34", "mpp35";
261 marvell,function = "sd0";
262 };
263 };
264
265 gpio0: gpio@18100 { 254 gpio0: gpio@18100 {
266 compatible = "marvell,orion-gpio"; 255 compatible = "marvell,orion-gpio";
267 reg = <0x18100 0x40>; 256 reg = <0x18100 0x40>;
@@ -305,3 +294,7 @@
305 }; 294 };
306 }; 295 };
307}; 296};
297
298&pinctrl {
299 compatible = "marvell,mv78260-pinctrl";
300};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 2c7b1fef4703..9c40c130d11a 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -289,17 +289,6 @@
289 }; 289 };
290 290
291 internal-regs { 291 internal-regs {
292 pinctrl {
293 compatible = "marvell,mv78460-pinctrl";
294 reg = <0x18000 0x38>;
295
296 sdio_pins: sdio-pins {
297 marvell,pins = "mpp30", "mpp31", "mpp32",
298 "mpp33", "mpp34", "mpp35";
299 marvell,function = "sd0";
300 };
301 };
302
303 gpio0: gpio@18100 { 292 gpio0: gpio@18100 {
304 compatible = "marvell,orion-gpio"; 293 compatible = "marvell,orion-gpio";
305 reg = <0x18100 0x40>; 294 reg = <0x18100 0x40>;
@@ -343,3 +332,7 @@
343 }; 332 };
344 }; 333 };
345}; 334};
335
336&pinctrl {
337 compatible = "marvell,mv78460-pinctrl";
338};
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index 7d8f32873e82..d81430aa4ab3 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -55,86 +55,10 @@
55 }; 55 };
56 56
57 internal-regs { 57 internal-regs {
58 pinctrl { 58 /* Two rear eSATA ports */
59 poweroff: poweroff { 59 sata@a0000 {
60 marvell,pins = "mpp42"; 60 nr-ports = <2>;
61 marvell,function = "gpio"; 61 status = "okay";
62 };
63
64 power_button_pin: power-button-pin {
65 marvell,pins = "mpp27";
66 marvell,function = "gpio";
67 };
68
69 reset_button_pin: reset-button-pin {
70 marvell,pins = "mpp41";
71 marvell,function = "gpio";
72 };
73
74 sata1_led_pin: sata1-led-pin {
75 marvell,pins = "mpp31";
76 marvell,function = "gpio";
77 };
78
79 sata2_led_pin: sata2-led-pin {
80 marvell,pins = "mpp40";
81 marvell,function = "gpio";
82 };
83
84 sata3_led_pin: sata3-led-pin {
85 marvell,pins = "mpp44";
86 marvell,function = "gpio";
87 };
88
89 sata4_led_pin: sata4-led-pin {
90 marvell,pins = "mpp47";
91 marvell,function = "gpio";
92 };
93
94 sata1_power_pin: sata1-power-pin {
95 marvell,pins = "mpp24";
96 marvell,function = "gpio";
97 };
98
99 sata2_power_pin: sata2-power-pin {
100 marvell,pins = "mpp25";
101 marvell,function = "gpio";
102 };
103
104 sata3_power_pin: sata3-power-pin {
105 marvell,pins = "mpp26";
106 marvell,function = "gpio";
107 };
108
109 sata4_power_pin: sata4-power-pin {
110 marvell,pins = "mpp28";
111 marvell,function = "gpio";
112 };
113
114 sata1_pres_pin: sata1-pres-pin {
115 marvell,pins = "mpp32";
116 marvell,function = "gpio";
117 };
118
119 sata2_pres_pin: sata2-pres-pin {
120 marvell,pins = "mpp33";
121 marvell,function = "gpio";
122 };
123
124 sata3_pres_pin: sata3-pres-pin {
125 marvell,pins = "mpp34";
126 marvell,function = "gpio";
127 };
128
129 sata4_pres_pin: sata4-pres-pin {
130 marvell,pins = "mpp35";
131 marvell,function = "gpio";
132 };
133
134 err_led_pin: err-led-pin {
135 marvell,pins = "mpp45";
136 marvell,function = "gpio";
137 };
138 }; 62 };
139 63
140 serial@12000 { 64 serial@12000 {
@@ -328,3 +252,85 @@
328 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 252 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
329 }; 253 };
330}; 254};
255
256&pinctrl {
257 poweroff: poweroff {
258 marvell,pins = "mpp42";
259 marvell,function = "gpio";
260 };
261
262 power_button_pin: power-button-pin {
263 marvell,pins = "mpp27";
264 marvell,function = "gpio";
265 };
266
267 reset_button_pin: reset-button-pin {
268 marvell,pins = "mpp41";
269 marvell,function = "gpio";
270 };
271
272 sata1_led_pin: sata1-led-pin {
273 marvell,pins = "mpp31";
274 marvell,function = "gpio";
275 };
276
277 sata2_led_pin: sata2-led-pin {
278 marvell,pins = "mpp40";
279 marvell,function = "gpio";
280 };
281
282 sata3_led_pin: sata3-led-pin {
283 marvell,pins = "mpp44";
284 marvell,function = "gpio";
285 };
286
287 sata4_led_pin: sata4-led-pin {
288 marvell,pins = "mpp47";
289 marvell,function = "gpio";
290 };
291
292 sata1_power_pin: sata1-power-pin {
293 marvell,pins = "mpp24";
294 marvell,function = "gpio";
295 };
296
297 sata2_power_pin: sata2-power-pin {
298 marvell,pins = "mpp25";
299 marvell,function = "gpio";
300 };
301
302 sata3_power_pin: sata3-power-pin {
303 marvell,pins = "mpp26";
304 marvell,function = "gpio";
305 };
306
307 sata4_power_pin: sata4-power-pin {
308 marvell,pins = "mpp28";
309 marvell,function = "gpio";
310 };
311
312 sata1_pres_pin: sata1-pres-pin {
313 marvell,pins = "mpp32";
314 marvell,function = "gpio";
315 };
316
317 sata2_pres_pin: sata2-pres-pin {
318 marvell,pins = "mpp33";
319 marvell,function = "gpio";
320 };
321
322 sata3_pres_pin: sata3-pres-pin {
323 marvell,pins = "mpp34";
324 marvell,function = "gpio";
325 };
326
327 sata4_pres_pin: sata4-pres-pin {
328 marvell,pins = "mpp35";
329 marvell,function = "gpio";
330 };
331
332 err_led_pin: err-led-pin {
333 marvell,pins = "mpp45";
334 marvell,function = "gpio";
335 };
336};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 4e5a59ee1501..6f6b0916df48 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -77,12 +77,7 @@
77 serial@12100 { 77 serial@12100 {
78 status = "okay"; 78 status = "okay";
79 }; 79 };
80 pinctrl { 80
81 led_pins: led-pins-0 {
82 marvell,pins = "mpp49", "mpp51", "mpp53";
83 marvell,function = "gpio";
84 };
85 };
86 leds { 81 leds {
87 compatible = "gpio-leds"; 82 compatible = "gpio-leds";
88 pinctrl-names = "default"; 83 pinctrl-names = "default";
@@ -187,3 +182,10 @@
187 }; 182 };
188 }; 183 };
189}; 184};
185
186&pinctrl {
187 led_pins: led-pins-0 {
188 marvell,pins = "mpp49", "mpp51", "mpp53";
189 marvell,function = "gpio";
190 };
191};
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
new file mode 100644
index 000000000000..749fdba5a642
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts
@@ -0,0 +1,330 @@
1/*
2 * Device Tree file for Synology DS414
3 *
4 * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Note: this Device Tree assumes that the bootloader has remapped the
12 * internal registers to 0xf1000000 (instead of the old 0xd0000000).
13 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
14 * bootloaders provided by Marvell. It is used in recent versions of
15 * DSM software provided by Synology. Nonetheless, some earlier boards
16 * were delivered with an older version of u-boot that left internal
17 * registers mapped at 0xd0000000. If you have such a device you will
18 * not be able to directly boot a kernel based on this Device Tree. In
19 * that case, the preferred solution is to update your bootloader (e.g.
20 * by upgrading to latest version of DSM, or building a new one and
21 * installing it from u-boot prompt) or adjust the Devive Tree
22 * (s/0xf1000000/0xd0000000/ in 'ranges' below).
23 */
24
25/dts-v1/;
26
27#include <dt-bindings/input/input.h>
28#include <dt-bindings/gpio/gpio.h>
29#include "armada-xp-mv78230.dtsi"
30
31/ {
32 model = "Synology DS414";
33 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
34 "marvell,armadaxp", "marvell,armada-370-xp";
35
36 chosen {
37 bootargs = "console=ttyS0,115200 earlyprintk";
38 stdout-path = &uart0;
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0 0x00000000 0 0x40000000>; /* 1GB */
44 };
45
46 soc {
47 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
48 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
49
50 pcie-controller {
51 status = "okay";
52
53 /*
54 * Connected to Marvell 88SX7042 SATA-II controller
55 * handling the four disks.
56 */
57 pcie@1,0 {
58 /* Port 0, Lane 0 */
59 status = "okay";
60 };
61
62 /*
63 * Connected to EtronTech EJ168A XHCI controller
64 * providing the two rear USB 3.0 ports.
65 */
66 pcie@5,0 {
67 /* Port 1, Lane 0 */
68 status = "okay";
69 };
70 };
71
72 internal-regs {
73
74 /* RTC is provided by Seiko S-35390A below */
75 rtc@10300 {
76 status = "disabled";
77 };
78
79 spi0: spi@10600 {
80 status = "okay";
81
82 spi-flash@0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "micron,n25q064";
86 reg = <0>; /* Chip select 0 */
87 spi-max-frequency = <20000000>;
88
89 /*
90 * Warning!
91 *
92 * Synology u-boot uses its compiled-in environment
93 * and it seems Synology did not care to change u-boot
94 * default configuration in order to allow saving a
95 * modified environment at a sensible location. So,
96 * if you do a 'saveenv' under u-boot, your modified
97 * environment will be saved at 1MB after the start
98 * of the flash, i.e. in the middle of the uImage.
99 * For that reason, it is strongly advised not to
100 * change the default environment, unless you know
101 * what you are doing.
102 */
103 partition@00000000 { /* u-boot */
104 label = "RedBoot";
105 reg = <0x00000000 0x000d0000>; /* 832KB */
106 };
107
108 partition@000c0000 { /* uImage */
109 label = "zImage";
110 reg = <0x000d0000 0x002d0000>; /* 2880KB */
111 };
112
113 partition@003a0000 { /* uInitramfs */
114 label = "rd.gz";
115 reg = <0x003a0000 0x00430000>; /* 4250KB */
116 };
117
118 partition@007d0000 { /* MAC address and serial number */
119 label = "vendor";
120 reg = <0x007d0000 0x00010000>; /* 64KB */
121 };
122
123 partition@007e0000 {
124 label = "RedBoot config";
125 reg = <0x007e0000 0x00010000>; /* 64KB */
126 };
127
128 partition@007f0000 {
129 label = "FIS directory";
130 reg = <0x007f0000 0x00010000>; /* 64KB */
131 };
132 };
133 };
134
135 i2c@11000 {
136 clock-frequency = <400000>;
137 status = "okay";
138
139 s35390a: s35390a@30 {
140 compatible = "sii,s35390a";
141 reg = <0x30>;
142 };
143 };
144
145 /* Connected to a header on device's PCB. This
146 * provides the main console for the device.
147 *
148 * Warning: the device may not boot with a 3.3V
149 * USB-serial converter connected when the power
150 * button is pressed. The converter needs to be
151 * connected a few seconds after pressing the
152 * power button. This is possibly due to UART0_TXD
153 * pin being sampled at reset (bit 0 of SAR).
154 */
155 serial@12000 {
156 status = "okay";
157 };
158
159 /* Connected to a Microchip PIC16F883 for power control */
160 serial@12100 {
161 status = "okay";
162 };
163
164 poweroff@12100 {
165 compatible = "synology,power-off";
166 reg = <0x12100 0x100>;
167 clocks = <&coreclk 0>;
168 };
169
170 /* Front USB 2.0 port */
171 usb@50000 {
172 status = "okay";
173 };
174
175 mdio {
176 phy0: ethernet-phy@0 { /* Marvell 88E1512 */
177 reg = <0>;
178 };
179
180 phy1: ethernet-phy@1 { /* Marvell 88E1512 */
181 reg = <1>;
182 };
183 };
184
185 ethernet@70000 {
186 status = "okay";
187 pinctrl-0 = <&ge0_rgmii_pins>;
188 pinctrl-names = "default";
189 phy = <&phy1>;
190 phy-mode = "rgmii-id";
191 };
192
193 ethernet@74000 {
194 pinctrl-0 = <&ge1_rgmii_pins>;
195 pinctrl-names = "default";
196 status = "okay";
197 phy = <&phy0>;
198 phy-mode = "rgmii-id";
199 };
200 };
201 };
202
203 regulators {
204 compatible = "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
208 &sata3_pwr_pin &sata4_pwr_pin>;
209 pinctrl-names = "default";
210
211 sata1_regulator: sata1-regulator {
212 compatible = "regulator-fixed";
213 reg = <1>;
214 regulator-name = "SATA1 Power";
215 regulator-min-microvolt = <5000000>;
216 regulator-max-microvolt = <5000000>;
217 startup-delay-us = <2000000>;
218 enable-active-high;
219 regulator-always-on;
220 regulator-boot-on;
221 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
222 };
223
224 sata2_regulator: sata2-regulator {
225 compatible = "regulator-fixed";
226 reg = <2>;
227 regulator-name = "SATA2 Power";
228 regulator-min-microvolt = <5000000>;
229 regulator-max-microvolt = <5000000>;
230 startup-delay-us = <4000000>;
231 enable-active-high;
232 regulator-always-on;
233 regulator-boot-on;
234 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
235 };
236
237 sata3_regulator: sata3-regulator {
238 compatible = "regulator-fixed";
239 reg = <3>;
240 regulator-name = "SATA3 Power";
241 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5000000>;
243 startup-delay-us = <6000000>;
244 enable-active-high;
245 regulator-always-on;
246 regulator-boot-on;
247 gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
248 };
249
250 sata4_regulator: sata4-regulator {
251 compatible = "regulator-fixed";
252 reg = <4>;
253 regulator-name = "SATA4 Power";
254 regulator-min-microvolt = <5000000>;
255 regulator-max-microvolt = <5000000>;
256 startup-delay-us = <8000000>;
257 enable-active-high;
258 regulator-always-on;
259 regulator-boot-on;
260 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
261 };
262 };
263};
264
265&pinctrl {
266 sata1_pwr_pin: sata1-pwr-pin {
267 marvell,pins = "mpp42";
268 marvell,function = "gpio";
269 };
270
271 sata2_pwr_pin: sata2-pwr-pin {
272 marvell,pins = "mpp44";
273 marvell,function = "gpio";
274 };
275
276 sata3_pwr_pin: sata3-pwr-pin {
277 marvell,pins = "mpp45";
278 marvell,function = "gpio";
279 };
280
281 sata4_pwr_pin: sata4-pwr-pin {
282 marvell,pins = "mpp46";
283 marvell,function = "gpio";
284 };
285
286 sata1_pres_pin: sata1-pres-pin {
287 marvell,pins = "mpp34";
288 marvell,function = "gpio";
289 };
290
291 sata2_pres_pin: sata2-pres-pin {
292 marvell,pins = "mpp35";
293 marvell,function = "gpio";
294 };
295
296 sata3_pres_pin: sata3-pres-pin {
297 marvell,pins = "mpp40";
298 marvell,function = "gpio";
299 };
300
301 sata4_pres_pin: sata4-pres-pin {
302 marvell,pins = "mpp41";
303 marvell,function = "gpio";
304 };
305
306 syno_id_bit0_pin: syno-id-bit0-pin {
307 marvell,pins = "mpp26";
308 marvell,function = "gpio";
309 };
310
311 syno_id_bit1_pin: syno-id-bit1-pin {
312 marvell,pins = "mpp28";
313 marvell,function = "gpio";
314 };
315
316 syno_id_bit2_pin: syno-id-bit2-pin {
317 marvell,pins = "mpp29";
318 marvell,function = "gpio";
319 };
320
321 fan1_alarm_pin: fan1-alarm-pin {
322 marvell,pins = "mpp33";
323 marvell,function = "gpio";
324 };
325
326 fan2_alarm_pin: fan2-alarm-pin {
327 marvell,pins = "mpp32";
328 marvell,function = "gpio";
329 };
330};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 2be244a96edf..62c3ba958b39 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -44,9 +44,15 @@
44 compatible = "marvell,aurora-system-cache"; 44 compatible = "marvell,aurora-system-cache";
45 reg = <0x08000 0x1000>; 45 reg = <0x08000 0x1000>;
46 cache-id-part = <0x100>; 46 cache-id-part = <0x100>;
47 cache-unified;
47 wt-override; 48 wt-override;
48 }; 49 };
49 50
51 spi0: spi@10600 {
52 pinctrl-0 = <&spi0_pins>;
53 pinctrl-names = "default";
54 };
55
50 i2c0: i2c@11000 { 56 i2c0: i2c@11000 {
51 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; 57 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
52 reg = <0x11000 0x100>; 58 reg = <0x11000 0x100>;
@@ -57,8 +63,10 @@
57 reg = <0x11100 0x100>; 63 reg = <0x11100 0x100>;
58 }; 64 };
59 65
60 serial@12200 { 66 uart2: serial@12200 {
61 compatible = "snps,dw-apb-uart"; 67 compatible = "snps,dw-apb-uart";
68 pinctrl-0 = <&uart2_pins>;
69 pinctrl-names = "default";
62 reg = <0x12200 0x100>; 70 reg = <0x12200 0x100>;
63 reg-shift = <2>; 71 reg-shift = <2>;
64 interrupts = <43>; 72 interrupts = <43>;
@@ -66,8 +74,11 @@
66 clocks = <&coreclk 0>; 74 clocks = <&coreclk 0>;
67 status = "disabled"; 75 status = "disabled";
68 }; 76 };
69 serial@12300 { 77
78 uart3: serial@12300 {
70 compatible = "snps,dw-apb-uart"; 79 compatible = "snps,dw-apb-uart";
80 pinctrl-0 = <&uart3_pins>;
81 pinctrl-names = "default";
71 reg = <0x12300 0x100>; 82 reg = <0x12300 0x100>;
72 reg-shift = <2>; 83 reg-shift = <2>;
73 interrupts = <44>; 84 interrupts = <44>;
@@ -204,3 +215,54 @@
204 }; 215 };
205 }; 216 };
206}; 217};
218
219&pinctrl {
220 ge0_gmii_pins: ge0-gmii-pins {
221 marvell,pins =
222 "mpp0", "mpp1", "mpp2", "mpp3",
223 "mpp4", "mpp5", "mpp6", "mpp7",
224 "mpp8", "mpp9", "mpp10", "mpp11",
225 "mpp12", "mpp13", "mpp14", "mpp15",
226 "mpp16", "mpp17", "mpp18", "mpp19",
227 "mpp20", "mpp21", "mpp22", "mpp23";
228 marvell,function = "ge0";
229 };
230
231 ge0_rgmii_pins: ge0-rgmii-pins {
232 marvell,pins =
233 "mpp0", "mpp1", "mpp2", "mpp3",
234 "mpp4", "mpp5", "mpp6", "mpp7",
235 "mpp8", "mpp9", "mpp10", "mpp11";
236 marvell,function = "ge0";
237 };
238
239 ge1_rgmii_pins: ge1-rgmii-pins {
240 marvell,pins =
241 "mpp12", "mpp13", "mpp14", "mpp15",
242 "mpp16", "mpp17", "mpp18", "mpp19",
243 "mpp20", "mpp21", "mpp22", "mpp23";
244 marvell,function = "ge1";
245 };
246
247 sdio_pins: sdio-pins {
248 marvell,pins = "mpp30", "mpp31", "mpp32",
249 "mpp33", "mpp34", "mpp35";
250 marvell,function = "sd0";
251 };
252
253 spi0_pins: spi0-pins {
254 marvell,pins = "mpp36", "mpp37",
255 "mpp38", "mpp39";
256 marvell,function = "spi";
257 };
258
259 uart2_pins: uart2-pins {
260 marvell,pins = "mpp42", "mpp43";
261 marvell,function = "uart2";
262 };
263
264 uart3_pins: uart3-pins {
265 marvell,pins = "mpp44", "mpp45";
266 marvell,function = "uart3";
267 };
268};
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 51416c7d0625..653e4395b7cb 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -677,6 +677,14 @@
677 }; 677 };
678 }; 678 };
679 679
680 can {
681 pinctrl_can_rx_tx: can_rx_tx {
682 atmel,pins =
683 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */
684 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
685 };
686 };
687
680 pioA: gpio@fffff200 { 688 pioA: gpio@fffff200 {
681 compatible = "atmel,at91rm9200-gpio"; 689 compatible = "atmel,at91rm9200-gpio";
682 reg = <0xfffff200 0x200>; 690 reg = <0xfffff200 0x200>;
@@ -905,6 +913,17 @@
905 clock-names = "pwm_clk"; 913 clock-names = "pwm_clk";
906 status = "disabled"; 914 status = "disabled";
907 }; 915 };
916
917 can: can@fffac000 {
918 compatible = "atmel,at91sam9263-can";
919 reg = <0xfffac000 0x300>;
920 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
921 pinctrl-names = "default";
922 pinctrl-0 = <&pinctrl_can_rx_tx>;
923 clocks = <&can_clk>;
924 clock-names = "can_clk";
925 status = "disabled";
926 };
908 }; 927 };
909 928
910 fb0: fb@0x00700000 { 929 fb0: fb@0x00700000 {
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index c2554219f7a4..3c5fa3388997 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -10,6 +10,7 @@
10#include "at91sam9x5_usart3.dtsi" 10#include "at91sam9x5_usart3.dtsi"
11#include "at91sam9x5_macb0.dtsi" 11#include "at91sam9x5_macb0.dtsi"
12#include "at91sam9x5_macb1.dtsi" 12#include "at91sam9x5_macb1.dtsi"
13#include "at91sam9x5_can.dtsi"
13 14
14/ { 15/ {
15 model = "Atmel AT91SAM9X25 SoC"; 16 model = "Atmel AT91SAM9X25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 8eac66ce0ab7..499cdc81f4c0 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -8,6 +8,7 @@
8 8
9#include "at91sam9x5.dtsi" 9#include "at91sam9x5.dtsi"
10#include "at91sam9x5_macb0.dtsi" 10#include "at91sam9x5_macb0.dtsi"
11#include "at91sam9x5_can.dtsi"
11 12
12/ { 13/ {
13 model = "Atmel AT91SAM9X35 SoC"; 14 model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 726274f7959b..bbb3ba65165f 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -860,6 +860,9 @@
860 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 860 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
861 pinctrl-names = "default"; 861 pinctrl-names = "default";
862 pinctrl-0 = <&pinctrl_dbgu>; 862 pinctrl-0 = <&pinctrl_dbgu>;
863 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
864 <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
865 dma-names = "tx", "rx";
863 clocks = <&mck>; 866 clocks = <&mck>;
864 clock-names = "usart"; 867 clock-names = "usart";
865 status = "disabled"; 868 status = "disabled";
@@ -871,6 +874,9 @@
871 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; 874 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
872 pinctrl-names = "default"; 875 pinctrl-names = "default";
873 pinctrl-0 = <&pinctrl_usart0>; 876 pinctrl-0 = <&pinctrl_usart0>;
877 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
878 <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
879 dma-names = "tx", "rx";
874 clocks = <&usart0_clk>; 880 clocks = <&usart0_clk>;
875 clock-names = "usart"; 881 clock-names = "usart";
876 status = "disabled"; 882 status = "disabled";
@@ -882,6 +888,9 @@
882 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 888 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
883 pinctrl-names = "default"; 889 pinctrl-names = "default";
884 pinctrl-0 = <&pinctrl_usart1>; 890 pinctrl-0 = <&pinctrl_usart1>;
891 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
892 <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
893 dma-names = "tx", "rx";
885 clocks = <&usart1_clk>; 894 clocks = <&usart1_clk>;
886 clock-names = "usart"; 895 clock-names = "usart";
887 status = "disabled"; 896 status = "disabled";
@@ -893,6 +902,9 @@
893 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 902 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
894 pinctrl-names = "default"; 903 pinctrl-names = "default";
895 pinctrl-0 = <&pinctrl_usart2>; 904 pinctrl-0 = <&pinctrl_usart2>;
905 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
906 <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
907 dma-names = "tx", "rx";
896 clocks = <&usart2_clk>; 908 clocks = <&usart2_clk>;
897 clock-names = "usart"; 909 clock-names = "usart";
898 status = "disabled"; 910 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
index f44ab7702a12..8eb2f9c1b978 100644
--- a/arch/arm/boot/dts/at91sam9x5_can.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 2 * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
3 * Ethernet interface. 3 * Ethernet interface.
4 * 4 *
5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 5 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
@@ -20,10 +20,50 @@
20 reg = <29>; 20 reg = <29>;
21 }; 21 };
22 22
23 can1_clk: can1_clk { 23 can1_clk: can1_clk {
24 #clock-cells = <0>; 24 #clock-cells = <0>;
25 reg = <30>; 25 reg = <30>;
26 }; 26 };
27 };
28 };
29
30 can0: can@f8000000 {
31 compatible = "atmel,at91sam9x5-can";
32 reg = <0xf8000000 0x300>;
33 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_can0_rx_tx>;
36 clocks = <&can0_clk>;
37 clock-names = "can_clk";
38 status = "disabled";
39 };
40
41 can1: can@f8004000 {
42 compatible = "atmel,at91sam9x5-can";
43 reg = <0xf8004000 0x300>;
44 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_can1_rx_tx>;
47 clocks = <&can1_clk>;
48 clock-names = "can_clk";
49 status = "disabled";
50 };
51
52 pinctrl@fffff400 {
53 can0 {
54 pinctrl_can0_rx_tx: can0_rx_tx {
55 atmel,pins =
56 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */
57 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */
58 };
59 };
60
61 can1 {
62 pinctrl_can1_rx_tx: can1_rx_tx {
63 atmel,pins =
64 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */
65 AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */
66 };
27 }; 67 };
28 }; 68 };
29 }; 69 };
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 140217a54384..43bb5b51caa6 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -57,6 +57,9 @@
57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 57 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_usart3>; 59 pinctrl-0 = <&pinctrl_usart3>;
60 dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
61 <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
62 dma-names = "tx", "rx";
60 clocks = <&usart3_clk>; 63 clocks = <&usart3_clk>;
61 clock-names = "usart"; 64 clock-names = "usart";
62 status = "disabled"; 65 status = "disabled";
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index bb22842a0826..29598667420b 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -131,6 +131,7 @@
131 reg = <0x90020000 0x10000>; 131 reg = <0x90020000 0x10000>;
132 interrupts = <31>; 132 interrupts = <31>;
133 clocks = <&clks 35>; 133 clocks = <&clks 35>;
134 resets = <&rstc 6>;
134 }; 135 };
135 }; 136 };
136 137
@@ -312,6 +313,7 @@
312 #address-cells = <1>; 313 #address-cells = <1>;
313 #size-cells = <0>; 314 #size-cells = <0>;
314 clocks = <&clks 19>; 315 clocks = <&clks 19>;
316 resets = <&rstc 26>;
315 status = "disabled"; 317 status = "disabled";
316 }; 318 };
317 319
@@ -327,6 +329,7 @@
327 #address-cells = <1>; 329 #address-cells = <1>;
328 #size-cells = <0>; 330 #size-cells = <0>;
329 clocks = <&clks 20>; 331 clocks = <&clks 20>;
332 resets = <&rstc 27>;
330 status = "disabled"; 333 status = "disabled";
331 }; 334 };
332 335
@@ -522,6 +525,18 @@
522 sirf,function = "sdmmc5"; 525 sirf,function = "sdmmc5";
523 }; 526 };
524 }; 527 };
528 i2s_mclk_pins_a: i2s_mclk@0 {
529 i2s_mclk {
530 sirf,pins = "i2smclkgrp";
531 sirf,function = "i2s_mclk";
532 };
533 };
534 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
535 i2s_ext_clk_input {
536 sirf,pins = "i2s_ext_clk_inputgrp";
537 sirf,function = "i2s_ext_clk_input";
538 };
539 };
525 i2s_pins_a: i2s@0 { 540 i2s_pins_a: i2s@0 {
526 i2s { 541 i2s {
527 sirf,pins = "i2sgrp"; 542 sirf,pins = "i2sgrp";
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 000000000000..60d8389fdb6c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,91 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33clocks {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
37
38 osc: oscillator {
39 compatible = "fixed-clock";
40 #clock-cells = <1>;
41 clock-frequency = <25000000>;
42 };
43
44 apb_clk: apb_clk {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <1000000000>;
48 };
49
50 periph_clk: periph_clk {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <500000000>;
54 };
55
56 sdio_clk: lcpll_ch2 {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <200000000>;
60 };
61
62 axi81_clk: axi81_clk {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <100000000>;
66 };
67
68 keypad_clk: keypad_clk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <31806>;
72 };
73
74 adc_clk: adc_clk {
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <1562500>;
78 };
79
80 pwm_clk: pwm_clk {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <1000000>;
84 };
85
86 lcd_clk: mipipll_ch1 {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <100000000>;
90 };
91};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 000000000000..5126f9e77a98
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,140 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <dt-bindings/interrupt-controller/arm-gic.h>
34#include <dt-bindings/interrupt-controller/irq.h>
35
36#include "skeleton.dtsi"
37
38/ {
39 compatible = "brcm,cygnus";
40 model = "Broadcom Cygnus SoC";
41 interrupt-parent = <&gic>;
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x0>;
52 };
53 };
54
55 /include/ "bcm-cygnus-clock.dtsi"
56
57 amba {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "arm,amba-bus", "simple-bus";
61 interrupt-parent = <&gic>;
62 ranges;
63
64 wdt@18009000 {
65 compatible = "arm,sp805" , "arm,primecell";
66 reg = <0x18009000 0x1000>;
67 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
68 clocks = <&axi81_clk>;
69 clock-names = "apb_pclk";
70 };
71 };
72
73 uart0: serial@18020000 {
74 compatible = "snps,dw-apb-uart";
75 reg = <0x18020000 0x100>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&axi81_clk>;
80 clock-frequency = <100000000>;
81 status = "disabled";
82 };
83
84 uart1: serial@18021000 {
85 compatible = "snps,dw-apb-uart";
86 reg = <0x18021000 0x100>;
87 reg-shift = <2>;
88 reg-io-width = <4>;
89 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&axi81_clk>;
91 clock-frequency = <100000000>;
92 status = "disabled";
93 };
94
95 uart2: serial@18022000 {
96 compatible = "snps,dw-apb-uart";
97 reg = <0x18020000 0x100>;
98 reg-shift = <2>;
99 reg-io-width = <4>;
100 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&axi81_clk>;
102 clock-frequency = <100000000>;
103 status = "disabled";
104 };
105
106 uart3: serial@18023000 {
107 compatible = "snps,dw-apb-uart";
108 reg = <0x18023000 0x100>;
109 reg-shift = <2>;
110 reg-io-width = <4>;
111 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&axi81_clk>;
113 clock-frequency = <100000000>;
114 status = "disabled";
115 };
116
117 gic: interrupt-controller@19021000 {
118 compatible = "arm,cortex-a9-gic";
119 #interrupt-cells = <3>;
120 #address-cells = <0>;
121 interrupt-controller;
122 reg = <0x19021000 0x1000>,
123 <0x19020100 0x100>;
124 };
125
126 L2: l2-cache {
127 compatible = "arm,pl310-cache";
128 reg = <0x19022000 0x1000>;
129 cache-unified;
130 cache-level = <2>;
131 };
132
133 timer@19020200 {
134 compatible = "arm,cortex-a9-global-timer";
135 reg = <0x19020200 0x100>;
136 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&periph_clk>;
138 };
139
140};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
new file mode 100644
index 000000000000..e479515099c3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -0,0 +1,30 @@
1/dts-v1/;
2/include/ "bcm2835-rpi.dtsi"
3
4/ {
5 compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
6 model = "Raspberry Pi Model B+";
7
8 leds {
9 act {
10 gpios = <&gpio 47 0>;
11 };
12
13 pwr {
14 label = "PWR";
15 gpios = <&gpio 35 0>;
16 default-state = "keep";
17 linux,default-trigger = "default-on";
18 };
19 };
20};
21
22&gpio {
23 pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
24
25 /* I2S interface */
26 i2s_alt0: i2s_alt0 {
27 brcm,pins = <18 19 20 21>;
28 brcm,function = <4>; /* alt0 */
29 };
30};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 58a0d60b95f1..bafa46fc226a 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,63 +1,23 @@
1/dts-v1/; 1/dts-v1/;
2/include/ "bcm2835.dtsi" 2/include/ "bcm2835-rpi.dtsi"
3 3
4/ { 4/ {
5 compatible = "raspberrypi,model-b", "brcm,bcm2835"; 5 compatible = "raspberrypi,model-b", "brcm,bcm2835";
6 model = "Raspberry Pi Model B"; 6 model = "Raspberry Pi Model B";
7 7
8 memory {
9 reg = <0 0x10000000>;
10 };
11
12 leds { 8 leds {
13 compatible = "gpio-leds";
14
15 act { 9 act {
16 label = "ACT";
17 gpios = <&gpio 16 1>; 10 gpios = <&gpio 16 1>;
18 default-state = "keep";
19 linux,default-trigger = "heartbeat";
20 }; 11 };
21 }; 12 };
22}; 13};
23 14
24&gpio { 15&gpio {
25 pinctrl-names = "default"; 16 pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
26 pinctrl-0 = <&gpioout &alt0 &alt2 &alt3>;
27
28 gpioout: gpioout {
29 brcm,pins = <6>;
30 brcm,function = <1>; /* GPIO out */
31 };
32
33 alt0: alt0 {
34 brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
35 brcm,function = <4>; /* alt0 */
36 };
37
38 alt3: alt3 {
39 brcm,pins = <48 49 50 51 52 53>;
40 brcm,function = <7>; /* alt3 */
41 };
42 17
43 /* I2S interface */ 18 /* I2S interface */
44 alt2: alt2 { 19 i2s_alt2: i2s_alt2 {
45 brcm,pins = <28 29 30 31>; 20 brcm,pins = <28 29 30 31>;
46 brcm,function = <6>; /* alt2 */ 21 brcm,function = <6>; /* alt2 */
47 }; 22 };
48}; 23};
49
50&i2c0 {
51 status = "okay";
52 clock-frequency = <100000>;
53};
54
55&i2c1 {
56 status = "okay";
57 clock-frequency = <100000>;
58};
59
60&sdhci {
61 status = "okay";
62 bus-width = <4>;
63};
diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi
new file mode 100644
index 000000000000..c7064487017d
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi
@@ -0,0 +1,51 @@
1/include/ "bcm2835.dtsi"
2
3/ {
4 memory {
5 reg = <0 0x10000000>;
6 };
7
8 leds {
9 compatible = "gpio-leds";
10
11 act {
12 label = "ACT";
13 default-state = "keep";
14 linux,default-trigger = "heartbeat";
15 };
16 };
17};
18
19&gpio {
20 pinctrl-names = "default";
21
22 gpioout: gpioout {
23 brcm,pins = <6>;
24 brcm,function = <1>; /* GPIO out */
25 };
26
27 alt0: alt0 {
28 brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
29 brcm,function = <4>; /* alt0 */
30 };
31
32 alt3: alt3 {
33 brcm,pins = <48 49 50 51 52 53>;
34 brcm,function = <7>; /* alt3 */
35 };
36};
37
38&i2c0 {
39 status = "okay";
40 clock-frequency = <100000>;
41};
42
43&i2c1 {
44 status = "okay";
45 clock-frequency = <100000>;
46};
47
48&sdhci {
49 status = "okay";
50 bus-width = <4>;
51};
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
new file mode 100644
index 000000000000..5fc0fae03092
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -0,0 +1,64 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Buffalo WZR-1750DHP
4 *
5 * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm4708.dtsi"
13
14/ {
15 compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
16 model = "Buffalo WZR-1750DHP (BCM4708)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30 poll-interval = <200>;
31
32 restart {
33 label = "Reset";
34 linux,code = <KEY_RESTART>;
35 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
36 };
37
38 aoss {
39 label = "AOSS";
40 linux,code = <KEY_WPS_BUTTON>;
41 gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
42 };
43
44 /* Commit mode set by switch? */
45 mode {
46 label = "Mode";
47 linux,code = <KEY_SETUP>;
48 gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
49 };
50
51 /* Switch: AP mode */
52 sw_ap {
53 label = "AP";
54 linux,code = <BTN_0>;
55 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
56 };
57
58 eject {
59 label = "USB eject";
60 linux,code = <KEY_EJECTCD>;
61 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
62 };
63 };
64};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 3b5259de5a38..4ed7de1058b7 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -32,4 +32,63 @@
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34 }; 34 };
35
36 leds {
37 compatible = "gpio-leds";
38
39 logo {
40 label = "bcm53xx:white:logo";
41 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
42 linux,default-trigger = "default-on";
43 };
44
45 power0 {
46 label = "bcm53xx:green:power";
47 gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
48 linux,default-trigger = "default-off";
49 };
50
51 power1 {
52 label = "bcm53xx:amber:power";
53 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
54 linux,default-trigger = "default-on";
55 };
56
57 usb {
58 label = "bcm53xx:blue:usb";
59 gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
60 linux,default-trigger = "default-off";
61 };
62
63 wireless {
64 label = "bcm53xx:blue:wireless";
65 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
66 linux,default-trigger = "default-off";
67 };
68 };
69
70 gpio-keys {
71 compatible = "gpio-keys";
72 #address-cells = <1>;
73 #size-cells = <0>;
74 poll-interval = <200>;
75
76 wps {
77 label = "WPS";
78 linux,code = <KEY_WPS_BUTTON>;
79 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
80 };
81
82 rfkill {
83 label = "WiFi";
84 linux,code = <KEY_RFKILL>;
85 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
86 };
87
88 restart {
89 label = "Reset";
90 linux,code = <KEY_RESTART>;
91 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
92 };
93 };
35}; 94};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
new file mode 100644
index 000000000000..12fc2a01e6ab
--- /dev/null
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -0,0 +1,84 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Netgear R6300 V2
4 *
5 * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm4708.dtsi"
13
14/ {
15 compatible = "netgear,r6300v2", "brcm,bcm4708";
16 model = "Netgear R6300 V2 (BCM4708)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 logo {
30 label = "bcm53xx:white:logo";
31 gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
32 linux,default-trigger = "default-on";
33 };
34
35 power0 {
36 label = "bcm53xx:green:power";
37 gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "default-off";
39 };
40
41 power1 {
42 label = "bcm53xx:amber:power";
43 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
44 linux,default-trigger = "default-on";
45 };
46
47 usb {
48 label = "bcm53xx:blue:usb";
49 gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
50 linux,default-trigger = "default-off";
51 };
52
53 wireless {
54 label = "bcm53xx:blue:wireless";
55 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
56 linux,default-trigger = "default-off";
57 };
58 };
59
60 gpio-keys {
61 compatible = "gpio-keys";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 poll-interval = <200>;
65
66 wps {
67 label = "WPS";
68 linux,code = <KEY_WPS_BUTTON>;
69 gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
70 };
71
72 rfkill {
73 label = "WiFi";
74 linux,code = <KEY_RFKILL>;
75 gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
76 };
77
78 restart {
79 label = "Reset";
80 linux,code = <KEY_RESTART>;
81 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
82 };
83 };
84};
diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
new file mode 100644
index 000000000000..fb76378bd511
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts
@@ -0,0 +1,78 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Asus RT-N18U
4 *
5 * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm47081.dtsi"
13
14/ {
15 compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708";
16 model = "Asus RT-N18U (BCM47081)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 leds {
27 compatible = "gpio-leds";
28
29 power {
30 label = "bcm53xx:blue:power";
31 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
32 linux,default-trigger = "default-on";
33 };
34
35 usb2 {
36 label = "bcm53xx:blue:usb2";
37 gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
38 linux,default-trigger = "default-off";
39 };
40
41 wan {
42 label = "bcm53xx:blue:wan";
43 gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
44 linux,default-trigger = "default-on";
45 };
46
47 lan {
48 label = "bcm53xx:blue:lan";
49 gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
50 linux,default-trigger = "default-on";
51 };
52
53 usb3 {
54 label = "bcm53xx:blue:usb3";
55 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
56 linux,default-trigger = "default-off";
57 };
58 };
59
60 gpio-keys {
61 compatible = "gpio-keys";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 poll-interval = <200>;
65
66 restart {
67 label = "Reset";
68 linux,code = <KEY_RESTART>;
69 gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
70 };
71
72 wps {
73 label = "WPS";
74 linux,code = <KEY_WPS_BUTTON>;
75 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
76 };
77 };
78};
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
new file mode 100644
index 000000000000..bbb414fbad65
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
@@ -0,0 +1,57 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for Buffalo WZR-600DHP2
4 *
5 * Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10/dts-v1/;
11
12#include "bcm47081.dtsi"
13
14/ {
15 compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708";
16 model = "Buffalo WZR-600DHP2 (BCM47081)";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 memory {
23 reg = <0x00000000 0x08000000>;
24 };
25
26 gpio-keys {
27 compatible = "gpio-keys";
28 #address-cells = <1>;
29 #size-cells = <0>;
30 poll-interval = <200>;
31
32 aoss {
33 label = "AOSS";
34 linux,code = <KEY_WPS_BUTTON>;
35 gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
36 };
37
38 restart {
39 label = "Reset";
40 linux,code = <KEY_RESTART>;
41 gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
42 };
43
44 /* Switch device mode? */
45 mode {
46 label = "Mode";
47 linux,code = <KEY_SETUP>;
48 gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
49 };
50
51 eject {
52 label = "USB eject";
53 linux,code = <KEY_EJECTCD>;
54 gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
55 };
56 };
57};
diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi
new file mode 100644
index 000000000000..f720012ee5ed
--- /dev/null
+++ b/arch/arm/boot/dts/bcm47081.dtsi
@@ -0,0 +1,26 @@
1/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * DTS for BCM47081 SoC.
4 *
5 * Copyright © 2014 Rafał Miłecki <zajec5@gmail.com>
6 *
7 * Licensed under the GNU/GPL. See COPYING for details.
8 */
9
10#include "bcm5301x.dtsi"
11
12/ {
13 compatible = "brcm,bcm47081";
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 reg = <0x0>;
24 };
25 };
26};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 53c624f766b4..78aec6270c2f 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -8,6 +8,8 @@
8 * Licensed under the GNU/GPL. See COPYING for details. 8 * Licensed under the GNU/GPL. See COPYING for details.
9 */ 9 */
10 10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "skeleton.dtsi" 15#include "skeleton.dtsi"
@@ -92,4 +94,53 @@
92 clock-frequency = <400000000>; 94 clock-frequency = <400000000>;
93 }; 95 };
94 }; 96 };
97
98 axi@18000000 {
99 compatible = "brcm,bus-axi";
100 reg = <0x18000000 0x1000>;
101 ranges = <0x00000000 0x18000000 0x00100000>;
102 #address-cells = <1>;
103 #size-cells = <1>;
104
105 #interrupt-cells = <1>;
106 interrupt-map-mask = <0x000fffff 0xffff>;
107 interrupt-map =
108 /* ChipCommon */
109 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
110
111 /* USB 2.0 Controller */
112 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
113
114 /* USB 3.0 Controller */
115 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
116
117 /* Ethernet Controller 0 */
118 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
119
120 /* Ethernet Controller 1 */
121 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
122
123 /* Ethernet Controller 2 */
124 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
125
126 /* Ethernet Controller 3 */
127 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
128
129 /* NAND Controller */
130 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
131 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
132 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
133 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
134 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
135 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
136 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
137 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
138
139 chipcommon: chipcommon@0 {
140 reg = <0x00000000 0x1000>;
141
142 gpio-controller;
143 #gpio-cells = <2>;
144 };
145 };
95}; 146};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 000000000000..d2ee95280548
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
39 compatible = "brcm,bcm11360", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 000000000000..9658d4f62d59
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus SVK (BCM911360K)";
39 compatible = "brcm,bcm11360", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 000000000000..f1bb36f3975c
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,53 @@
1/*
2 * BSD LICENSE
3 *
4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/dts-v1/;
34
35#include "bcm-cygnus.dtsi"
36
37/ {
38 model = "Cygnus SVK (BCM958300K)";
39 compatible = "brcm,bcm58300", "brcm,cygnus";
40
41 aliases {
42 serial0 = &uart3;
43 };
44
45 chosen {
46 stdout-path = &uart3;
47 bootargs = "console=ttyS0,115200";
48 };
49
50 uart3: serial@18023000 {
51 status = "okay";
52 };
53};
diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
index c72bfd468d10..86d85d8896a3 100644
--- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
+++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts
@@ -26,4 +26,20 @@
26 }; 26 };
27}; 27};
28 28
29&ahci { status = "okay"; };
30
31&eth1 { status = "okay"; };
32
33/* Unpopulated SATA plug on solder side */
34&sata0 { status = "okay"; };
35
36&sata_phy { status = "okay"; };
37
38/* Samsung M8G2FA 8GB eMMC */
39&sdhci2 {
40 non-removable;
41 bus-width = <8>;
42 status = "okay";
43};
44
29&uart0 { status = "okay"; }; 45&uart0 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 9d7c810ebd0b..015a06c67c91 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -53,6 +53,35 @@
53 53
54 ranges = <0 0xf7000000 0x1000000>; 54 ranges = <0 0xf7000000 0x1000000>;
55 55
56 sdhci0: sdhci@ab0000 {
57 compatible = "mrvl,pxav3-mmc";
58 reg = <0xab0000 0x200>;
59 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
60 clock-names = "io", "core";
61 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
62 status = "disabled";
63 };
64
65 sdhci1: sdhci@ab0800 {
66 compatible = "mrvl,pxav3-mmc";
67 reg = <0xab0800 0x200>;
68 clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
69 clock-names = "io", "core";
70 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
71 status = "disabled";
72 };
73
74 sdhci2: sdhci@ab1000 {
75 compatible = "mrvl,pxav3-mmc";
76 reg = <0xab1000 0x200>;
77 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
78 clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>;
79 clock-names = "io", "core";
80 pinctrl-0 = <&emmc_pmux>;
81 pinctrl-names = "default";
82 status = "disabled";
83 };
84
56 l2: l2-cache-controller@ac0000 { 85 l2: l2-cache-controller@ac0000 {
57 compatible = "marvell,tauros3-cache", "arm,pl310-cache"; 86 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
58 reg = <0xac0000 0x1000>; 87 reg = <0xac0000 0x1000>;
@@ -79,11 +108,47 @@
79 clocks = <&chip CLKID_TWD>; 108 clocks = <&chip CLKID_TWD>;
80 }; 109 };
81 110
111 eth1: ethernet@b90000 {
112 compatible = "marvell,pxa168-eth";
113 reg = <0xb90000 0x10000>;
114 clocks = <&chip CLKID_GETH1>;
115 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
116 /* set by bootloader */
117 local-mac-address = [00 00 00 00 00 00];
118 #address-cells = <1>;
119 #size-cells = <0>;
120 phy-connection-type = "mii";
121 phy-handle = <&ethphy1>;
122 status = "disabled";
123
124 ethphy1: ethernet-phy@0 {
125 reg = <0>;
126 };
127 };
128
82 cpu-ctrl@dd0000 { 129 cpu-ctrl@dd0000 {
83 compatible = "marvell,berlin-cpu-ctrl"; 130 compatible = "marvell,berlin-cpu-ctrl";
84 reg = <0xdd0000 0x10000>; 131 reg = <0xdd0000 0x10000>;
85 }; 132 };
86 133
134 eth0: ethernet@e50000 {
135 compatible = "marvell,pxa168-eth";
136 reg = <0xe50000 0x10000>;
137 clocks = <&chip CLKID_GETH0>;
138 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
139 /* set by bootloader */
140 local-mac-address = [00 00 00 00 00 00];
141 #address-cells = <1>;
142 #size-cells = <0>;
143 phy-connection-type = "mii";
144 phy-handle = <&ethphy0>;
145 status = "disabled";
146
147 ethphy0: ethernet-phy@0 {
148 reg = <0>;
149 };
150 };
151
87 apb@e80000 { 152 apb@e80000 {
88 compatible = "simple-bus"; 153 compatible = "simple-bus";
89 #address-cells = <1>; 154 #address-cells = <1>;
@@ -246,12 +311,57 @@
246 }; 311 };
247 }; 312 };
248 313
314 ahci: sata@e90000 {
315 compatible = "marvell,berlin2-ahci", "generic-ahci";
316 reg = <0xe90000 0x1000>;
317 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&chip CLKID_SATA>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321
322 sata0: sata-port@0 {
323 reg = <0>;
324 phys = <&sata_phy 0>;
325 status = "disabled";
326 };
327
328 sata1: sata-port@1 {
329 reg = <1>;
330 phys = <&sata_phy 1>;
331 status = "disabled";
332 };
333 };
334
335 sata_phy: phy@e900a0 {
336 compatible = "marvell,berlin2-sata-phy";
337 reg = <0xe900a0 0x200>;
338 clocks = <&chip CLKID_SATA>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 #phy-cells = <1>;
342 status = "disabled";
343
344 sata-phy@0 {
345 reg = <0>;
346 };
347
348 sata-phy@1 {
349 reg = <1>;
350 };
351 };
352
249 chip: chip-control@ea0000 { 353 chip: chip-control@ea0000 {
250 compatible = "marvell,berlin2-chip-ctrl"; 354 compatible = "marvell,berlin2-chip-ctrl";
251 #clock-cells = <1>; 355 #clock-cells = <1>;
356 #reset-cells = <2>;
252 reg = <0xea0000 0x400>; 357 reg = <0xea0000 0x400>;
253 clocks = <&refclk>; 358 clocks = <&refclk>;
254 clock-names = "refclk"; 359 clock-names = "refclk";
360
361 emmc_pmux: emmc-pmux {
362 groups = "G26";
363 function = "emmc";
364 };
255 }; 365 };
256 366
257 apb@fc0000 { 367 apb@fc0000 {
diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
index bcd81ffc495d..30270be4d0c9 100644
--- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
+++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts
@@ -11,6 +11,7 @@
11/dts-v1/; 11/dts-v1/;
12 12
13#include "berlin2cd.dtsi" 13#include "berlin2cd.dtsi"
14#include <dt-bindings/gpio/gpio.h>
14 15
15/ { 16/ {
16 model = "Google Chromecast"; 17 model = "Google Chromecast";
@@ -24,6 +25,35 @@
24 device_type = "memory"; 25 device_type = "memory";
25 reg = <0x00000000 0x20000000>; /* 512 MB */ 26 reg = <0x00000000 0x20000000>; /* 512 MB */
26 }; 27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 white {
33 label = "white";
34 gpios = <&portc 1 GPIO_ACTIVE_HIGH>;
35 default-state = "keep";
36 };
37
38 red {
39 label = "red";
40 gpios = <&portc 2 GPIO_ACTIVE_HIGH>;
41 default-state = "keep";
42 };
43 };
44};
45
46/*
47 * AzureWave AW-NH387 (Marvell 88W8787)
48 * 802.11b/g/n + Bluetooth 2.1
49 */
50&sdhci0 {
51 non-removable;
52 status = "okay";
27}; 53};
28 54
29&uart0 { status = "okay"; }; 55&uart0 { status = "okay"; };
56
57&usb_phy1 { status = "okay"; };
58
59&usb1 { status = "okay"; };
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index cc1df65da504..230df3b1770e 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -45,6 +45,15 @@
45 45
46 ranges = <0 0xf7000000 0x1000000>; 46 ranges = <0 0xf7000000 0x1000000>;
47 47
48 sdhci0: sdhci@ab0000 {
49 compatible = "mrvl,pxav3-mmc";
50 reg = <0xab0000 0x200>;
51 clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>;
52 clock-names = "io", "core";
53 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
54 status = "disabled";
55 };
56
48 l2: l2-cache-controller@ac0000 { 57 l2: l2-cache-controller@ac0000 {
49 compatible = "arm,pl310-cache"; 58 compatible = "arm,pl310-cache";
50 reg = <0xac0000 0x1000>; 59 reg = <0xac0000 0x1000>;
@@ -66,6 +75,58 @@
66 clocks = <&chip CLKID_TWD>; 75 clocks = <&chip CLKID_TWD>;
67 }; 76 };
68 77
78 usb_phy0: usb-phy@b74000 {
79 compatible = "marvell,berlin2cd-usb-phy";
80 reg = <0xb74000 0x128>;
81 #phy-cells = <0>;
82 resets = <&chip 0x178 23>;
83 status = "disabled";
84 };
85
86 usb_phy1: usb-phy@b78000 {
87 compatible = "marvell,berlin2cd-usb-phy";
88 reg = <0xb78000 0x128>;
89 #phy-cells = <0>;
90 resets = <&chip 0x178 24>;
91 status = "disabled";
92 };
93
94 eth1: ethernet@b90000 {
95 compatible = "marvell,pxa168-eth";
96 reg = <0xb90000 0x10000>;
97 clocks = <&chip CLKID_GETH1>;
98 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
99 /* set by bootloader */
100 local-mac-address = [00 00 00 00 00 00];
101 #address-cells = <1>;
102 #size-cells = <0>;
103 phy-connection-type = "mii";
104 phy-handle = <&ethphy1>;
105 status = "disabled";
106
107 ethphy1: ethernet-phy@0 {
108 reg = <0>;
109 };
110 };
111
112 eth0: ethernet@e50000 {
113 compatible = "marvell,pxa168-eth";
114 reg = <0xe50000 0x10000>;
115 clocks = <&chip CLKID_GETH0>;
116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
117 /* set by bootloader */
118 local-mac-address = [00 00 00 00 00 00];
119 #address-cells = <1>;
120 #size-cells = <0>;
121 phy-connection-type = "mii";
122 phy-handle = <&ethphy0>;
123 status = "disabled";
124
125 ethphy0: ethernet-phy@0 {
126 reg = <0>;
127 };
128 };
129
69 apb@e80000 { 130 apb@e80000 {
70 compatible = "simple-bus"; 131 compatible = "simple-bus";
71 #address-cells = <1>; 132 #address-cells = <1>;
@@ -231,6 +292,7 @@
231 chip: chip-control@ea0000 { 292 chip: chip-control@ea0000 {
232 compatible = "marvell,berlin2cd-chip-ctrl"; 293 compatible = "marvell,berlin2cd-chip-ctrl";
233 #clock-cells = <1>; 294 #clock-cells = <1>;
295 #reset-cells = <2>;
234 reg = <0xea0000 0x400>; 296 reg = <0xea0000 0x400>;
235 clocks = <&refclk>; 297 clocks = <&refclk>;
236 clock-names = "refclk"; 298 clock-names = "refclk";
@@ -241,6 +303,26 @@
241 }; 303 };
242 }; 304 };
243 305
306 usb0: usb@ed0000 {
307 compatible = "chipidea,usb2";
308 reg = <0xed0000 0x200>;
309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&chip CLKID_USB0>;
311 phys = <&usb_phy0>;
312 phy-names = "usb-phy";
313 status = "disabled";
314 };
315
316 usb1: usb@ee0000 {
317 compatible = "chipidea,usb2";
318 reg = <0xee0000 0x200>;
319 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&chip CLKID_USB1>;
321 phys = <&usb_phy1>;
322 phy-names = "usb-phy";
323 status = "disabled";
324 };
325
244 apb@fc0000 { 326 apb@fc0000 {
245 compatible = "simple-bus"; 327 compatible = "simple-bus";
246 #address-cells = <1>; 328 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index ea1f99b8eed6..28e7e2060c33 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -7,6 +7,8 @@
7 */ 7 */
8 8
9/dts-v1/; 9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
10#include "berlin2q.dtsi" 12#include "berlin2q.dtsi"
11 13
12/ { 14/ {
@@ -21,6 +23,39 @@
21 choosen { 23 choosen {
22 bootargs = "console=ttyS0,115200 earlyprintk"; 24 bootargs = "console=ttyS0,115200 earlyprintk";
23 }; 25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb0_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 regulator-name = "usb0_vbus";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 gpio = <&portb 8 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40
41 reg_usb1_vbus: regulator@1 {
42 compatible = "regulator-fixed";
43 regulator-name = "usb1_vbus";
44 regulator-min-microvolt = <5000000>;
45 regulator-max-microvolt = <5000000>;
46 gpio = <&portb 10 GPIO_ACTIVE_HIGH>;
47 enable-active-high;
48 };
49
50 reg_usb2_vbus: regulator@2 {
51 compatible = "regulator-fixed";
52 regulator-name = "usb2_vbus";
53 regulator-min-microvolt = <5000000>;
54 regulator-max-microvolt = <5000000>;
55 gpio = <&portb 12 GPIO_ACTIVE_HIGH>;
56 enable-active-high;
57 };
58 };
24}; 59};
25 60
26&sdhci1 { 61&sdhci1 {
@@ -46,6 +81,32 @@
46 status = "okay"; 81 status = "okay";
47}; 82};
48 83
84&usb_phy0 {
85 status = "okay";
86};
87
88&usb_phy2 {
89 status = "okay";
90};
91
92&usb0 {
93 vbus-supply = <&reg_usb0_vbus>;
94 status = "okay";
95};
96
97&usb2 {
98 vbus-supply = <&reg_usb2_vbus>;
99 status = "okay";
100};
101
49&eth0 { 102&eth0 {
50 status = "okay"; 103 status = "okay";
51}; 104};
105
106&sata0 {
107 status = "okay";
108};
109
110&sata_phy {
111 status = "okay";
112};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 891d56b03922..35253c947a7c 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -114,6 +114,40 @@
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 }; 115 };
116 116
117 usb_phy2: phy@a2f400 {
118 compatible = "marvell,berlin2-usb-phy";
119 reg = <0xa2f400 0x128>;
120 #phy-cells = <0>;
121 resets = <&chip 0x104 14>;
122 status = "disabled";
123 };
124
125 usb2: usb@a30000 {
126 compatible = "chipidea,usb2";
127 reg = <0xa30000 0x10000>;
128 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&chip CLKID_USB2>;
130 phys = <&usb_phy2>;
131 phy-names = "usb-phy";
132 status = "disabled";
133 };
134
135 usb_phy0: phy@b74000 {
136 compatible = "marvell,berlin2-usb-phy";
137 reg = <0xb74000 0x128>;
138 #phy-cells = <0>;
139 resets = <&chip 0x104 12>;
140 status = "disabled";
141 };
142
143 usb_phy1: phy@b78000 {
144 compatible = "marvell,berlin2-usb-phy";
145 reg = <0xb78000 0x128>;
146 #phy-cells = <0>;
147 resets = <&chip 0x104 13>;
148 status = "disabled";
149 };
150
117 eth0: ethernet@b90000 { 151 eth0: ethernet@b90000 {
118 compatible = "marvell,pxa168-eth"; 152 compatible = "marvell,pxa168-eth";
119 reg = <0xb90000 0x10000>; 153 reg = <0xb90000 0x10000>;
@@ -123,6 +157,7 @@
123 local-mac-address = [00 00 00 00 00 00]; 157 local-mac-address = [00 00 00 00 00 00];
124 #address-cells = <1>; 158 #address-cells = <1>;
125 #size-cells = <0>; 159 #size-cells = <0>;
160 phy-connection-type = "mii";
126 phy-handle = <&ethphy0>; 161 phy-handle = <&ethphy0>;
127 status = "disabled"; 162 status = "disabled";
128 163
@@ -255,7 +290,6 @@
255 reg = <0x2c14 0x14>; 290 reg = <0x2c14 0x14>;
256 clocks = <&chip CLKID_CFG>; 291 clocks = <&chip CLKID_CFG>;
257 clock-names = "timer"; 292 clock-names = "timer";
258 status = "disabled";
259 }; 293 };
260 294
261 timer2: timer@2c28 { 295 timer2: timer@2c28 {
@@ -349,6 +383,7 @@
349 chip: chip-control@ea0000 { 383 chip: chip-control@ea0000 {
350 compatible = "marvell,berlin2q-chip-ctrl"; 384 compatible = "marvell,berlin2q-chip-ctrl";
351 #clock-cells = <1>; 385 #clock-cells = <1>;
386 #reset-cells = <2>;
352 reg = <0xea0000 0x400>, <0xdd0170 0x10>; 387 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
353 clocks = <&refclk>; 388 clocks = <&refclk>;
354 clock-names = "refclk"; 389 clock-names = "refclk";
@@ -364,6 +399,65 @@
364 }; 399 };
365 }; 400 };
366 401
402 ahci: sata@e90000 {
403 compatible = "marvell,berlin2q-ahci", "generic-ahci";
404 reg = <0xe90000 0x1000>;
405 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&chip CLKID_SATA>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409
410 sata0: sata-port@0 {
411 reg = <0>;
412 phys = <&sata_phy 0>;
413 status = "disabled";
414 };
415
416 sata1: sata-port@1 {
417 reg = <1>;
418 phys = <&sata_phy 1>;
419 status = "disabled";
420 };
421 };
422
423 sata_phy: phy@e900a0 {
424 compatible = "marvell,berlin2q-sata-phy";
425 reg = <0xe900a0 0x200>;
426 clocks = <&chip CLKID_SATA>;
427 #address-cells = <1>;
428 #size-cells = <0>;
429 #phy-cells = <1>;
430 status = "disabled";
431
432 sata-phy@0 {
433 reg = <0>;
434 };
435
436 sata-phy@1 {
437 reg = <1>;
438 };
439 };
440
441 usb0: usb@ed0000 {
442 compatible = "chipidea,usb2";
443 reg = <0xed0000 0x10000>;
444 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&chip CLKID_USB0>;
446 phys = <&usb_phy0>;
447 phy-names = "usb-phy";
448 status = "disabled";
449 };
450
451 usb1: usb@ee0000 {
452 compatible = "chipidea,usb2";
453 reg = <0xee0000 0x10000>;
454 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&chip CLKID_USB1>;
456 phys = <&usb_phy1>;
457 phy-names = "usb-phy";
458 status = "disabled";
459 };
460
367 apb@fc0000 { 461 apb@fc0000 {
368 compatible = "simple-bus"; 462 compatible = "simple-bus";
369 #address-cells = <1>; 463 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index c6ce6258434f..736092b1a535 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -171,6 +171,101 @@
171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ 171 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
172 >; 172 >;
173 }; 173 };
174
175 cpsw_default: cpsw_default {
176 pinctrl-single,pins = <
177 /* Slave 1 */
178 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
179 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
180 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
181 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
182 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
183 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
184 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
185 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
186 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
187 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
188 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
189 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
190
191 /* Slave 2 */
192 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
193 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
194 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
195 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
196 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
197 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
198 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
199 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
200 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
201 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
202 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
203 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
204 >;
205
206 };
207
208 cpsw_sleep: cpsw_sleep {
209 pinctrl-single,pins = <
210 /* Slave 1 */
211 0x250 (MUX_MODE15)
212 0x254 (MUX_MODE15)
213 0x258 (MUX_MODE15)
214 0x25c (MUX_MODE15)
215 0x260 (MUX_MODE15)
216 0x264 (MUX_MODE15)
217 0x268 (MUX_MODE15)
218 0x26c (MUX_MODE15)
219 0x270 (MUX_MODE15)
220 0x274 (MUX_MODE15)
221 0x278 (MUX_MODE15)
222 0x27c (MUX_MODE15)
223
224 /* Slave 2 */
225 0x198 (MUX_MODE15)
226 0x19c (MUX_MODE15)
227 0x1a0 (MUX_MODE15)
228 0x1a4 (MUX_MODE15)
229 0x1a8 (MUX_MODE15)
230 0x1ac (MUX_MODE15)
231 0x1b0 (MUX_MODE15)
232 0x1b4 (MUX_MODE15)
233 0x1b8 (MUX_MODE15)
234 0x1bc (MUX_MODE15)
235 0x1c0 (MUX_MODE15)
236 0x1c4 (MUX_MODE15)
237 >;
238 };
239
240 davinci_mdio_default: davinci_mdio_default {
241 pinctrl-single,pins = <
242 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
243 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
244 >;
245 };
246
247 davinci_mdio_sleep: davinci_mdio_sleep {
248 pinctrl-single,pins = <
249 0x23c (MUX_MODE15)
250 0x240 (MUX_MODE15)
251 >;
252 };
253
254 dcan1_pins_default: dcan1_pins_default {
255 pinctrl-single,pins = <
256 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
257 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
258 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
259 >;
260 };
261
262 dcan1_pins_sleep: dcan1_pins_sleep {
263 pinctrl-single,pins = <
264 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
265 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
266 0x418 (MUX_MODE15) /* wakeup0.off */
267 >;
268 };
174}; 269};
175 270
176&i2c1 { 271&i2c1 {
@@ -201,6 +296,7 @@
201 regulator-name = "smps45"; 296 regulator-name = "smps45";
202 regulator-min-microvolt = < 850000>; 297 regulator-min-microvolt = < 850000>;
203 regulator-max-microvolt = <1150000>; 298 regulator-max-microvolt = <1150000>;
299 regulator-always-on;
204 regulator-boot-on; 300 regulator-boot-on;
205 }; 301 };
206 302
@@ -209,6 +305,7 @@
209 regulator-name = "smps6"; 305 regulator-name = "smps6";
210 regulator-min-microvolt = <850000>; 306 regulator-min-microvolt = <850000>;
211 regulator-max-microvolt = <12500000>; 307 regulator-max-microvolt = <12500000>;
308 regulator-always-on;
212 regulator-boot-on; 309 regulator-boot-on;
213 }; 310 };
214 311
@@ -226,6 +323,7 @@
226 regulator-name = "smps8"; 323 regulator-name = "smps8";
227 regulator-min-microvolt = < 850000>; 324 regulator-min-microvolt = < 850000>;
228 regulator-max-microvolt = <1250000>; 325 regulator-max-microvolt = <1250000>;
326 regulator-always-on;
229 regulator-boot-on; 327 regulator-boot-on;
230 }; 328 };
231 329
@@ -252,6 +350,7 @@
252 regulator-name = "ldo2"; 350 regulator-name = "ldo2";
253 regulator-min-microvolt = <3300000>; 351 regulator-min-microvolt = <3300000>;
254 regulator-max-microvolt = <3300000>; 352 regulator-max-microvolt = <3300000>;
353 regulator-always-on;
255 regulator-boot-on; 354 regulator-boot-on;
256 }; 355 };
257 356
@@ -269,6 +368,7 @@
269 regulator-name = "ldo9"; 368 regulator-name = "ldo9";
270 regulator-min-microvolt = <1050000>; 369 regulator-min-microvolt = <1050000>;
271 regulator-max-microvolt = <1050000>; 370 regulator-max-microvolt = <1050000>;
371 regulator-always-on;
272 regulator-boot-on; 372 regulator-boot-on;
273 }; 373 };
274 374
@@ -528,3 +628,36 @@
528 ti,no-reset-on-init; 628 ti,no-reset-on-init;
529 ti,no-idle-on-init; 629 ti,no-idle-on-init;
530}; 630};
631
632&mac {
633 status = "okay";
634 pinctrl-names = "default", "sleep";
635 pinctrl-0 = <&cpsw_default>;
636 pinctrl-1 = <&cpsw_sleep>;
637 dual_emac;
638};
639
640&cpsw_emac0 {
641 phy_id = <&davinci_mdio>, <2>;
642 phy-mode = "rgmii";
643 dual_emac_res_vlan = <1>;
644};
645
646&cpsw_emac1 {
647 phy_id = <&davinci_mdio>, <3>;
648 phy-mode = "rgmii";
649 dual_emac_res_vlan = <2>;
650};
651
652&davinci_mdio {
653 pinctrl-names = "default", "sleep";
654 pinctrl-0 = <&davinci_mdio_default>;
655 pinctrl-1 = <&davinci_mdio_sleep>;
656};
657
658&dcan1 {
659 status = "ok";
660 pinctrl-names = "default", "sleep";
661 pinctrl-0 = <&dcan1_pins_default>;
662 pinctrl-1 = <&dcan1_pins_sleep>;
663};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 9cc98436a982..63bf99be1762 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -34,6 +34,14 @@
34 serial3 = &uart4; 34 serial3 = &uart4;
35 serial4 = &uart5; 35 serial4 = &uart5;
36 serial5 = &uart6; 36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
39 serial8 = &uart9;
40 serial9 = &uart10;
41 ethernet0 = &cpsw_emac0;
42 ethernet1 = &cpsw_emac1;
43 d_can0 = &dcan1;
44 d_can1 = &dcan2;
37 }; 45 };
38 46
39 timer { 47 timer {
@@ -201,6 +209,11 @@
201 ti,hwmods = "counter_32k"; 209 ti,hwmods = "counter_32k";
202 }; 210 };
203 211
212 dra7_ctrl_core: ctrl_core@4a002000 {
213 compatible = "syscon";
214 reg = <0x4a002000 0x6d0>;
215 };
216
204 dra7_ctrl_general: tisyscon@4a002e00 { 217 dra7_ctrl_general: tisyscon@4a002e00 {
205 compatible = "syscon"; 218 compatible = "syscon";
206 reg = <0x4a002e00 0x7c>; 219 reg = <0x4a002e00 0x7c>;
@@ -335,6 +348,8 @@
335 ti,hwmods = "uart1"; 348 ti,hwmods = "uart1";
336 clock-frequency = <48000000>; 349 clock-frequency = <48000000>;
337 status = "disabled"; 350 status = "disabled";
351 dmas = <&sdma 49>, <&sdma 50>;
352 dma-names = "tx", "rx";
338 }; 353 };
339 354
340 uart2: serial@4806c000 { 355 uart2: serial@4806c000 {
@@ -344,6 +359,8 @@
344 ti,hwmods = "uart2"; 359 ti,hwmods = "uart2";
345 clock-frequency = <48000000>; 360 clock-frequency = <48000000>;
346 status = "disabled"; 361 status = "disabled";
362 dmas = <&sdma 51>, <&sdma 52>;
363 dma-names = "tx", "rx";
347 }; 364 };
348 365
349 uart3: serial@48020000 { 366 uart3: serial@48020000 {
@@ -353,6 +370,8 @@
353 ti,hwmods = "uart3"; 370 ti,hwmods = "uart3";
354 clock-frequency = <48000000>; 371 clock-frequency = <48000000>;
355 status = "disabled"; 372 status = "disabled";
373 dmas = <&sdma 53>, <&sdma 54>;
374 dma-names = "tx", "rx";
356 }; 375 };
357 376
358 uart4: serial@4806e000 { 377 uart4: serial@4806e000 {
@@ -362,6 +381,8 @@
362 ti,hwmods = "uart4"; 381 ti,hwmods = "uart4";
363 clock-frequency = <48000000>; 382 clock-frequency = <48000000>;
364 status = "disabled"; 383 status = "disabled";
384 dmas = <&sdma 55>, <&sdma 56>;
385 dma-names = "tx", "rx";
365 }; 386 };
366 387
367 uart5: serial@48066000 { 388 uart5: serial@48066000 {
@@ -371,6 +392,8 @@
371 ti,hwmods = "uart5"; 392 ti,hwmods = "uart5";
372 clock-frequency = <48000000>; 393 clock-frequency = <48000000>;
373 status = "disabled"; 394 status = "disabled";
395 dmas = <&sdma 63>, <&sdma 64>;
396 dma-names = "tx", "rx";
374 }; 397 };
375 398
376 uart6: serial@48068000 { 399 uart6: serial@48068000 {
@@ -380,6 +403,8 @@
380 ti,hwmods = "uart6"; 403 ti,hwmods = "uart6";
381 clock-frequency = <48000000>; 404 clock-frequency = <48000000>;
382 status = "disabled"; 405 status = "disabled";
406 dmas = <&sdma 79>, <&sdma 80>;
407 dma-names = "tx", "rx";
383 }; 408 };
384 409
385 uart7: serial@48420000 { 410 uart7: serial@48420000 {
@@ -421,7 +446,11 @@
421 mailbox1: mailbox@4a0f4000 { 446 mailbox1: mailbox@4a0f4000 {
422 compatible = "ti,omap4-mailbox"; 447 compatible = "ti,omap4-mailbox";
423 reg = <0x4a0f4000 0x200>; 448 reg = <0x4a0f4000 0x200>;
449 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
424 ti,hwmods = "mailbox1"; 452 ti,hwmods = "mailbox1";
453 #mbox-cells = <1>;
425 ti,mbox-num-users = <3>; 454 ti,mbox-num-users = <3>;
426 ti,mbox-num-fifos = <8>; 455 ti,mbox-num-fifos = <8>;
427 status = "disabled"; 456 status = "disabled";
@@ -430,7 +459,12 @@
430 mailbox2: mailbox@4883a000 { 459 mailbox2: mailbox@4883a000 {
431 compatible = "ti,omap4-mailbox"; 460 compatible = "ti,omap4-mailbox";
432 reg = <0x4883a000 0x200>; 461 reg = <0x4883a000 0x200>;
462 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
433 ti,hwmods = "mailbox2"; 466 ti,hwmods = "mailbox2";
467 #mbox-cells = <1>;
434 ti,mbox-num-users = <4>; 468 ti,mbox-num-users = <4>;
435 ti,mbox-num-fifos = <12>; 469 ti,mbox-num-fifos = <12>;
436 status = "disabled"; 470 status = "disabled";
@@ -439,7 +473,12 @@
439 mailbox3: mailbox@4883c000 { 473 mailbox3: mailbox@4883c000 {
440 compatible = "ti,omap4-mailbox"; 474 compatible = "ti,omap4-mailbox";
441 reg = <0x4883c000 0x200>; 475 reg = <0x4883c000 0x200>;
476 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
442 ti,hwmods = "mailbox3"; 480 ti,hwmods = "mailbox3";
481 #mbox-cells = <1>;
443 ti,mbox-num-users = <4>; 482 ti,mbox-num-users = <4>;
444 ti,mbox-num-fifos = <12>; 483 ti,mbox-num-fifos = <12>;
445 status = "disabled"; 484 status = "disabled";
@@ -448,7 +487,12 @@
448 mailbox4: mailbox@4883e000 { 487 mailbox4: mailbox@4883e000 {
449 compatible = "ti,omap4-mailbox"; 488 compatible = "ti,omap4-mailbox";
450 reg = <0x4883e000 0x200>; 489 reg = <0x4883e000 0x200>;
490 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
451 ti,hwmods = "mailbox4"; 494 ti,hwmods = "mailbox4";
495 #mbox-cells = <1>;
452 ti,mbox-num-users = <4>; 496 ti,mbox-num-users = <4>;
453 ti,mbox-num-fifos = <12>; 497 ti,mbox-num-fifos = <12>;
454 status = "disabled"; 498 status = "disabled";
@@ -457,7 +501,12 @@
457 mailbox5: mailbox@48840000 { 501 mailbox5: mailbox@48840000 {
458 compatible = "ti,omap4-mailbox"; 502 compatible = "ti,omap4-mailbox";
459 reg = <0x48840000 0x200>; 503 reg = <0x48840000 0x200>;
504 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
460 ti,hwmods = "mailbox5"; 508 ti,hwmods = "mailbox5";
509 #mbox-cells = <1>;
461 ti,mbox-num-users = <4>; 510 ti,mbox-num-users = <4>;
462 ti,mbox-num-fifos = <12>; 511 ti,mbox-num-fifos = <12>;
463 status = "disabled"; 512 status = "disabled";
@@ -466,7 +515,12 @@
466 mailbox6: mailbox@48842000 { 515 mailbox6: mailbox@48842000 {
467 compatible = "ti,omap4-mailbox"; 516 compatible = "ti,omap4-mailbox";
468 reg = <0x48842000 0x200>; 517 reg = <0x48842000 0x200>;
518 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "mailbox6"; 522 ti,hwmods = "mailbox6";
523 #mbox-cells = <1>;
470 ti,mbox-num-users = <4>; 524 ti,mbox-num-users = <4>;
471 ti,mbox-num-fifos = <12>; 525 ti,mbox-num-fifos = <12>;
472 status = "disabled"; 526 status = "disabled";
@@ -475,7 +529,12 @@
475 mailbox7: mailbox@48844000 { 529 mailbox7: mailbox@48844000 {
476 compatible = "ti,omap4-mailbox"; 530 compatible = "ti,omap4-mailbox";
477 reg = <0x48844000 0x200>; 531 reg = <0x48844000 0x200>;
532 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
478 ti,hwmods = "mailbox7"; 536 ti,hwmods = "mailbox7";
537 #mbox-cells = <1>;
479 ti,mbox-num-users = <4>; 538 ti,mbox-num-users = <4>;
480 ti,mbox-num-fifos = <12>; 539 ti,mbox-num-fifos = <12>;
481 status = "disabled"; 540 status = "disabled";
@@ -484,7 +543,12 @@
484 mailbox8: mailbox@48846000 { 543 mailbox8: mailbox@48846000 {
485 compatible = "ti,omap4-mailbox"; 544 compatible = "ti,omap4-mailbox";
486 reg = <0x48846000 0x200>; 545 reg = <0x48846000 0x200>;
546 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
487 ti,hwmods = "mailbox8"; 550 ti,hwmods = "mailbox8";
551 #mbox-cells = <1>;
488 ti,mbox-num-users = <4>; 552 ti,mbox-num-users = <4>;
489 ti,mbox-num-fifos = <12>; 553 ti,mbox-num-fifos = <12>;
490 status = "disabled"; 554 status = "disabled";
@@ -493,7 +557,12 @@
493 mailbox9: mailbox@4885e000 { 557 mailbox9: mailbox@4885e000 {
494 compatible = "ti,omap4-mailbox"; 558 compatible = "ti,omap4-mailbox";
495 reg = <0x4885e000 0x200>; 559 reg = <0x4885e000 0x200>;
560 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
496 ti,hwmods = "mailbox9"; 564 ti,hwmods = "mailbox9";
565 #mbox-cells = <1>;
497 ti,mbox-num-users = <4>; 566 ti,mbox-num-users = <4>;
498 ti,mbox-num-fifos = <12>; 567 ti,mbox-num-fifos = <12>;
499 status = "disabled"; 568 status = "disabled";
@@ -502,7 +571,12 @@
502 mailbox10: mailbox@48860000 { 571 mailbox10: mailbox@48860000 {
503 compatible = "ti,omap4-mailbox"; 572 compatible = "ti,omap4-mailbox";
504 reg = <0x48860000 0x200>; 573 reg = <0x48860000 0x200>;
574 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "mailbox10"; 578 ti,hwmods = "mailbox10";
579 #mbox-cells = <1>;
506 ti,mbox-num-users = <4>; 580 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <12>; 581 ti,mbox-num-fifos = <12>;
508 status = "disabled"; 582 status = "disabled";
@@ -511,7 +585,12 @@
511 mailbox11: mailbox@48862000 { 585 mailbox11: mailbox@48862000 {
512 compatible = "ti,omap4-mailbox"; 586 compatible = "ti,omap4-mailbox";
513 reg = <0x48862000 0x200>; 587 reg = <0x48862000 0x200>;
588 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
514 ti,hwmods = "mailbox11"; 592 ti,hwmods = "mailbox11";
593 #mbox-cells = <1>;
515 ti,mbox-num-users = <4>; 594 ti,mbox-num-users = <4>;
516 ti,mbox-num-fifos = <12>; 595 ti,mbox-num-fifos = <12>;
517 status = "disabled"; 596 status = "disabled";
@@ -520,7 +599,12 @@
520 mailbox12: mailbox@48864000 { 599 mailbox12: mailbox@48864000 {
521 compatible = "ti,omap4-mailbox"; 600 compatible = "ti,omap4-mailbox";
522 reg = <0x48864000 0x200>; 601 reg = <0x48864000 0x200>;
602 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
523 ti,hwmods = "mailbox12"; 606 ti,hwmods = "mailbox12";
607 #mbox-cells = <1>;
524 ti,mbox-num-users = <4>; 608 ti,mbox-num-users = <4>;
525 ti,mbox-num-fifos = <12>; 609 ti,mbox-num-fifos = <12>;
526 status = "disabled"; 610 status = "disabled";
@@ -529,7 +613,12 @@
529 mailbox13: mailbox@48802000 { 613 mailbox13: mailbox@48802000 {
530 compatible = "ti,omap4-mailbox"; 614 compatible = "ti,omap4-mailbox";
531 reg = <0x48802000 0x200>; 615 reg = <0x48802000 0x200>;
616 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "mailbox13"; 620 ti,hwmods = "mailbox13";
621 #mbox-cells = <1>;
533 ti,mbox-num-users = <4>; 622 ti,mbox-num-users = <4>;
534 ti,mbox-num-fifos = <12>; 623 ti,mbox-num-fifos = <12>;
535 status = "disabled"; 624 status = "disabled";
@@ -1075,6 +1164,15 @@
1075 status = "disabled"; 1164 status = "disabled";
1076 }; 1165 };
1077 1166
1167 rtc@48838000 {
1168 compatible = "ti,am3352-rtc";
1169 reg = <0x48838000 0x100>;
1170 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1172 ti,hwmods = "rtcss";
1173 clocks = <&sys_32k_ck>;
1174 };
1175
1078 omap_control_usb2phy1: control-phy@4a002300 { 1176 omap_control_usb2phy1: control-phy@4a002300 {
1079 compatible = "ti,control-phy-usb2"; 1177 compatible = "ti,control-phy-usb2";
1080 reg = <0x4a002300 0x4>; 1178 reg = <0x4a002300 0x4>;
@@ -1141,7 +1239,7 @@
1141 }; 1239 };
1142 }; 1240 };
1143 1241
1144 omap_dwc3_1@48880000 { 1242 omap_dwc3_1: omap_dwc3_1@48880000 {
1145 compatible = "ti,dwc3"; 1243 compatible = "ti,dwc3";
1146 ti,hwmods = "usb_otg_ss1"; 1244 ti,hwmods = "usb_otg_ss1";
1147 reg = <0x48880000 0x10000>; 1245 reg = <0x48880000 0x10000>;
@@ -1162,7 +1260,7 @@
1162 }; 1260 };
1163 }; 1261 };
1164 1262
1165 omap_dwc3_2@488c0000 { 1263 omap_dwc3_2: omap_dwc3_2@488c0000 {
1166 compatible = "ti,dwc3"; 1264 compatible = "ti,dwc3";
1167 ti,hwmods = "usb_otg_ss2"; 1265 ti,hwmods = "usb_otg_ss2";
1168 reg = <0x488c0000 0x10000>; 1266 reg = <0x488c0000 0x10000>;
@@ -1184,7 +1282,7 @@
1184 }; 1282 };
1185 1283
1186 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1284 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1187 omap_dwc3_3@48900000 { 1285 omap_dwc3_3: omap_dwc3_3@48900000 {
1188 compatible = "ti,dwc3"; 1286 compatible = "ti,dwc3";
1189 ti,hwmods = "usb_otg_ss3"; 1287 ti,hwmods = "usb_otg_ss3";
1190 reg = <0x48900000 0x10000>; 1288 reg = <0x48900000 0x10000>;
@@ -1204,26 +1302,6 @@
1204 }; 1302 };
1205 }; 1303 };
1206 1304
1207 omap_dwc3_4@48940000 {
1208 compatible = "ti,dwc3";
1209 ti,hwmods = "usb_otg_ss4";
1210 reg = <0x48940000 0x10000>;
1211 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 utmi-mode = <2>;
1215 ranges;
1216 status = "disabled";
1217 usb4: usb@48950000 {
1218 compatible = "snps,dwc3";
1219 reg = <0x48950000 0x17000>;
1220 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1221 tx-fifo-resize;
1222 maximum-speed = "high-speed";
1223 dr_mode = "otg";
1224 };
1225 };
1226
1227 elm: elm@48078000 { 1305 elm: elm@48078000 {
1228 compatible = "ti,am3352-elm"; 1306 compatible = "ti,am3352-elm";
1229 reg = <0x48078000 0xfc0>; /* device IO registers */ 1307 reg = <0x48078000 0xfc0>; /* device IO registers */
@@ -1265,6 +1343,84 @@
1265 ti,irqs-skip = <10 133 139 140>; 1343 ti,irqs-skip = <10 133 139 140>;
1266 ti,irqs-safe-map = <0>; 1344 ti,irqs-safe-map = <0>;
1267 }; 1345 };
1346
1347 mac: ethernet@4a100000 {
1348 compatible = "ti,cpsw";
1349 ti,hwmods = "gmac";
1350 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1351 clock-names = "fck", "cpts";
1352 cpdma_channels = <8>;
1353 ale_entries = <1024>;
1354 bd_ram_size = <0x2000>;
1355 no_bd_ram = <0>;
1356 rx_descs = <64>;
1357 mac_control = <0x20>;
1358 slaves = <2>;
1359 active_slave = <0>;
1360 cpts_clock_mult = <0x80000000>;
1361 cpts_clock_shift = <29>;
1362 reg = <0x48484000 0x1000
1363 0x48485200 0x2E00>;
1364 #address-cells = <1>;
1365 #size-cells = <1>;
1366 /*
1367 * rx_thresh_pend
1368 * rx_pend
1369 * tx_pend
1370 * misc_pend
1371 */
1372 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1376 ranges;
1377 status = "disabled";
1378
1379 davinci_mdio: mdio@48485000 {
1380 compatible = "ti,davinci_mdio";
1381 #address-cells = <1>;
1382 #size-cells = <0>;
1383 ti,hwmods = "davinci_mdio";
1384 bus_freq = <1000000>;
1385 reg = <0x48485000 0x100>;
1386 };
1387
1388 cpsw_emac0: slave@48480200 {
1389 /* Filled in by U-Boot */
1390 mac-address = [ 00 00 00 00 00 00 ];
1391 };
1392
1393 cpsw_emac1: slave@48480300 {
1394 /* Filled in by U-Boot */
1395 mac-address = [ 00 00 00 00 00 00 ];
1396 };
1397
1398 phy_sel: cpsw-phy-sel@4a002554 {
1399 compatible = "ti,dra7xx-cpsw-phy-sel";
1400 reg= <0x4a002554 0x4>;
1401 reg-names = "gmii-sel";
1402 };
1403 };
1404
1405 dcan1: can@481cc000 {
1406 compatible = "ti,dra7-d_can";
1407 ti,hwmods = "dcan1";
1408 reg = <0x4ae3c000 0x2000>;
1409 syscon-raminit = <&dra7_ctrl_core 0x558 0>;
1410 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&dcan1_sys_clk_mux>;
1412 status = "disabled";
1413 };
1414
1415 dcan2: can@481d0000 {
1416 compatible = "ti,dra7-d_can";
1417 ti,hwmods = "dcan2";
1418 reg = <0x48480000 0x2000>;
1419 syscon-raminit = <&dra7_ctrl_core 0x558 1>;
1420 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&sys_clkin1>;
1422 status = "disabled";
1423 };
1268 }; 1424 };
1269}; 1425};
1270 1426
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 41074288adfa..afc74fd4bb5e 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -17,6 +17,13 @@
17 device_type = "memory"; 17 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1024 MB */ 18 reg = <0x80000000 0x40000000>; /* 1024 MB */
19 }; 19 };
20
21 evm_3v3: fixedregulator-evm_3v3 {
22 compatible = "regulator-fixed";
23 regulator-name = "evm_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
20}; 27};
21 28
22&dra7_pmx_core { 29&dra7_pmx_core {
@@ -26,6 +33,94 @@
26 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
27 >; 34 >;
28 }; 35 };
36
37 nand_default: nand_default {
38 pinctrl-single,pins = <
39 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
40 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
41 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
42 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
43 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
44 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
45 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
46 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
47 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
48 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
49 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
50 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
51 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
52 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
53 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
54 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
55 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */
56 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
57 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
58 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
59 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */
60 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */
61 >;
62 };
63
64 usb1_pins: pinmux_usb1_pins {
65 pinctrl-single,pins = <
66 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
67 >;
68 };
69
70 usb2_pins: pinmux_usb2_pins {
71 pinctrl-single,pins = <
72 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
73 >;
74 };
75
76 tps65917_pins_default: tps65917_pins_default {
77 pinctrl-single,pins = <
78 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
79 >;
80 };
81
82 mmc1_pins_default: mmc1_pins_default {
83 pinctrl-single,pins = <
84 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
85 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
86 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
87 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
88 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
89 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
90 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
91 >;
92 };
93
94 mmc2_pins_default: mmc2_pins_default {
95 pinctrl-single,pins = <
96 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
97 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
98 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
99 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
100 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
101 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
102 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
103 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
104 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
105 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
106 >;
107 };
108
109 dcan1_pins_default: dcan1_pins_default {
110 pinctrl-single,pins = <
111 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
112 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
113 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
114 >;
115 };
116
117 dcan1_pins_sleep: dcan1_pins_sleep {
118 pinctrl-single,pins = <
119 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
120 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
121 0x418 (MUX_MODE15) /* wakeup0.off */
122 >;
123 };
29}; 124};
30 125
31&i2c1 { 126&i2c1 {
@@ -38,6 +133,9 @@
38 compatible = "ti,tps65917"; 133 compatible = "ti,tps65917";
39 reg = <0x58>; 134 reg = <0x58>;
40 135
136 pinctrl-names = "default";
137 pinctrl-0 = <&tps65917_pins_default>;
138
41 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 139 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
42 interrupt-parent = <&gic>; 140 interrupt-parent = <&gic>;
43 interrupt-controller; 141 interrupt-controller;
@@ -136,9 +234,230 @@
136 }; 234 };
137 }; 235 };
138 }; 236 };
237
238 tps65917_power_button {
239 compatible = "ti,palmas-pwrbutton";
240 interrupt-parent = <&tps65917>;
241 interrupts = <1 IRQ_TYPE_NONE>;
242 wakeup-source;
243 ti,palmas-long-press-seconds = <6>;
244 };
139 }; 245 };
140}; 246};
141 247
142&uart1 { 248&uart1 {
143 status = "okay"; 249 status = "okay";
144}; 250};
251
252&elm {
253 status = "okay";
254};
255
256&gpmc {
257 status = "okay";
258 pinctrl-names = "default";
259 pinctrl-0 = <&nand_default>;
260 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
261 nand@0,0 {
262 /* To use NAND, DIP switch SW5 must be set like so:
263 * SW5.1 (NAND_SELn) = ON (LOW)
264 * SW5.9 (GPMC_WPN) = OFF (HIGH)
265 */
266 reg = <0 0 4>; /* device IO registers */
267 ti,nand-ecc-opt = "bch8";
268 ti,elm-id = <&elm>;
269 nand-bus-width = <16>;
270 gpmc,device-width = <2>;
271 gpmc,sync-clk-ps = <0>;
272 gpmc,cs-on-ns = <0>;
273 gpmc,cs-rd-off-ns = <80>;
274 gpmc,cs-wr-off-ns = <80>;
275 gpmc,adv-on-ns = <0>;
276 gpmc,adv-rd-off-ns = <60>;
277 gpmc,adv-wr-off-ns = <60>;
278 gpmc,we-on-ns = <10>;
279 gpmc,we-off-ns = <50>;
280 gpmc,oe-on-ns = <4>;
281 gpmc,oe-off-ns = <40>;
282 gpmc,access-ns = <40>;
283 gpmc,wr-access-ns = <80>;
284 gpmc,rd-cycle-ns = <80>;
285 gpmc,wr-cycle-ns = <80>;
286 gpmc,bus-turnaround-ns = <0>;
287 gpmc,cycle2cycle-delay-ns = <0>;
288 gpmc,clk-activation-ns = <0>;
289 gpmc,wait-monitoring-ns = <0>;
290 gpmc,wr-data-mux-bus-ns = <0>;
291 /* MTD partition table */
292 /* All SPL-* partitions are sized to minimal length
293 * which can be independently programmable. For
294 * NAND flash this is equal to size of erase-block */
295 #address-cells = <1>;
296 #size-cells = <1>;
297 partition@0 {
298 label = "NAND.SPL";
299 reg = <0x00000000 0x000020000>;
300 };
301 partition@1 {
302 label = "NAND.SPL.backup1";
303 reg = <0x00020000 0x00020000>;
304 };
305 partition@2 {
306 label = "NAND.SPL.backup2";
307 reg = <0x00040000 0x00020000>;
308 };
309 partition@3 {
310 label = "NAND.SPL.backup3";
311 reg = <0x00060000 0x00020000>;
312 };
313 partition@4 {
314 label = "NAND.u-boot-spl-os";
315 reg = <0x00080000 0x00040000>;
316 };
317 partition@5 {
318 label = "NAND.u-boot";
319 reg = <0x000c0000 0x00100000>;
320 };
321 partition@6 {
322 label = "NAND.u-boot-env";
323 reg = <0x001c0000 0x00020000>;
324 };
325 partition@7 {
326 label = "NAND.u-boot-env.backup1";
327 reg = <0x001e0000 0x00020000>;
328 };
329 partition@8 {
330 label = "NAND.kernel";
331 reg = <0x00200000 0x00800000>;
332 };
333 partition@9 {
334 label = "NAND.file-system";
335 reg = <0x00a00000 0x0f600000>;
336 };
337 };
338};
339
340&usb2_phy1 {
341 phy-supply = <&ldo4_reg>;
342};
343
344&usb2_phy2 {
345 phy-supply = <&ldo4_reg>;
346};
347
348&usb1 {
349 dr_mode = "peripheral";
350 pinctrl-names = "default";
351 pinctrl-0 = <&usb1_pins>;
352};
353
354&usb2 {
355 dr_mode = "host";
356 pinctrl-names = "default";
357 pinctrl-0 = <&usb2_pins>;
358};
359
360&mmc1 {
361 status = "okay";
362 pinctrl-names = "default";
363 pinctrl-0 = <&mmc1_pins_default>;
364
365 vmmc-supply = <&ldo1_reg>;
366 bus-width = <4>;
367 /*
368 * SDCD signal is not being used here - using the fact that GPIO mode
369 * is a viable alternative
370 */
371 cd-gpios = <&gpio6 27 0>;
372};
373
374&mmc2 {
375 /* SW5-3 in ON position */
376 status = "okay";
377 pinctrl-names = "default";
378 pinctrl-0 = <&mmc2_pins_default>;
379
380 vmmc-supply = <&evm_3v3>;
381 bus-width = <8>;
382 ti,non-removable;
383};
384
385&dra7_pmx_core {
386 cpsw_default: cpsw_default {
387 pinctrl-single,pins = <
388 /* Slave 2 */
389 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
390 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
391 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
392 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
393 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
394 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
395 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
396 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
397 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
398 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
399 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
400 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
401 >;
402
403 };
404
405 cpsw_sleep: cpsw_sleep {
406 pinctrl-single,pins = <
407 /* Slave 2 */
408 0x198 (MUX_MODE15)
409 0x19c (MUX_MODE15)
410 0x1a0 (MUX_MODE15)
411 0x1a4 (MUX_MODE15)
412 0x1a8 (MUX_MODE15)
413 0x1ac (MUX_MODE15)
414 0x1b0 (MUX_MODE15)
415 0x1b4 (MUX_MODE15)
416 0x1b8 (MUX_MODE15)
417 0x1bc (MUX_MODE15)
418 0x1c0 (MUX_MODE15)
419 0x1c4 (MUX_MODE15)
420 >;
421 };
422
423 davinci_mdio_default: davinci_mdio_default {
424 pinctrl-single,pins = <
425 /* MDIO */
426 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
427 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
428 >;
429 };
430
431 davinci_mdio_sleep: davinci_mdio_sleep {
432 pinctrl-single,pins = <
433 0x23c (MUX_MODE15)
434 0x240 (MUX_MODE15)
435 >;
436 };
437};
438
439&mac {
440 status = "okay";
441 pinctrl-names = "default", "sleep";
442 pinctrl-0 = <&cpsw_default>;
443 pinctrl-1 = <&cpsw_sleep>;
444};
445
446&cpsw_emac1 {
447 phy_id = <&davinci_mdio>, <3>;
448 phy-mode = "rgmii";
449};
450
451&davinci_mdio {
452 pinctrl-names = "default", "sleep";
453 pinctrl-0 = <&davinci_mdio_default>;
454 pinctrl-1 = <&davinci_mdio_sleep>;
455 active_slave = <1>;
456};
457
458&dcan1 {
459 status = "ok";
460 pinctrl-names = "default", "sleep";
461 pinctrl-0 = <&dcan1_pins_default>;
462 pinctrl-1 = <&dcan1_pins_sleep>;
463};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 3be544c4891f..10173fab1a15 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -44,4 +44,26 @@
44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, 44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; 45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
46 }; 46 };
47
48 ocp {
49 omap_dwc3_4: omap_dwc3_4@48940000 {
50 compatible = "ti,dwc3";
51 ti,hwmods = "usb_otg_ss4";
52 reg = <0x48940000 0x10000>;
53 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 utmi-mode = <2>;
57 ranges;
58 status = "disabled";
59 usb4: usb@48950000 {
60 compatible = "snps,dwc3";
61 reg = <0x48950000 0x17000>;
62 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
63 tx-fifo-resize;
64 maximum-speed = "high-speed";
65 dr_mode = "otg";
66 };
67 };
68 };
47}; 69};
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts
new file mode 100644
index 000000000000..24822aa98057
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-monk.dts
@@ -0,0 +1,579 @@
1/*
2 * Samsung's Exynos3250 based Monk board device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's Monk board which is based on
8 * Samsung Exynos3250 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15/dts-v1/;
16#include "exynos3250.dtsi"
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "Samsung Monk board";
21 compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3";
22
23 aliases {
24 i2c7 = &i2c_max77836;
25 };
26
27 memory {
28 reg = <0x40000000 0x1ff00000>;
29 };
30
31 firmware@0205F000 {
32 compatible = "samsung,secure-firmware";
33 reg = <0x0205F000 0x1000>;
34 };
35
36 gpio_keys {
37 compatible = "gpio-keys";
38
39 power_key {
40 interrupt-parent = <&gpx2>;
41 interrupts = <7 0>;
42 gpios = <&gpx2 7 1>;
43 linux,code = <KEY_POWER>;
44 label = "power key";
45 debounce-interval = <10>;
46 gpio-key,wakeup;
47 };
48 };
49
50 vemmc_reg: voltage-regulator-0 {
51 compatible = "regulator-fixed";
52 regulator-name = "V_EMMC_2.8V-fixed";
53 regulator-min-microvolt = <2800000>;
54 regulator-max-microvolt = <2800000>;
55 gpio = <&gpk0 2 0>;
56 enable-active-high;
57 };
58
59 i2c_max77836: i2c-gpio-0 {
60 compatible = "i2c-gpio";
61 gpios = <&gpd0 2 0>, <&gpd0 3 0>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64
65 max77836: subpmic@25 {
66 compatible = "maxim,max77836";
67 interrupt-parent = <&gpx1>;
68 interrupts = <5 0>;
69 reg = <0x25>;
70 wakeup;
71
72 muic: max77836-muic {
73 compatible = "maxim,max77836-muic";
74 };
75
76 regulators {
77 compatible = "maxim,max77836-regulator";
78 safeout_reg: SAFEOUT {
79 regulator-name = "SAFEOUT";
80 };
81
82 charger_reg: CHARGER {
83 regulator-name = "CHARGER";
84 regulator-min-microamp = <45000>;
85 regulator-max-microamp = <475000>;
86 regulator-boot-on;
87 };
88
89 motor_reg: LDO1 {
90 regulator-name = "MOT_2.7V";
91 regulator-min-microvolt = <1100000>;
92 regulator-max-microvolt = <2700000>;
93 };
94
95 LDO2 {
96 regulator-name = "UNUSED_LDO2";
97 regulator-min-microvolt = <800000>;
98 regulator-max-microvolt = <3950000>;
99 };
100 };
101
102 charger {
103 compatible = "maxim,max77836-charger";
104
105 maxim,constant-uvolt = <4350000>;
106 maxim,fast-charge-uamp = <225000>;
107 maxim,eoc-uamp = <7500>;
108 maxim,ovp-uvolt = <6500000>;
109 };
110 };
111 };
112};
113
114&adc {
115 vdd-supply = <&ldo3_reg>;
116 status = "okay";
117 assigned-clocks = <&cmu CLK_SCLK_TSADC>;
118 assigned-clock-rates = <6000000>;
119
120 thermistor-ap {
121 compatible = "ntc,ncp15wb473";
122 pullup-uv = <1800000>;
123 pullup-ohm = <100000>;
124 pulldown-ohm = <100000>;
125 io-channels = <&adc 0>;
126 };
127
128 thermistor-battery {
129 compatible = "ntc,ncp15wb473";
130 pullup-uv = <1800000>;
131 pullup-ohm = <100000>;
132 pulldown-ohm = <100000>;
133 io-channels = <&adc 1>;
134 };
135};
136
137&i2c_0 {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 samsung,i2c-sda-delay = <100>;
141 samsung,i2c-slave-addr = <0x10>;
142 samsung,i2c-max-bus-freq = <100000>;
143 status = "okay";
144
145 s2mps14_pmic@66 {
146 compatible = "samsung,s2mps14-pmic";
147 interrupt-parent = <&gpx0>;
148 interrupts = <7 0>;
149 reg = <0x66>;
150 wakeup;
151
152 s2mps14_osc: clocks {
153 compatible = "samsung,s2mps14-clk";
154 #clock-cells = <1>;
155 clock-output-names = "s2mps14_ap", "unused",
156 "s2mps14_bt";
157 };
158
159 regulators {
160 ldo1_reg: LDO1 {
161 regulator-name = "VAP_ALIVE_1.0V";
162 regulator-min-microvolt = <1000000>;
163 regulator-max-microvolt = <1000000>;
164 regulator-always-on;
165 };
166
167 ldo2_reg: LDO2 {
168 regulator-name = "VAP_M1_1.2V";
169 regulator-min-microvolt = <1200000>;
170 regulator-max-microvolt = <1200000>;
171 regulator-always-on;
172 };
173
174 ldo3_reg: LDO3 {
175 regulator-name = "VCC_AP_1.8V";
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <1800000>;
178 regulator-always-on;
179 };
180
181 ldo4_reg: LDO4 {
182 regulator-name = "VAP_AVDD_PLL1";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 regulator-always-on;
186 };
187
188 ldo5_reg: LDO5 {
189 regulator-name = "VAP_PLL_ISO_1.0V";
190 regulator-min-microvolt = <1000000>;
191 regulator-max-microvolt = <1000000>;
192 regulator-always-on;
193 };
194
195 ldo6_reg: LDO6 {
196 regulator-name = "VAP_MIPI_1.0V";
197 regulator-min-microvolt = <1000000>;
198 regulator-max-microvolt = <1000000>;
199 };
200
201 ldo7_reg: LDO7 {
202 regulator-name = "VAP_AVDD_1.8V";
203 regulator-min-microvolt = <1800000>;
204 regulator-max-microvolt = <1800000>;
205 regulator-always-on;
206 };
207
208 ldo8_reg: LDO8 {
209 regulator-name = "VAP_USB_3.0V";
210 regulator-min-microvolt = <3000000>;
211 regulator-max-microvolt = <3000000>;
212 regulator-always-on;
213 };
214
215 ldo9_reg: LDO9 {
216 regulator-name = "V_LPDDR_1.2V";
217 regulator-min-microvolt = <1200000>;
218 regulator-max-microvolt = <1200000>;
219 regulator-always-on;
220 };
221
222 ldo10_reg: LDO10 {
223 regulator-name = "UNUSED_LDO10";
224 regulator-min-microvolt = <1000000>;
225 regulator-max-microvolt = <1000000>;
226 };
227
228 ldo11_reg: LDO11 {
229 regulator-name = "V_EMMC_1.8V";
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <1800000>;
232 samsung,ext-control-gpios = <&gpk0 2 0>;
233 };
234
235 ldo12_reg: LDO12 {
236 regulator-name = "V_EMMC_2.8V";
237 regulator-min-microvolt = <2800000>;
238 regulator-max-microvolt = <2800000>;
239 samsung,ext-control-gpios = <&gpk0 2 0>;
240 };
241
242 ldo13_reg: LDO13 {
243 regulator-name = "VSENSOR_2.85V";
244 regulator-min-microvolt = <2850000>;
245 regulator-max-microvolt = <2850000>;
246 regulator-always-on;
247 };
248
249 ldo14_reg: LDO14 {
250 regulator-name = "UNUSED_LDO14";
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 };
254
255 ldo15_reg: LDO15 {
256 regulator-name = "TSP_AVDD_3.3V";
257 regulator-min-microvolt = <3300000>;
258 regulator-max-microvolt = <3300000>;
259 };
260
261 ldo16_reg: LDO16 {
262 regulator-name = "LCD_VDD_3.3V";
263 regulator-min-microvolt = <3300000>;
264 regulator-max-microvolt = <3300000>;
265 };
266
267 ldo17_reg: LDO17 {
268 regulator-name = "UNUSED_LDO17";
269 regulator-min-microvolt = <1800000>;
270 regulator-max-microvolt = <1800000>;
271 };
272
273 ldo18_reg: LDO18 {
274 regulator-name = "UNUSED_LDO18";
275 regulator-min-microvolt = <1800000>;
276 regulator-max-microvolt = <1800000>;
277 };
278
279 ldo19_reg: LDO19 {
280 regulator-name = "TSP_VDD_1.8V";
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <1800000>;
283 };
284
285 ldo20_reg: LDO20 {
286 regulator-name = "LCD_VDD_1.8V";
287 regulator-min-microvolt = <1800000>;
288 regulator-max-microvolt = <1800000>;
289 };
290
291 ldo21_reg: LDO21 {
292 regulator-name = "UNUSED_LDO21";
293 regulator-min-microvolt = <1000000>;
294 regulator-max-microvolt = <1000000>;
295 };
296
297 ldo22_reg: LDO22 {
298 regulator-name = "UNUSED_LDO22";
299 regulator-min-microvolt = <1000000>;
300 regulator-max-microvolt = <1000000>;
301 };
302
303 ldo23_reg: LDO23 {
304 regulator-name = "UNUSED_LDO23";
305 regulator-min-microvolt = <1000000>;
306 regulator-max-microvolt = <1000000>;
307 regulator-always-on;
308 };
309
310 ldo24_reg: LDO24 {
311 regulator-name = "UNUSED_LDO24";
312 regulator-min-microvolt = <1800000>;
313 regulator-max-microvolt = <1800000>;
314 };
315
316 ldo25_reg: LDO25 {
317 regulator-name = "UNUSED_LDO25";
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <1800000>;
320 };
321
322 buck1_reg: BUCK1 {
323 regulator-name = "VAP_MIF_1.0V";
324 regulator-min-microvolt = <800000>;
325 regulator-max-microvolt = <900000>;
326 regulator-always-on;
327 };
328
329 buck2_reg: BUCK2 {
330 regulator-name = "VAP_ARM_1.0V";
331 regulator-min-microvolt = <850000>;
332 regulator-max-microvolt = <1150000>;
333 regulator-always-on;
334 };
335
336 buck3_reg: BUCK3 {
337 regulator-name = "VAP_INT3D_1.0V";
338 regulator-min-microvolt = <850000>;
339 regulator-max-microvolt = <1000000>;
340 regulator-always-on;
341 };
342
343 buck4_reg: BUCK4 {
344 regulator-name = "VCC_SUB_1.95V";
345 regulator-min-microvolt = <1950000>;
346 regulator-max-microvolt = <1950000>;
347 regulator-always-on;
348 };
349
350 buck5_reg: BUCK5 {
351 regulator-name = "VCC_SUB_1.35V";
352 regulator-min-microvolt = <1350000>;
353 regulator-max-microvolt = <1350000>;
354 regulator-always-on;
355 };
356 };
357 };
358};
359
360&i2c_1 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 samsung,i2c-sda-delay = <100>;
364 samsung,i2c-slave-addr = <0x10>;
365 samsung,i2c-max-bus-freq = <400000>;
366 status = "okay";
367
368 fuelgauge@36 {
369 compatible = "maxim,max77836-battery";
370 interrupt-parent = <&gpx1>;
371 interrupts = <2 8>;
372 reg = <0x36>;
373 };
374};
375
376&i2s2 {
377 status = "okay";
378};
379
380&mshc_0 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 num-slots = <1>;
384 broken-cd;
385 non-removable;
386 cap-mmc-highspeed;
387 desc-num = <4>;
388 mmc-hs200-1_8v;
389 card-detect-delay = <200>;
390 vmmc-supply = <&vemmc_reg>;
391 clock-frequency = <100000000>;
392 clock-freq-min-max = <400000 100000000>;
393 samsung,dw-mshc-ciu-div = <1>;
394 samsung,dw-mshc-sdr-timing = <0 1>;
395 samsung,dw-mshc-ddr-timing = <1 2>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
398 bus-width = <8>;
399 status = "okay";
400};
401
402&serial_0 {
403 assigned-clocks = <&cmu CLK_SCLK_UART0>;
404 assigned-clock-rates = <100000000>;
405 status = "okay";
406};
407
408&serial_1 {
409 status = "okay";
410};
411
412&tmu {
413 vtmu-supply = <&ldo7_reg>;
414 status = "okay";
415};
416
417&rtc {
418 clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
419 clock-names = "rtc", "rtc_src";
420 status = "okay";
421};
422
423&xusbxti {
424 clock-frequency = <24000000>;
425};
426
427&pinctrl_0 {
428 pinctrl-names = "default";
429 pinctrl-0 = <&sleep0>;
430
431 sleep0: sleep-state {
432 PIN_SLP(gpa0-0, INPUT, DOWN);
433 PIN_SLP(gpa0-1, INPUT, DOWN);
434 PIN_SLP(gpa0-2, INPUT, DOWN);
435 PIN_SLP(gpa0-3, INPUT, DOWN);
436 PIN_SLP(gpa0-4, INPUT, DOWN);
437 PIN_SLP(gpa0-5, INPUT, DOWN);
438 PIN_SLP(gpa0-6, INPUT, DOWN);
439 PIN_SLP(gpa0-7, INPUT, DOWN);
440
441 PIN_SLP(gpa1-0, INPUT, DOWN);
442 PIN_SLP(gpa1-1, INPUT, DOWN);
443 PIN_SLP(gpa1-2, INPUT, DOWN);
444 PIN_SLP(gpa1-3, INPUT, DOWN);
445 PIN_SLP(gpa1-4, INPUT, DOWN);
446 PIN_SLP(gpa1-5, INPUT, DOWN);
447
448 PIN_SLP(gpb-0, PREV, NONE);
449 PIN_SLP(gpb-1, PREV, NONE);
450 PIN_SLP(gpb-2, PREV, NONE);
451 PIN_SLP(gpb-3, PREV, NONE);
452 PIN_SLP(gpb-4, INPUT, DOWN);
453 PIN_SLP(gpb-5, INPUT, DOWN);
454 PIN_SLP(gpb-6, INPUT, DOWN);
455 PIN_SLP(gpb-7, INPUT, DOWN);
456
457 PIN_SLP(gpc0-0, INPUT, DOWN);
458 PIN_SLP(gpc0-1, INPUT, DOWN);
459 PIN_SLP(gpc0-2, INPUT, DOWN);
460 PIN_SLP(gpc0-3, INPUT, DOWN);
461 PIN_SLP(gpc0-4, INPUT, DOWN);
462
463 PIN_SLP(gpc1-0, INPUT, DOWN);
464 PIN_SLP(gpc1-1, INPUT, DOWN);
465 PIN_SLP(gpc1-2, INPUT, DOWN);
466 PIN_SLP(gpc1-3, INPUT, DOWN);
467 PIN_SLP(gpc1-4, INPUT, DOWN);
468
469 PIN_SLP(gpd0-0, INPUT, DOWN);
470 PIN_SLP(gpd0-1, INPUT, DOWN);
471 PIN_SLP(gpd0-2, INPUT, NONE);
472 PIN_SLP(gpd0-3, INPUT, NONE);
473
474 PIN_SLP(gpd1-0, INPUT, NONE);
475 PIN_SLP(gpd1-1, INPUT, NONE);
476 PIN_SLP(gpd1-2, INPUT, NONE);
477 PIN_SLP(gpd1-3, INPUT, NONE);
478 };
479};
480
481&pinctrl_1 {
482 pinctrl-names = "default";
483 pinctrl-0 = <&sleep1>;
484
485 sleep1: sleep-state {
486 PIN_SLP(gpe0-0, PREV, NONE);
487 PIN_SLP(gpe0-1, PREV, NONE);
488 PIN_SLP(gpe0-2, INPUT, DOWN);
489 PIN_SLP(gpe0-3, INPUT, DOWN);
490 PIN_SLP(gpe0-4, PREV, NONE);
491 PIN_SLP(gpe0-5, INPUT, DOWN);
492 PIN_SLP(gpe0-6, INPUT, DOWN);
493 PIN_SLP(gpe0-7, INPUT, DOWN);
494
495 PIN_SLP(gpe1-0, INPUT, DOWN);
496 PIN_SLP(gpe1-1, PREV, NONE);
497 PIN_SLP(gpe1-2, INPUT, DOWN);
498 PIN_SLP(gpe1-3, INPUT, DOWN);
499 PIN_SLP(gpe1-4, INPUT, DOWN);
500 PIN_SLP(gpe1-5, INPUT, DOWN);
501 PIN_SLP(gpe1-6, INPUT, DOWN);
502 PIN_SLP(gpe1-7, INPUT, NONE);
503
504 PIN_SLP(gpe2-0, INPUT, NONE);
505 PIN_SLP(gpe2-1, INPUT, NONE);
506 PIN_SLP(gpe2-2, INPUT, NONE);
507
508 PIN_SLP(gpk0-0, INPUT, DOWN);
509 PIN_SLP(gpk0-1, INPUT, DOWN);
510 PIN_SLP(gpk0-2, OUT0, NONE);
511 PIN_SLP(gpk0-3, INPUT, DOWN);
512 PIN_SLP(gpk0-4, INPUT, DOWN);
513 PIN_SLP(gpk0-5, INPUT, DOWN);
514 PIN_SLP(gpk0-6, INPUT, DOWN);
515 PIN_SLP(gpk0-7, INPUT, DOWN);
516
517 PIN_SLP(gpk1-0, PREV, NONE);
518 PIN_SLP(gpk1-1, PREV, NONE);
519 PIN_SLP(gpk1-2, INPUT, DOWN);
520 PIN_SLP(gpk1-3, PREV, NONE);
521 PIN_SLP(gpk1-4, PREV, NONE);
522 PIN_SLP(gpk1-5, PREV, NONE);
523 PIN_SLP(gpk1-6, PREV, NONE);
524
525 PIN_SLP(gpk2-0, INPUT, DOWN);
526 PIN_SLP(gpk2-1, INPUT, DOWN);
527 PIN_SLP(gpk2-2, INPUT, DOWN);
528 PIN_SLP(gpk2-3, INPUT, DOWN);
529 PIN_SLP(gpk2-4, INPUT, DOWN);
530 PIN_SLP(gpk2-5, INPUT, DOWN);
531 PIN_SLP(gpk2-6, INPUT, DOWN);
532
533 PIN_SLP(gpl0-0, INPUT, DOWN);
534 PIN_SLP(gpl0-1, INPUT, DOWN);
535 PIN_SLP(gpl0-2, INPUT, DOWN);
536 PIN_SLP(gpl0-3, INPUT, DOWN);
537
538 PIN_SLP(gpm0-0, INPUT, DOWN);
539 PIN_SLP(gpm0-1, INPUT, DOWN);
540 PIN_SLP(gpm0-2, INPUT, DOWN);
541 PIN_SLP(gpm0-3, INPUT, DOWN);
542 PIN_SLP(gpm0-4, INPUT, DOWN);
543 PIN_SLP(gpm0-5, INPUT, DOWN);
544 PIN_SLP(gpm0-6, INPUT, DOWN);
545 PIN_SLP(gpm0-7, INPUT, DOWN);
546
547 PIN_SLP(gpm1-0, INPUT, DOWN);
548 PIN_SLP(gpm1-1, INPUT, DOWN);
549 PIN_SLP(gpm1-2, INPUT, DOWN);
550 PIN_SLP(gpm1-3, INPUT, DOWN);
551 PIN_SLP(gpm1-4, INPUT, DOWN);
552 PIN_SLP(gpm1-5, INPUT, DOWN);
553 PIN_SLP(gpm1-6, INPUT, DOWN);
554
555 PIN_SLP(gpm2-0, INPUT, DOWN);
556 PIN_SLP(gpm2-1, INPUT, DOWN);
557 PIN_SLP(gpm2-2, INPUT, DOWN);
558 PIN_SLP(gpm2-3, INPUT, DOWN);
559 PIN_SLP(gpm2-4, INPUT, DOWN);
560
561 PIN_SLP(gpm3-0, INPUT, DOWN);
562 PIN_SLP(gpm3-1, INPUT, DOWN);
563 PIN_SLP(gpm3-2, INPUT, DOWN);
564 PIN_SLP(gpm3-3, INPUT, DOWN);
565 PIN_SLP(gpm3-4, INPUT, DOWN);
566 PIN_SLP(gpm3-5, INPUT, DOWN);
567 PIN_SLP(gpm3-6, INPUT, DOWN);
568 PIN_SLP(gpm3-7, INPUT, DOWN);
569
570 PIN_SLP(gpm4-0, INPUT, DOWN);
571 PIN_SLP(gpm4-1, INPUT, DOWN);
572 PIN_SLP(gpm4-2, INPUT, DOWN);
573 PIN_SLP(gpm4-3, INPUT, DOWN);
574 PIN_SLP(gpm4-4, INPUT, DOWN);
575 PIN_SLP(gpm4-5, INPUT, DOWN);
576 PIN_SLP(gpm4-6, INPUT, DOWN);
577 PIN_SLP(gpm4-7, INPUT, DOWN);
578 };
579};
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
index 47b92c150f4e..5ab81c39e2c9 100644
--- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -12,6 +12,22 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 3
18
19#define PIN_PDN_OUT0 0
20#define PIN_PDN_OUT1 1
21#define PIN_PDN_INPUT 2
22#define PIN_PDN_PREV 3
23
24#define PIN_SLP(_pin, _mode, _pull) \
25 _pin { \
26 samsung,pins = #_pin; \
27 samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \
28 samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \
29 }
30
15&pinctrl_0 { 31&pinctrl_0 {
16 gpa0: gpa0 { 32 gpa0: gpa0 {
17 gpio-controller; 33 gpio-controller;
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
new file mode 100644
index 000000000000..80aa8b4c4a3d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -0,0 +1,682 @@
1/*
2 * Samsung's Exynos3250 based Rinato board device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's Rinato board which is based on
8 * Samsung Exynos3250 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15/dts-v1/;
16#include "exynos3250.dtsi"
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "Samsung Rinato board";
21 compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3";
22
23 aliases {
24 i2c7 = &i2c_max77836;
25 };
26
27 memory {
28 reg = <0x40000000 0x1ff00000>;
29 };
30
31 firmware@0205F000 {
32 compatible = "samsung,secure-firmware";
33 reg = <0x0205F000 0x1000>;
34 };
35
36 gpio_keys {
37 compatible = "gpio-keys";
38
39 power_key {
40 interrupt-parent = <&gpx2>;
41 interrupts = <7 0>;
42 gpios = <&gpx2 7 1>;
43 linux,code = <KEY_POWER>;
44 label = "power key";
45 debounce-interval = <10>;
46 gpio-key,wakeup;
47 };
48 };
49
50 i2c_max77836: i2c-gpio-0 {
51 compatible = "i2c-gpio";
52 gpios = <&gpd0 2 0>, <&gpd0 3 0>;
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 max77836: subpmic@25 {
57 compatible = "maxim,max77836";
58 interrupt-parent = <&gpx1>;
59 interrupts = <5 0>;
60 reg = <0x25>;
61 wakeup;
62
63 muic: max77836-muic {
64 compatible = "maxim,max77836-muic";
65 };
66
67 regulators {
68 compatible = "maxim,max77836-regulator";
69 safeout_reg: SAFEOUT {
70 regulator-name = "SAFEOUT";
71 };
72
73 charger_reg: CHARGER {
74 regulator-name = "CHARGER";
75 regulator-min-microamp = <45000>;
76 regulator-max-microamp = <475000>;
77 regulator-boot-on;
78 };
79
80 motor_reg: LDO1 {
81 regulator-name = "MOT_2.7V";
82 regulator-min-microvolt = <1100000>;
83 regulator-max-microvolt = <2700000>;
84 };
85
86 LDO2 {
87 regulator-name = "UNUSED_LDO2";
88 regulator-min-microvolt = <800000>;
89 regulator-max-microvolt = <3950000>;
90 };
91 };
92
93 charger {
94 compatible = "maxim,max77836-charger";
95
96 maxim,constant-uvolt = <4350000>;
97 maxim,fast-charge-uamp = <225000>;
98 maxim,eoc-uamp = <7500>;
99 maxim,ovp-uvolt = <6500000>;
100 };
101 };
102 };
103};
104
105&adc {
106 vdd-supply = <&ldo3_reg>;
107 status = "okay";
108 assigned-clocks = <&cmu CLK_SCLK_TSADC>;
109 assigned-clock-rates = <6000000>;
110
111 thermistor-ap {
112 compatible = "ntc,ncp15wb473";
113 pullup-uv = <1800000>;
114 pullup-ohm = <100000>;
115 pulldown-ohm = <100000>;
116 io-channels = <&adc 0>;
117 };
118
119 thermistor-battery {
120 compatible = "ntc,ncp15wb473";
121 pullup-uv = <1800000>;
122 pullup-ohm = <100000>;
123 pulldown-ohm = <100000>;
124 io-channels = <&adc 1>;
125 };
126};
127
128&i2c_0 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 samsung,i2c-sda-delay = <100>;
132 samsung,i2c-slave-addr = <0x10>;
133 samsung,i2c-max-bus-freq = <100000>;
134 status = "okay";
135
136 s2mps14_pmic@66 {
137 compatible = "samsung,s2mps14-pmic";
138 interrupt-parent = <&gpx0>;
139 interrupts = <7 0>;
140 reg = <0x66>;
141 wakeup;
142
143 s2mps14_osc: clocks {
144 compatible = "samsung,s2mps14-clk";
145 #clock-cells = <1>;
146 clock-output-names = "s2mps14_ap", "unused",
147 "s2mps14_bt";
148 };
149
150 regulators {
151 ldo1_reg: LDO1 {
152 regulator-name = "VAP_ALIVE_1.0V";
153 regulator-min-microvolt = <1000000>;
154 regulator-max-microvolt = <1000000>;
155 regulator-always-on;
156
157 regulator-state-mem {
158 regulator-on-in-suspend;
159 };
160 };
161
162 ldo2_reg: LDO2 {
163 regulator-name = "VAP_M1_1.2V";
164 regulator-min-microvolt = <1200000>;
165 regulator-max-microvolt = <1200000>;
166 regulator-always-on;
167
168 regulator-state-mem {
169 regulator-off-in-suspend;
170 };
171 };
172
173 ldo3_reg: LDO3 {
174 regulator-name = "VCC_AP_1.8V";
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>;
177 regulator-always-on;
178
179 regulator-state-mem {
180 regulator-off-in-suspend;
181 };
182 };
183
184 ldo4_reg: LDO4 {
185 regulator-name = "VAP_AVDD_PLL1";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <1800000>;
188 regulator-always-on;
189
190 regulator-state-mem {
191 regulator-off-in-suspend;
192 };
193 };
194
195 ldo5_reg: LDO5 {
196 regulator-name = "VAP_PLL_ISO_1.0V";
197 regulator-min-microvolt = <1000000>;
198 regulator-max-microvolt = <1000000>;
199 regulator-always-on;
200
201 regulator-state-mem {
202 regulator-off-in-suspend;
203 };
204 };
205
206 ldo6_reg: LDO6 {
207 regulator-name = "VAP_VMIPI_1.0V";
208 regulator-min-microvolt = <1000000>;
209 regulator-max-microvolt = <1000000>;
210 regulator-always-on;
211
212 regulator-state-mem {
213 regulator-off-in-suspend;
214 };
215 };
216
217 ldo7_reg: LDO7 {
218 regulator-name = "VAP_AVDD_1.8V";
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <1800000>;
221 regulator-always-on;
222
223 regulator-state-mem {
224 regulator-off-in-suspend;
225 };
226 };
227
228 ldo8_reg: LDO8 {
229 regulator-name = "VAP_USB_3.0V";
230 regulator-min-microvolt = <3000000>;
231 regulator-max-microvolt = <3000000>;
232 regulator-always-on;
233
234 regulator-state-mem {
235 regulator-off-in-suspend;
236 };
237 };
238
239 ldo9_reg: LDO9 {
240 regulator-name = "V_LPDDR_1.2V";
241 regulator-min-microvolt = <1200000>;
242 regulator-max-microvolt = <1200000>;
243 regulator-always-on;
244
245 regulator-state-mem {
246 regulator-on-in-suspend;
247 };
248 };
249
250 ldo10_reg: LDO10 {
251 regulator-name = "UNUSED_LDO10";
252 regulator-min-microvolt = <1000000>;
253 regulator-max-microvolt = <1000000>;
254
255 regulator-state-mem {
256 regulator-off-in-suspend;
257 };
258 };
259
260 ldo11_reg: LDO11 {
261 regulator-name = "V_EMMC_1.8V";
262 regulator-min-microvolt = <1800000>;
263 regulator-max-microvolt = <1800000>;
264 samsung,ext-control-gpios = <&gpk0 2 0>;
265 };
266
267 ldo12_reg: LDO12 {
268 regulator-name = "V_EMMC_2.8V";
269 regulator-min-microvolt = <2800000>;
270 regulator-max-microvolt = <2800000>;
271 samsung,ext-control-gpios = <&gpk0 2 0>;
272 };
273
274 ldo13_reg: LDO13 {
275 regulator-name = "CAM_AVDD_2.8V";
276 regulator-min-microvolt = <2800000>;
277 regulator-max-microvolt = <2800000>;
278
279 regulator-state-mem {
280 regulator-off-in-suspend;
281 };
282 };
283
284 ldo14_reg: LDO14 {
285 regulator-name = "UNUSED_LDO14";
286 regulator-min-microvolt = <2700000>;
287 regulator-max-microvolt = <2700000>;
288
289 regulator-state-mem {
290 regulator-off-in-suspend;
291 };
292 };
293
294 ldo15_reg: LDO15 {
295 regulator-name = "TSP_AVDD_3.3V";
296 regulator-min-microvolt = <3300000>;
297 regulator-max-microvolt = <3300000>;
298
299 regulator-state-mem {
300 regulator-off-in-suspend;
301 };
302 };
303
304 ldo16_reg: LDO16 {
305 regulator-name = "LCD_VDD_3.3V";
306 regulator-min-microvolt = <3300000>;
307 regulator-max-microvolt = <3300000>;
308
309 regulator-state-mem {
310 regulator-off-in-suspend;
311 };
312 };
313
314 ldo17_reg: LDO17 {
315 regulator-name = "V_IRLED_3.3V";
316 regulator-min-microvolt = <3300000>;
317 regulator-max-microvolt = <3300000>;
318
319 regulator-state-mem {
320 regulator-off-in-suspend;
321 };
322 };
323
324 ldo18_reg: LDO18 {
325 regulator-name = "CAM_AF_2.8V";
326 regulator-min-microvolt = <2800000>;
327 regulator-max-microvolt = <2800000>;
328
329 regulator-state-mem {
330 regulator-off-in-suspend;
331 };
332 };
333
334 ldo19_reg: LDO19 {
335 regulator-name = "TSP_VDD_1.8V";
336 regulator-min-microvolt = <1800000>;
337 regulator-max-microvolt = <1800000>;
338
339 regulator-state-mem {
340 regulator-off-in-suspend;
341 };
342 };
343
344 ldo20_reg: LDO20 {
345 regulator-name = "LCD_VDD_1.8V";
346 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <1800000>;
348
349 regulator-state-mem {
350 regulator-off-in-suspend;
351 };
352 };
353
354 ldo21_reg: LDO21 {
355 regulator-name = "CAM_IO_1.8V";
356 regulator-min-microvolt = <1800000>;
357 regulator-max-microvolt = <1800000>;
358
359 regulator-state-mem {
360 regulator-off-in-suspend;
361 };
362 };
363
364 ldo22_reg: LDO22 {
365 regulator-name = "CAM_DVDD_1.2V";
366 regulator-min-microvolt = <1200000>;
367 regulator-max-microvolt = <1200000>;
368
369 regulator-state-mem {
370 regulator-off-in-suspend;
371 };
372 };
373
374 ldo23_reg: LDO23 {
375 regulator-name = "HRM_VCC_1.8V";
376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <1800000>;
378 regulator-always-on;
379 };
380
381 ldo24_reg: LDO24 {
382 regulator-name = "HRM_VCC_3.3V";
383 regulator-min-microvolt = <3000000>;
384 regulator-max-microvolt = <3000000>;
385
386 regulator-state-mem {
387 regulator-off-in-suspend;
388 };
389 };
390
391 ldo25_reg: LDO25 {
392 regulator-name = "UNUSED_LDO25";
393 regulator-min-microvolt = <3000000>;
394 regulator-max-microvolt = <3000000>;
395
396 regulator-state-mem {
397 regulator-off-in-suspend;
398 };
399 };
400
401 buck1_reg: BUCK1 {
402 regulator-name = "VAP_MIF_1.0V";
403 regulator-min-microvolt = <800000>;
404 regulator-max-microvolt = <900000>;
405 regulator-always-on;
406
407 regulator-state-mem {
408 regulator-off-in-suspend;
409 };
410 };
411
412 buck2_reg: BUCK2 {
413 regulator-name = "VAP_ARM_1.0V";
414 regulator-min-microvolt = <850000>;
415 regulator-max-microvolt = <1150000>;
416 regulator-always-on;
417
418 regulator-state-mem {
419 regulator-off-in-suspend;
420 };
421 };
422
423 buck3_reg: BUCK3 {
424 regulator-name = "VAP_INT3D_1.0V";
425 regulator-min-microvolt = <850000>;
426 regulator-max-microvolt = <1000000>;
427 regulator-always-on;
428
429 regulator-state-mem {
430 regulator-off-in-suspend;
431 };
432 };
433
434 buck4_reg: BUCK4 {
435 regulator-name = "VCC_SUB_1.95V";
436 regulator-min-microvolt = <1950000>;
437 regulator-max-microvolt = <1950000>;
438 regulator-always-on;
439
440 regulator-state-mem {
441 regulator-on-in-suspend;
442 };
443 };
444
445 buck5_reg: BUCK5 {
446 regulator-name = "VCC_SUB_1.35V";
447 regulator-min-microvolt = <1350000>;
448 regulator-max-microvolt = <1350000>;
449 regulator-always-on;
450
451 regulator-state-mem {
452 regulator-on-in-suspend;
453 };
454 };
455 };
456 };
457};
458
459&i2c_1 {
460 #address-cells = <1>;
461 #size-cells = <0>;
462 samsung,i2c-sda-delay = <100>;
463 samsung,i2c-slave-addr = <0x10>;
464 samsung,i2c-max-bus-freq = <400000>;
465 status = "okay";
466
467 fuelgauge@36 {
468 compatible = "maxim,max77836-battery";
469 interrupt-parent = <&gpx1>;
470 interrupts = <2 8>;
471 reg = <0x36>;
472 };
473};
474
475&i2s2 {
476 status = "okay";
477};
478
479&mfc {
480 status = "okay";
481};
482
483&mshc_0 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 num-slots = <1>;
487 broken-cd;
488 non-removable;
489 cap-mmc-highspeed;
490 desc-num = <4>;
491 mmc-hs200-1_8v;
492 card-detect-delay = <200>;
493 vmmc-supply = <&ldo12_reg>;
494 clock-frequency = <100000000>;
495 clock-freq-min-max = <400000 100000000>;
496 samsung,dw-mshc-ciu-div = <1>;
497 samsung,dw-mshc-sdr-timing = <0 1>;
498 samsung,dw-mshc-ddr-timing = <1 2>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
501 bus-width = <8>;
502 status = "okay";
503};
504
505&serial_0 {
506 assigned-clocks = <&cmu CLK_SCLK_UART0>;
507 assigned-clock-rates = <100000000>;
508 status = "okay";
509};
510
511&serial_1 {
512 status = "okay";
513};
514
515&tmu {
516 vtmu-supply = <&ldo7_reg>;
517 status = "okay";
518};
519
520&rtc {
521 clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>;
522 clock-names = "rtc", "rtc_src";
523 status = "okay";
524};
525
526&xusbxti {
527 clock-frequency = <24000000>;
528};
529
530&pinctrl_0 {
531 pinctrl-names = "default";
532 pinctrl-0 = <&sleep0>;
533
534 sleep0: sleep-state {
535 PIN_SLP(gpa0-0, INPUT, DOWN);
536 PIN_SLP(gpa0-1, INPUT, DOWN);
537 PIN_SLP(gpa0-2, INPUT, DOWN);
538 PIN_SLP(gpa0-3, INPUT, DOWN);
539 PIN_SLP(gpa0-4, INPUT, DOWN);
540 PIN_SLP(gpa0-5, INPUT, DOWN);
541 PIN_SLP(gpa0-6, INPUT, DOWN);
542 PIN_SLP(gpa0-7, INPUT, DOWN);
543
544 PIN_SLP(gpa1-0, INPUT, DOWN);
545 PIN_SLP(gpa1-1, INPUT, DOWN);
546 PIN_SLP(gpa1-2, INPUT, DOWN);
547 PIN_SLP(gpa1-3, INPUT, DOWN);
548 PIN_SLP(gpa1-4, INPUT, DOWN);
549 PIN_SLP(gpa1-5, INPUT, DOWN);
550
551 PIN_SLP(gpb-0, PREV, NONE);
552 PIN_SLP(gpb-1, PREV, NONE);
553 PIN_SLP(gpb-2, PREV, NONE);
554 PIN_SLP(gpb-3, PREV, NONE);
555 PIN_SLP(gpb-4, INPUT, DOWN);
556 PIN_SLP(gpb-5, INPUT, DOWN);
557 PIN_SLP(gpb-6, INPUT, DOWN);
558 PIN_SLP(gpb-7, INPUT, DOWN);
559
560 PIN_SLP(gpc0-0, INPUT, DOWN);
561 PIN_SLP(gpc0-1, INPUT, DOWN);
562 PIN_SLP(gpc0-2, INPUT, DOWN);
563 PIN_SLP(gpc0-3, INPUT, DOWN);
564 PIN_SLP(gpc0-4, INPUT, DOWN);
565
566 PIN_SLP(gpc1-0, INPUT, DOWN);
567 PIN_SLP(gpc1-1, INPUT, DOWN);
568 PIN_SLP(gpc1-2, INPUT, DOWN);
569 PIN_SLP(gpc1-3, INPUT, DOWN);
570 PIN_SLP(gpc1-4, INPUT, DOWN);
571
572 PIN_SLP(gpd0-0, INPUT, DOWN);
573 PIN_SLP(gpd0-1, INPUT, DOWN);
574 PIN_SLP(gpd0-2, INPUT, NONE);
575 PIN_SLP(gpd0-3, INPUT, NONE);
576
577 PIN_SLP(gpd1-0, INPUT, NONE);
578 PIN_SLP(gpd1-1, INPUT, NONE);
579 PIN_SLP(gpd1-2, INPUT, NONE);
580 PIN_SLP(gpd1-3, INPUT, NONE);
581 };
582};
583
584&pinctrl_1 {
585 pinctrl-names = "default";
586 pinctrl-0 = <&sleep1>;
587
588 sleep1: sleep-state {
589 PIN_SLP(gpe0-0, PREV, NONE);
590 PIN_SLP(gpe0-1, PREV, NONE);
591 PIN_SLP(gpe0-2, INPUT, DOWN);
592 PIN_SLP(gpe0-3, INPUT, UP);
593 PIN_SLP(gpe0-4, INPUT, DOWN);
594 PIN_SLP(gpe0-5, INPUT, DOWN);
595 PIN_SLP(gpe0-6, INPUT, DOWN);
596 PIN_SLP(gpe0-7, INPUT, DOWN);
597
598 PIN_SLP(gpe1-0, INPUT, DOWN);
599 PIN_SLP(gpe1-1, PREV, NONE);
600 PIN_SLP(gpe1-2, INPUT, DOWN);
601 PIN_SLP(gpe1-3, INPUT, DOWN);
602 PIN_SLP(gpe1-4, INPUT, DOWN);
603 PIN_SLP(gpe1-5, INPUT, DOWN);
604 PIN_SLP(gpe1-6, INPUT, DOWN);
605 PIN_SLP(gpe1-7, INPUT, NONE);
606
607 PIN_SLP(gpe2-0, INPUT, NONE);
608 PIN_SLP(gpe2-1, INPUT, NONE);
609 PIN_SLP(gpe2-2, INPUT, NONE);
610
611 PIN_SLP(gpk0-0, INPUT, DOWN);
612 PIN_SLP(gpk0-1, INPUT, DOWN);
613 PIN_SLP(gpk0-2, OUT0, NONE);
614 PIN_SLP(gpk0-3, INPUT, DOWN);
615 PIN_SLP(gpk0-4, INPUT, DOWN);
616 PIN_SLP(gpk0-5, INPUT, DOWN);
617 PIN_SLP(gpk0-6, INPUT, DOWN);
618 PIN_SLP(gpk0-7, INPUT, DOWN);
619
620 PIN_SLP(gpk1-0, INPUT, DOWN);
621 PIN_SLP(gpk1-1, INPUT, DOWN);
622 PIN_SLP(gpk1-2, INPUT, DOWN);
623 PIN_SLP(gpk1-3, INPUT, DOWN);
624 PIN_SLP(gpk1-4, INPUT, DOWN);
625 PIN_SLP(gpk1-5, INPUT, DOWN);
626 PIN_SLP(gpk1-6, INPUT, DOWN);
627
628 PIN_SLP(gpk2-0, INPUT, DOWN);
629 PIN_SLP(gpk2-1, INPUT, DOWN);
630 PIN_SLP(gpk2-2, INPUT, DOWN);
631 PIN_SLP(gpk2-3, INPUT, DOWN);
632 PIN_SLP(gpk2-4, INPUT, DOWN);
633 PIN_SLP(gpk2-5, INPUT, DOWN);
634 PIN_SLP(gpk2-6, INPUT, DOWN);
635
636 PIN_SLP(gpl0-0, INPUT, DOWN);
637 PIN_SLP(gpl0-1, INPUT, DOWN);
638 PIN_SLP(gpl0-2, INPUT, DOWN);
639 PIN_SLP(gpl0-3, INPUT, DOWN);
640
641 PIN_SLP(gpm0-0, INPUT, DOWN);
642 PIN_SLP(gpm0-1, INPUT, DOWN);
643 PIN_SLP(gpm0-2, INPUT, DOWN);
644 PIN_SLP(gpm0-3, INPUT, DOWN);
645 PIN_SLP(gpm0-4, INPUT, DOWN);
646 PIN_SLP(gpm0-5, INPUT, DOWN);
647 PIN_SLP(gpm0-6, INPUT, DOWN);
648 PIN_SLP(gpm0-7, INPUT, DOWN);
649
650 PIN_SLP(gpm1-0, INPUT, DOWN);
651 PIN_SLP(gpm1-1, INPUT, DOWN);
652 PIN_SLP(gpm1-2, INPUT, DOWN);
653 PIN_SLP(gpm1-3, INPUT, DOWN);
654 PIN_SLP(gpm1-4, INPUT, DOWN);
655 PIN_SLP(gpm1-5, INPUT, DOWN);
656 PIN_SLP(gpm1-6, INPUT, DOWN);
657
658 PIN_SLP(gpm2-0, INPUT, DOWN);
659 PIN_SLP(gpm2-1, INPUT, DOWN);
660 PIN_SLP(gpm2-2, INPUT, DOWN);
661 PIN_SLP(gpm2-3, INPUT, DOWN);
662 PIN_SLP(gpm2-4, INPUT, DOWN);
663
664 PIN_SLP(gpm3-0, INPUT, DOWN);
665 PIN_SLP(gpm3-1, INPUT, DOWN);
666 PIN_SLP(gpm3-2, INPUT, DOWN);
667 PIN_SLP(gpm3-3, INPUT, DOWN);
668 PIN_SLP(gpm3-4, INPUT, DOWN);
669 PIN_SLP(gpm3-5, INPUT, DOWN);
670 PIN_SLP(gpm3-6, INPUT, DOWN);
671 PIN_SLP(gpm3-7, INPUT, DOWN);
672
673 PIN_SLP(gpm4-0, INPUT, DOWN);
674 PIN_SLP(gpm4-1, INPUT, DOWN);
675 PIN_SLP(gpm4-2, INPUT, DOWN);
676 PIN_SLP(gpm4-3, INPUT, DOWN);
677 PIN_SLP(gpm4-4, INPUT, DOWN);
678 PIN_SLP(gpm4-5, INPUT, DOWN);
679 PIN_SLP(gpm4-6, INPUT, DOWN);
680 PIN_SLP(gpm4-7, INPUT, DOWN);
681 };
682};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 693a3275606f..242ddda0a8cd 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -320,6 +320,16 @@
320 status = "disabled"; 320 status = "disabled";
321 }; 321 };
322 322
323 mfc: codec@13400000 {
324 compatible = "samsung,mfc-v7";
325 reg = <0x13400000 0x10000>;
326 interrupts = <0 102 0>;
327 clock-names = "mfc", "sclk_mfc";
328 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
329 samsung,power-domain = <&pd_mfc>;
330 status = "disabled";
331 };
332
323 serial_0: serial@13800000 { 333 serial_0: serial@13800000 {
324 compatible = "samsung,exynos4210-uart"; 334 compatible = "samsung,exynos4210-uart";
325 reg = <0x13800000 0x100>; 335 reg = <0x13800000 0x100>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index e0278ecbc816..b8168f1f8139 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -392,8 +392,8 @@
392 reg = <0x13400000 0x10000>; 392 reg = <0x13400000 0x10000>;
393 interrupts = <0 94 0>; 393 interrupts = <0 94 0>;
394 samsung,power-domain = <&pd_mfc>; 394 samsung,power-domain = <&pd_mfc>;
395 clocks = <&clock CLK_MFC>; 395 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
396 clock-names = "mfc"; 396 clock-names = "mfc", "sclk_mfc";
397 status = "disabled"; 397 status = "disabled";
398 }; 398 };
399 399
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9e8b3a..720836205546 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -431,18 +431,34 @@
431 431
432 fimc_0: fimc@11800000 { 432 fimc_0: fimc@11800000 {
433 status = "okay"; 433 status = "okay";
434 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
435 <&clock CLK_SCLK_FIMC0>;
436 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
437 assigned-clock-rates = <0>, <160000000>;
434 }; 438 };
435 439
436 fimc_1: fimc@11810000 { 440 fimc_1: fimc@11810000 {
437 status = "okay"; 441 status = "okay";
442 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
443 <&clock CLK_SCLK_FIMC1>;
444 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
445 assigned-clock-rates = <0>, <160000000>;
438 }; 446 };
439 447
440 fimc_2: fimc@11820000 { 448 fimc_2: fimc@11820000 {
441 status = "okay"; 449 status = "okay";
450 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
451 <&clock CLK_SCLK_FIMC2>;
452 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
453 assigned-clock-rates = <0>, <160000000>;
442 }; 454 };
443 455
444 fimc_3: fimc@11830000 { 456 fimc_3: fimc@11830000 {
445 status = "okay"; 457 status = "okay";
458 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
459 <&clock CLK_SCLK_FIMC3>;
460 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
461 assigned-clock-rates = <0>, <160000000>;
446 }; 462 };
447 }; 463 };
448}; 464};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3aa708e..aaf0cae4f5e8 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -473,18 +473,34 @@
473 473
474 fimc_0: fimc@11800000 { 474 fimc_0: fimc@11800000 {
475 status = "okay"; 475 status = "okay";
476 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
477 <&clock CLK_SCLK_FIMC0>;
478 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
479 assigned-clock-rates = <0>, <160000000>;
476 }; 480 };
477 481
478 fimc_1: fimc@11810000 { 482 fimc_1: fimc@11810000 {
479 status = "okay"; 483 status = "okay";
484 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
485 <&clock CLK_SCLK_FIMC1>;
486 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
487 assigned-clock-rates = <0>, <160000000>;
480 }; 488 };
481 489
482 fimc_2: fimc@11820000 { 490 fimc_2: fimc@11820000 {
483 status = "okay"; 491 status = "okay";
492 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
493 <&clock CLK_SCLK_FIMC2>;
494 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
495 assigned-clock-rates = <0>, <160000000>;
484 }; 496 };
485 497
486 fimc_3: fimc@11830000 { 498 fimc_3: fimc@11830000 {
487 status = "okay"; 499 status = "okay";
500 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
501 <&clock CLK_SCLK_FIMC3>;
502 assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
503 assigned-clock-rates = <0>, <160000000>;
488 }; 504 };
489 }; 505 };
490}; 506};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 807bb5bf91fc..bcc9e63c8070 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,23 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@900 {
39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <0x900>;
42 };
43
44 cpu@901 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a9";
47 reg = <0x901>;
48 };
49 };
50
34 pmu_system_controller: system-controller@10020000 { 51 pmu_system_controller: system-controller@10020000 {
35 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 52 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
36 "clkout4", "clkout8", "clkout9"; 53 "clkout4", "clkout8", "clkout9";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 3c00e6ec9302..dd0a43ec56da 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -22,6 +22,23 @@
22/ { 22/ {
23 compatible = "samsung,exynos4212", "samsung,exynos4"; 23 compatible = "samsung,exynos4212", "samsung,exynos4";
24 24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@A00 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <0xA00>;
33 };
34
35 cpu@A01 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0xA01>;
39 };
40 };
41
25 combiner: interrupt-controller@10440000 { 42 combiner: interrupt-controller@10440000 {
26 samsung,combiner-nr = <18>; 43 samsung,combiner-nr = <18>;
27 }; 44 };
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index c697ff01ae8d..3fbf588682b9 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -45,6 +45,16 @@
45 compatible = "samsung,odroidx2-audio"; 45 compatible = "samsung,odroidx2-audio";
46 samsung,i2s-controller = <&i2s0>; 46 samsung,i2s-controller = <&i2s0>;
47 samsung,audio-codec = <&max98090>; 47 samsung,audio-codec = <&max98090>;
48 assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
49 <&clock_audss EXYNOS_MOUT_I2S>,
50 <&clock_audss EXYNOS_DOUT_SRP>,
51 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
52 assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
53 <&clock_audss EXYNOS_MOUT_AUDSS>;
54 assigned-clock-rates = <0>,
55 <0>,
56 <192000000>,
57 <19200000>;
48 }; 58 };
49 59
50 mmc@12550000 { 60 mmc@12550000 {
@@ -82,18 +92,34 @@
82 92
83 fimc_0: fimc@11800000 { 93 fimc_0: fimc@11800000 {
84 status = "okay"; 94 status = "okay";
95 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
96 <&clock CLK_SCLK_FIMC0>;
97 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
98 assigned-clock-rates = <0>, <176000000>;
85 }; 99 };
86 100
87 fimc_1: fimc@11810000 { 101 fimc_1: fimc@11810000 {
88 status = "okay"; 102 status = "okay";
103 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
104 <&clock CLK_SCLK_FIMC1>;
105 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
106 assigned-clock-rates = <0>, <176000000>;
89 }; 107 };
90 108
91 fimc_2: fimc@11820000 { 109 fimc_2: fimc@11820000 {
92 status = "okay"; 110 status = "okay";
111 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
112 <&clock CLK_SCLK_FIMC2>;
113 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
114 assigned-clock-rates = <0>, <176000000>;
93 }; 115 };
94 116
95 fimc_3: fimc@11830000 { 117 fimc_3: fimc@11830000 {
96 status = "okay"; 118 status = "okay";
119 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
120 <&clock CLK_SCLK_FIMC3>;
121 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
122 assigned-clock-rates = <0>, <176000000>;
97 }; 123 };
98 }; 124 };
99 125
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 5e066cd87f66..29231b452643 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -14,6 +14,7 @@
14 14
15/dts-v1/; 15/dts-v1/;
16#include "exynos4412.dtsi" 16#include "exynos4412.dtsi"
17#include <dt-bindings/gpio/gpio.h>
17 18
18/ { 19/ {
19 model = "Samsung Trats 2 based on Exynos4412"; 20 model = "Samsung Trats 2 based on Exynos4412";
@@ -22,6 +23,7 @@
22 aliases { 23 aliases {
23 i2c9 = &i2c_ak8975; 24 i2c9 = &i2c_ak8975;
24 i2c10 = &i2c_cm36651; 25 i2c10 = &i2c_cm36651;
26 i2c11 = &i2c_max77693;
25 }; 27 };
26 28
27 memory { 29 memory {
@@ -399,8 +401,6 @@
399 regulator-name = "VMEM_VDD_2.8V"; 401 regulator-name = "VMEM_VDD_2.8V";
400 regulator-min-microvolt = <2800000>; 402 regulator-min-microvolt = <2800000>;
401 regulator-max-microvolt = <2800000>; 403 regulator-max-microvolt = <2800000>;
402 regulator-always-on;
403 regulator-mem-off;
404 }; 404 };
405 405
406 ldo23_reg: ldo23 { 406 ldo23_reg: ldo23 {
@@ -503,8 +503,6 @@
503 regulator-name = "VMEM_VDDF_3.0V"; 503 regulator-name = "VMEM_VDDF_3.0V";
504 regulator-min-microvolt = <2850000>; 504 regulator-min-microvolt = <2850000>;
505 regulator-max-microvolt = <2850000>; 505 regulator-max-microvolt = <2850000>;
506 regulator-always-on;
507 regulator-mem-off;
508 }; 506 };
509 507
510 buck9_reg: buck9 { 508 buck9_reg: buck9 {
@@ -518,6 +516,42 @@
518 }; 516 };
519 }; 517 };
520 518
519 i2c_max77693: i2c-gpio-1 {
520 compatible = "i2c-gpio";
521 gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>;
522 i2c-gpio,delay-us = <2>;
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "okay";
526
527 max77693@66 {
528 compatible = "maxim,max77693";
529 interrupt-parent = <&gpx1>;
530 interrupts = <5 2>;
531 reg = <0x66>;
532
533 regulators {
534 esafeout1_reg: ESAFEOUT1@1 {
535 regulator-name = "ESAFEOUT1";
536 };
537 esafeout2_reg: ESAFEOUT2@2 {
538 regulator-name = "ESAFEOUT2";
539 };
540 charger_reg: CHARGER@0 {
541 regulator-name = "CHARGER";
542 regulator-min-microamp = <60000>;
543 regulator-max-microamp = <2580000>;
544 };
545 };
546
547 max77693_haptic {
548 compatible = "maxim,max77693-haptic";
549 haptic-supply = <&ldo26_reg>;
550 pwms = <&pwm 0 38022 0>;
551 };
552 };
553 };
554
521 mmc@12550000 { 555 mmc@12550000 {
522 num-slots = <1>; 556 num-slots = <1>;
523 broken-cd; 557 broken-cd;
@@ -535,6 +569,16 @@
535 cap-mmc-highspeed; 569 cap-mmc-highspeed;
536 }; 570 };
537 571
572 sdhci@12530000 {
573 bus-width = <4>;
574 cd-gpios = <&gpx3 4 0>;
575 cd-inverted;
576 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
577 pinctrl-names = "default";
578 vmmc-supply = <&ldo21_reg>;
579 status = "okay";
580 };
581
538 serial@13800000 { 582 serial@13800000 {
539 status = "okay"; 583 status = "okay";
540 }; 584 };
@@ -551,6 +595,11 @@
551 status = "okay"; 595 status = "okay";
552 }; 596 };
553 597
598 tmu@100C0000 {
599 vtmu-supply = <&ldo10_reg>;
600 status = "okay";
601 };
602
554 i2c_ak8975: i2c-gpio-0 { 603 i2c_ak8975: i2c-gpio-0 {
555 compatible = "i2c-gpio"; 604 compatible = "i2c-gpio";
556 gpios = <&gpy2 4 0>, <&gpy2 5 0>; 605 gpios = <&gpy2 4 0>, <&gpy2 5 0>;
@@ -598,6 +647,13 @@
598 }; 647 };
599 }; 648 };
600 649
650 pwm: pwm@139D0000 {
651 pinctrl-0 = <&pwm0_out>;
652 pinctrl-names = "default";
653 samsung,pwm-outputs = <0>;
654 status = "okay";
655 };
656
601 dsi_0: dsi@11C80000 { 657 dsi_0: dsi@11C80000 {
602 vddcore-supply = <&ldo8_reg>; 658 vddcore-supply = <&ldo8_reg>;
603 vddio-supply = <&ldo10_reg>; 659 vddio-supply = <&ldo10_reg>;
@@ -663,28 +719,51 @@
663 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; 719 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
664 pinctrl-names = "default"; 720 pinctrl-names = "default";
665 status = "okay"; 721 status = "okay";
722 assigned-clocks = <&clock CLK_MOUT_CAM0>,
723 <&clock CLK_MOUT_CAM1>;
724 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>,
725 <&clock CLK_MOUT_MPLL_USER_T>;
666 726
667 fimc_0: fimc@11800000 { 727 fimc_0: fimc@11800000 {
668 status = "okay"; 728 status = "okay";
729 assigned-clocks = <&clock CLK_MOUT_FIMC0>,
730 <&clock CLK_SCLK_FIMC0>;
731 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
732 assigned-clock-rates = <0>, <176000000>;
669 }; 733 };
670 734
671 fimc_1: fimc@11810000 { 735 fimc_1: fimc@11810000 {
672 status = "okay"; 736 status = "okay";
737 assigned-clocks = <&clock CLK_MOUT_FIMC1>,
738 <&clock CLK_SCLK_FIMC1>;
739 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
740 assigned-clock-rates = <0>, <176000000>;
673 }; 741 };
674 742
675 fimc_2: fimc@11820000 { 743 fimc_2: fimc@11820000 {
676 status = "okay"; 744 status = "okay";
745 assigned-clocks = <&clock CLK_MOUT_FIMC2>,
746 <&clock CLK_SCLK_FIMC2>;
747 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
748 assigned-clock-rates = <0>, <176000000>;
677 }; 749 };
678 750
679 fimc_3: fimc@11830000 { 751 fimc_3: fimc@11830000 {
680 status = "okay"; 752 status = "okay";
753 assigned-clocks = <&clock CLK_MOUT_FIMC3>,
754 <&clock CLK_SCLK_FIMC3>;
755 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
756 assigned-clock-rates = <0>, <176000000>;
681 }; 757 };
682 758
683 csis_0: csis@11880000 { 759 csis_0: csis@11880000 {
684 status = "okay"; 760 status = "okay";
685 vddcore-supply = <&ldo8_reg>; 761 vddcore-supply = <&ldo8_reg>;
686 vddio-supply = <&ldo10_reg>; 762 vddio-supply = <&ldo10_reg>;
687 clock-frequency = <176000000>; 763 assigned-clocks = <&clock CLK_MOUT_CSIS0>,
764 <&clock CLK_SCLK_CSIS0>;
765 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
766 assigned-clock-rates = <0>, <176000000>;
688 767
689 /* Camera C (3) MIPI CSI-2 (CSIS0) */ 768 /* Camera C (3) MIPI CSI-2 (CSIS0) */
690 port@3 { 769 port@3 {
@@ -698,10 +777,13 @@
698 }; 777 };
699 778
700 csis_1: csis@11890000 { 779 csis_1: csis@11890000 {
780 status = "okay";
701 vddcore-supply = <&ldo8_reg>; 781 vddcore-supply = <&ldo8_reg>;
702 vddio-supply = <&ldo10_reg>; 782 vddio-supply = <&ldo10_reg>;
703 clock-frequency = <160000000>; 783 assigned-clocks = <&clock CLK_MOUT_CSIS1>,
704 status = "okay"; 784 <&clock CLK_SCLK_CSIS1>;
785 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
786 assigned-clock-rates = <0>, <176000000>;
705 787
706 /* Camera D (4) MIPI CSI-2 (CSIS1) */ 788 /* Camera D (4) MIPI CSI-2 (CSIS1) */
707 port@4 { 789 port@4 {
@@ -782,3 +864,319 @@
782 io-channels = <&adc 2>; /* Battery temperature */ 864 io-channels = <&adc 2>; /* Battery temperature */
783 }; 865 };
784}; 866};
867
868&pinctrl_0 {
869 pinctrl-names = "default";
870 pinctrl-0 = <&sleep0>;
871
872 sleep0: sleep-states {
873 PIN_SLP(gpa0-0, INPUT, NONE);
874 PIN_SLP(gpa0-1, OUT0, NONE);
875 PIN_SLP(gpa0-2, INPUT, NONE);
876 PIN_SLP(gpa0-3, INPUT, UP);
877 PIN_SLP(gpa0-4, INPUT, NONE);
878 PIN_SLP(gpa0-5, INPUT, DOWN);
879 PIN_SLP(gpa0-6, INPUT, DOWN);
880 PIN_SLP(gpa0-7, INPUT, UP);
881
882 PIN_SLP(gpa1-0, INPUT, DOWN);
883 PIN_SLP(gpa1-1, INPUT, DOWN);
884 PIN_SLP(gpa1-2, INPUT, DOWN);
885 PIN_SLP(gpa1-3, INPUT, DOWN);
886 PIN_SLP(gpa1-4, INPUT, DOWN);
887 PIN_SLP(gpa1-5, INPUT, DOWN);
888
889 PIN_SLP(gpb-0, INPUT, NONE);
890 PIN_SLP(gpb-1, INPUT, NONE);
891 PIN_SLP(gpb-2, INPUT, NONE);
892 PIN_SLP(gpb-3, INPUT, NONE);
893 PIN_SLP(gpb-4, INPUT, DOWN);
894 PIN_SLP(gpb-5, INPUT, UP);
895 PIN_SLP(gpb-6, INPUT, DOWN);
896 PIN_SLP(gpb-7, INPUT, DOWN);
897
898 PIN_SLP(gpc0-0, INPUT, DOWN);
899 PIN_SLP(gpc0-1, INPUT, DOWN);
900 PIN_SLP(gpc0-2, INPUT, DOWN);
901 PIN_SLP(gpc0-3, INPUT, DOWN);
902 PIN_SLP(gpc0-4, INPUT, DOWN);
903
904 PIN_SLP(gpc1-0, INPUT, NONE);
905 PIN_SLP(gpc1-1, PREV, NONE);
906 PIN_SLP(gpc1-2, INPUT, NONE);
907 PIN_SLP(gpc1-3, INPUT, NONE);
908 PIN_SLP(gpc1-4, INPUT, NONE);
909
910 PIN_SLP(gpd0-0, INPUT, DOWN);
911 PIN_SLP(gpd0-1, INPUT, DOWN);
912 PIN_SLP(gpd0-2, INPUT, NONE);
913 PIN_SLP(gpd0-3, INPUT, NONE);
914
915 PIN_SLP(gpd1-0, INPUT, DOWN);
916 PIN_SLP(gpd1-1, INPUT, DOWN);
917 PIN_SLP(gpd1-2, INPUT, NONE);
918 PIN_SLP(gpd1-3, INPUT, NONE);
919
920 PIN_SLP(gpf0-0, INPUT, NONE);
921 PIN_SLP(gpf0-1, INPUT, NONE);
922 PIN_SLP(gpf0-2, INPUT, DOWN);
923 PIN_SLP(gpf0-3, INPUT, DOWN);
924 PIN_SLP(gpf0-4, INPUT, NONE);
925 PIN_SLP(gpf0-5, INPUT, DOWN);
926 PIN_SLP(gpf0-6, INPUT, NONE);
927 PIN_SLP(gpf0-7, INPUT, DOWN);
928
929 PIN_SLP(gpf1-0, INPUT, DOWN);
930 PIN_SLP(gpf1-1, INPUT, DOWN);
931 PIN_SLP(gpf1-2, INPUT, DOWN);
932 PIN_SLP(gpf1-3, INPUT, DOWN);
933 PIN_SLP(gpf1-4, INPUT, NONE);
934 PIN_SLP(gpf1-5, INPUT, NONE);
935 PIN_SLP(gpf1-6, INPUT, DOWN);
936 PIN_SLP(gpf1-7, PREV, NONE);
937
938 PIN_SLP(gpf2-0, PREV, NONE);
939 PIN_SLP(gpf2-1, INPUT, DOWN);
940 PIN_SLP(gpf2-2, INPUT, DOWN);
941 PIN_SLP(gpf2-3, INPUT, DOWN);
942 PIN_SLP(gpf2-4, INPUT, DOWN);
943 PIN_SLP(gpf2-5, INPUT, DOWN);
944 PIN_SLP(gpf2-6, INPUT, NONE);
945 PIN_SLP(gpf2-7, INPUT, NONE);
946
947 PIN_SLP(gpf3-0, INPUT, NONE);
948 PIN_SLP(gpf3-1, PREV, NONE);
949 PIN_SLP(gpf3-2, PREV, NONE);
950 PIN_SLP(gpf3-3, PREV, NONE);
951 PIN_SLP(gpf3-4, OUT1, NONE);
952 PIN_SLP(gpf3-5, INPUT, DOWN);
953
954 PIN_SLP(gpj0-0, PREV, NONE);
955 PIN_SLP(gpj0-1, PREV, NONE);
956 PIN_SLP(gpj0-2, PREV, NONE);
957 PIN_SLP(gpj0-3, INPUT, DOWN);
958 PIN_SLP(gpj0-4, PREV, NONE);
959 PIN_SLP(gpj0-5, PREV, NONE);
960 PIN_SLP(gpj0-6, INPUT, DOWN);
961 PIN_SLP(gpj0-7, INPUT, DOWN);
962
963 PIN_SLP(gpj1-0, INPUT, DOWN);
964 PIN_SLP(gpj1-1, PREV, NONE);
965 PIN_SLP(gpj1-2, PREV, NONE);
966 PIN_SLP(gpj1-3, INPUT, DOWN);
967 PIN_SLP(gpj1-4, INPUT, DOWN);
968 };
969};
970
971&pinctrl_1 {
972 pinctrl-names = "default";
973 pinctrl-0 = <&sleep1>;
974
975 sleep1: sleep-states {
976 PIN_SLP(gpk0-0, PREV, NONE);
977 PIN_SLP(gpk0-1, PREV, NONE);
978 PIN_SLP(gpk0-2, OUT0, NONE);
979 PIN_SLP(gpk0-3, PREV, NONE);
980 PIN_SLP(gpk0-4, PREV, NONE);
981 PIN_SLP(gpk0-5, PREV, NONE);
982 PIN_SLP(gpk0-6, PREV, NONE);
983
984 PIN_SLP(gpk1-0, INPUT, DOWN);
985 PIN_SLP(gpk1-1, INPUT, DOWN);
986 PIN_SLP(gpk1-2, INPUT, DOWN);
987 PIN_SLP(gpk1-3, PREV, NONE);
988 PIN_SLP(gpk1-4, PREV, NONE);
989 PIN_SLP(gpk1-5, PREV, NONE);
990 PIN_SLP(gpk1-6, PREV, NONE);
991
992 PIN_SLP(gpk2-0, INPUT, DOWN);
993 PIN_SLP(gpk2-1, INPUT, DOWN);
994 PIN_SLP(gpk2-2, INPUT, DOWN);
995 PIN_SLP(gpk2-3, INPUT, DOWN);
996 PIN_SLP(gpk2-4, INPUT, DOWN);
997 PIN_SLP(gpk2-5, INPUT, DOWN);
998 PIN_SLP(gpk2-6, INPUT, DOWN);
999
1000 PIN_SLP(gpk3-0, OUT0, NONE);
1001 PIN_SLP(gpk3-1, INPUT, NONE);
1002 PIN_SLP(gpk3-2, INPUT, DOWN);
1003 PIN_SLP(gpk3-3, INPUT, NONE);
1004 PIN_SLP(gpk3-4, INPUT, NONE);
1005 PIN_SLP(gpk3-5, INPUT, NONE);
1006 PIN_SLP(gpk3-6, INPUT, NONE);
1007
1008 PIN_SLP(gpl0-0, INPUT, DOWN);
1009 PIN_SLP(gpl0-1, INPUT, DOWN);
1010 PIN_SLP(gpl0-2, INPUT, DOWN);
1011 PIN_SLP(gpl0-3, INPUT, DOWN);
1012 PIN_SLP(gpl0-4, PREV, NONE);
1013 PIN_SLP(gpl0-6, PREV, NONE);
1014
1015 PIN_SLP(gpl1-0, INPUT, DOWN);
1016 PIN_SLP(gpl1-1, INPUT, DOWN);
1017 PIN_SLP(gpl2-0, INPUT, DOWN);
1018 PIN_SLP(gpl2-1, INPUT, DOWN);
1019 PIN_SLP(gpl2-2, INPUT, DOWN);
1020 PIN_SLP(gpl2-3, INPUT, DOWN);
1021 PIN_SLP(gpl2-4, INPUT, DOWN);
1022 PIN_SLP(gpl2-5, INPUT, DOWN);
1023 PIN_SLP(gpl2-6, PREV, NONE);
1024 PIN_SLP(gpl2-7, INPUT, DOWN);
1025
1026 PIN_SLP(gpm0-0, INPUT, DOWN);
1027 PIN_SLP(gpm0-1, INPUT, DOWN);
1028 PIN_SLP(gpm0-2, INPUT, DOWN);
1029 PIN_SLP(gpm0-3, INPUT, DOWN);
1030 PIN_SLP(gpm0-4, INPUT, DOWN);
1031 PIN_SLP(gpm0-5, INPUT, DOWN);
1032 PIN_SLP(gpm0-6, INPUT, DOWN);
1033 PIN_SLP(gpm0-7, INPUT, DOWN);
1034
1035 PIN_SLP(gpm1-0, INPUT, DOWN);
1036 PIN_SLP(gpm1-1, INPUT, DOWN);
1037 PIN_SLP(gpm1-2, INPUT, NONE);
1038 PIN_SLP(gpm1-3, INPUT, NONE);
1039 PIN_SLP(gpm1-4, INPUT, NONE);
1040 PIN_SLP(gpm1-5, INPUT, NONE);
1041 PIN_SLP(gpm1-6, INPUT, DOWN);
1042
1043 PIN_SLP(gpm2-0, INPUT, NONE);
1044 PIN_SLP(gpm2-1, INPUT, NONE);
1045 PIN_SLP(gpm2-2, INPUT, DOWN);
1046 PIN_SLP(gpm2-3, INPUT, DOWN);
1047 PIN_SLP(gpm2-4, INPUT, DOWN);
1048
1049 PIN_SLP(gpm3-0, PREV, NONE);
1050 PIN_SLP(gpm3-1, PREV, NONE);
1051 PIN_SLP(gpm3-2, PREV, NONE);
1052 PIN_SLP(gpm3-3, OUT1, NONE);
1053 PIN_SLP(gpm3-4, INPUT, DOWN);
1054 PIN_SLP(gpm3-5, INPUT, DOWN);
1055 PIN_SLP(gpm3-6, INPUT, DOWN);
1056 PIN_SLP(gpm3-7, INPUT, DOWN);
1057
1058 PIN_SLP(gpm4-0, INPUT, DOWN);
1059 PIN_SLP(gpm4-1, INPUT, DOWN);
1060 PIN_SLP(gpm4-2, INPUT, DOWN);
1061 PIN_SLP(gpm4-3, INPUT, DOWN);
1062 PIN_SLP(gpm4-4, INPUT, DOWN);
1063 PIN_SLP(gpm4-5, INPUT, DOWN);
1064 PIN_SLP(gpm4-6, INPUT, DOWN);
1065 PIN_SLP(gpm4-7, INPUT, DOWN);
1066
1067 PIN_SLP(gpy0-0, INPUT, DOWN);
1068 PIN_SLP(gpy0-1, INPUT, DOWN);
1069 PIN_SLP(gpy0-2, INPUT, DOWN);
1070 PIN_SLP(gpy0-3, INPUT, DOWN);
1071 PIN_SLP(gpy0-4, INPUT, DOWN);
1072 PIN_SLP(gpy0-5, INPUT, DOWN);
1073
1074 PIN_SLP(gpy1-0, INPUT, DOWN);
1075 PIN_SLP(gpy1-1, INPUT, DOWN);
1076 PIN_SLP(gpy1-2, INPUT, DOWN);
1077 PIN_SLP(gpy1-3, INPUT, DOWN);
1078
1079 PIN_SLP(gpy2-0, PREV, NONE);
1080 PIN_SLP(gpy2-1, INPUT, DOWN);
1081 PIN_SLP(gpy2-2, INPUT, NONE);
1082 PIN_SLP(gpy2-3, INPUT, NONE);
1083 PIN_SLP(gpy2-4, INPUT, NONE);
1084 PIN_SLP(gpy2-5, INPUT, NONE);
1085
1086 PIN_SLP(gpy3-0, INPUT, DOWN);
1087 PIN_SLP(gpy3-1, INPUT, DOWN);
1088 PIN_SLP(gpy3-2, INPUT, DOWN);
1089 PIN_SLP(gpy3-3, INPUT, DOWN);
1090 PIN_SLP(gpy3-4, INPUT, DOWN);
1091 PIN_SLP(gpy3-5, INPUT, DOWN);
1092 PIN_SLP(gpy3-6, INPUT, DOWN);
1093 PIN_SLP(gpy3-7, INPUT, DOWN);
1094
1095 PIN_SLP(gpy4-0, INPUT, DOWN);
1096 PIN_SLP(gpy4-1, INPUT, DOWN);
1097 PIN_SLP(gpy4-2, INPUT, DOWN);
1098 PIN_SLP(gpy4-3, INPUT, DOWN);
1099 PIN_SLP(gpy4-4, INPUT, DOWN);
1100 PIN_SLP(gpy4-5, INPUT, DOWN);
1101 PIN_SLP(gpy4-6, INPUT, DOWN);
1102 PIN_SLP(gpy4-7, INPUT, DOWN);
1103
1104 PIN_SLP(gpy5-0, INPUT, DOWN);
1105 PIN_SLP(gpy5-1, INPUT, DOWN);
1106 PIN_SLP(gpy5-2, INPUT, DOWN);
1107 PIN_SLP(gpy5-3, INPUT, DOWN);
1108 PIN_SLP(gpy5-4, INPUT, DOWN);
1109 PIN_SLP(gpy5-5, INPUT, DOWN);
1110 PIN_SLP(gpy5-6, INPUT, DOWN);
1111 PIN_SLP(gpy5-7, INPUT, DOWN);
1112
1113 PIN_SLP(gpy6-0, INPUT, DOWN);
1114 PIN_SLP(gpy6-1, INPUT, DOWN);
1115 PIN_SLP(gpy6-2, INPUT, DOWN);
1116 PIN_SLP(gpy6-3, INPUT, DOWN);
1117 PIN_SLP(gpy6-4, INPUT, DOWN);
1118 PIN_SLP(gpy6-5, INPUT, DOWN);
1119 PIN_SLP(gpy6-6, INPUT, DOWN);
1120 PIN_SLP(gpy6-7, INPUT, DOWN);
1121 };
1122};
1123
1124&pinctrl_2 {
1125 pinctrl-names = "default";
1126 pinctrl-0 = <&sleep2>;
1127
1128 sleep2: sleep-states {
1129 PIN_SLP(gpz-0, INPUT, DOWN);
1130 PIN_SLP(gpz-1, INPUT, DOWN);
1131 PIN_SLP(gpz-2, INPUT, DOWN);
1132 PIN_SLP(gpz-3, INPUT, DOWN);
1133 PIN_SLP(gpz-4, INPUT, DOWN);
1134 PIN_SLP(gpz-5, INPUT, DOWN);
1135 PIN_SLP(gpz-6, INPUT, DOWN);
1136 };
1137};
1138
1139&pinctrl_3 {
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&sleep3>;
1142
1143 sleep3: sleep-states {
1144 PIN_SLP(gpv0-0, INPUT, DOWN);
1145 PIN_SLP(gpv0-1, INPUT, DOWN);
1146 PIN_SLP(gpv0-2, INPUT, DOWN);
1147 PIN_SLP(gpv0-3, INPUT, DOWN);
1148 PIN_SLP(gpv0-4, INPUT, DOWN);
1149 PIN_SLP(gpv0-5, INPUT, DOWN);
1150 PIN_SLP(gpv0-6, INPUT, DOWN);
1151 PIN_SLP(gpv0-7, INPUT, DOWN);
1152
1153 PIN_SLP(gpv1-0, INPUT, DOWN);
1154 PIN_SLP(gpv1-1, INPUT, DOWN);
1155 PIN_SLP(gpv1-2, INPUT, DOWN);
1156 PIN_SLP(gpv1-3, INPUT, DOWN);
1157 PIN_SLP(gpv1-4, INPUT, DOWN);
1158 PIN_SLP(gpv1-5, INPUT, DOWN);
1159 PIN_SLP(gpv1-6, INPUT, DOWN);
1160 PIN_SLP(gpv1-7, INPUT, DOWN);
1161
1162 PIN_SLP(gpv2-0, INPUT, DOWN);
1163 PIN_SLP(gpv2-1, INPUT, DOWN);
1164 PIN_SLP(gpv2-2, INPUT, DOWN);
1165 PIN_SLP(gpv2-3, INPUT, DOWN);
1166 PIN_SLP(gpv2-4, INPUT, DOWN);
1167 PIN_SLP(gpv2-5, INPUT, DOWN);
1168 PIN_SLP(gpv2-6, INPUT, DOWN);
1169 PIN_SLP(gpv2-7, INPUT, DOWN);
1170
1171 PIN_SLP(gpv3-0, INPUT, DOWN);
1172 PIN_SLP(gpv3-1, INPUT, DOWN);
1173 PIN_SLP(gpv3-2, INPUT, DOWN);
1174 PIN_SLP(gpv3-3, INPUT, DOWN);
1175 PIN_SLP(gpv3-4, INPUT, DOWN);
1176 PIN_SLP(gpv3-5, INPUT, DOWN);
1177 PIN_SLP(gpv3-6, INPUT, DOWN);
1178 PIN_SLP(gpv3-7, INPUT, DOWN);
1179
1180 PIN_SLP(gpv4-0, INPUT, DOWN);
1181 };
1182};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d8bc059e172f..0f6ec93bb1d8 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -22,6 +22,35 @@
22/ { 22/ {
23 compatible = "samsung,exynos4412", "samsung,exynos4"; 23 compatible = "samsung,exynos4412", "samsung,exynos4";
24 24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@A00 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 reg = <0xA00>;
33 };
34
35 cpu@A01 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0xA01>;
39 };
40
41 cpu@A02 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 reg = <0xA02>;
45 };
46
47 cpu@A03 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 reg = <0xA03>;
51 };
52 };
53
25 combiner: interrupt-controller@10440000 { 54 combiner: interrupt-controller@10440000 {
26 samsung,combiner-nr = <20>; 55 samsung,combiner-nr = <20>;
27 }; 56 };
diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
new file mode 100644
index 000000000000..75af9c56123e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi
@@ -0,0 +1,573 @@
1/*
2 * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 *
6 * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device
7 * tree nodes are listed in this file.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14&pinctrl_0 {
15 gpa0: gpa0 {
16 gpio-controller;
17 #gpio-cells = <2>;
18
19 interrupt-controller;
20 #interrupt-cells = <2>;
21 };
22
23 gpa1: gpa1 {
24 gpio-controller;
25 #gpio-cells = <2>;
26
27 interrupt-controller;
28 #interrupt-cells = <2>;
29 };
30
31 gpb: gpb {
32 gpio-controller;
33 #gpio-cells = <2>;
34
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 };
38
39 gpc0: gpc0 {
40 gpio-controller;
41 #gpio-cells = <2>;
42
43 interrupt-controller;
44 #interrupt-cells = <2>;
45 };
46
47 gpc1: gpc1 {
48 gpio-controller;
49 #gpio-cells = <2>;
50
51 interrupt-controller;
52 #interrupt-cells = <2>;
53 };
54
55 gpd0: gpd0 {
56 gpio-controller;
57 #gpio-cells = <2>;
58
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 };
62
63 gpd1: gpd1 {
64 gpio-controller;
65 #gpio-cells = <2>;
66
67 interrupt-controller;
68 #interrupt-cells = <2>;
69 };
70
71 gpf0: gpf0 {
72 gpio-controller;
73 #gpio-cells = <2>;
74
75 interrupt-controller;
76 #interrupt-cells = <2>;
77 };
78
79 gpf1: gpf1 {
80 gpio-controller;
81 #gpio-cells = <2>;
82
83 interrupt-controller;
84 #interrupt-cells = <2>;
85 };
86
87 gpf2: gpf2 {
88 gpio-controller;
89 #gpio-cells = <2>;
90
91 interrupt-controller;
92 #interrupt-cells = <2>;
93 };
94
95 uart0_data: uart0-data {
96 samsung,pins = "gpa0-0", "gpa0-1";
97 samsung,pin-function = <0x2>;
98 samsung,pin-pud = <0>;
99 samsung,pin-drv = <0>;
100 };
101
102 uart0_fctl: uart0-fctl {
103 samsung,pins = "gpa0-2", "gpa0-3";
104 samsung,pin-function = <2>;
105 samsung,pin-pud = <0>;
106 samsung,pin-drv = <0>;
107 };
108
109 uart1_data: uart1-data {
110 samsung,pins = "gpa0-4", "gpa0-5";
111 samsung,pin-function = <2>;
112 samsung,pin-pud = <0>;
113 samsung,pin-drv = <0>;
114 };
115
116 uart1_fctl: uart1-fctl {
117 samsung,pins = "gpa0-6", "gpa0-7";
118 samsung,pin-function = <2>;
119 samsung,pin-pud = <0>;
120 samsung,pin-drv = <0>;
121 };
122
123 uart2_data: uart2-data {
124 samsung,pins = "gpa1-0", "gpa1-1";
125 samsung,pin-function = <2>;
126 samsung,pin-pud = <0>;
127 samsung,pin-drv = <0>;
128 };
129
130 uart2_fctl: uart2-fctl {
131 samsung,pins = "gpa1-2", "gpa1-3";
132 samsung,pin-function = <2>;
133 samsung,pin-pud = <0>;
134 samsung,pin-drv = <0>;
135 };
136
137 uart3_data: uart3-data {
138 samsung,pins = "gpa1-4", "gpa1-5";
139 samsung,pin-function = <2>;
140 samsung,pin-pud = <0>;
141 samsung,pin-drv = <0>;
142 };
143
144 i2c2_bus: i2c2-bus {
145 samsung,pins = "gpa0-6", "gpa0-7";
146 samsung,pin-function = <3>;
147 samsung,pin-pud = <3>;
148 samsung,pin-drv = <0>;
149 };
150
151 i2c3_bus: i2c3-bus {
152 samsung,pins = "gpa1-2", "gpa1-3";
153 samsung,pin-function = <3>;
154 samsung,pin-pud = <3>;
155 samsung,pin-drv = <0>;
156 };
157
158 spi0_bus: spi0-bus {
159 samsung,pins = "gpb-0", "gpb-2", "gpb-3";
160 samsung,pin-function = <2>;
161 samsung,pin-pud = <3>;
162 samsung,pin-drv = <0>;
163 };
164
165 i2c4_bus: i2c4-bus {
166 samsung,pins = "gpb-0", "gpb-1";
167 samsung,pin-function = <3>;
168 samsung,pin-pud = <3>;
169 samsung,pin-drv = <0>;
170 };
171
172 spi1_bus: spi1-bus {
173 samsung,pins = "gpb-4", "gpb-6", "gpb-7";
174 samsung,pin-function = <2>;
175 samsung,pin-pud = <3>;
176 samsung,pin-drv = <0>;
177 };
178
179 i2c5_bus: i2c5-bus {
180 samsung,pins = "gpb-2", "gpb-3";
181 samsung,pin-function = <3>;
182 samsung,pin-pud = <3>;
183 samsung,pin-drv = <0>;
184 };
185
186 i2s1_bus: i2s1-bus {
187 samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3",
188 "gpc0-4";
189 samsung,pin-function = <2>;
190 samsung,pin-pud = <0>;
191 samsung,pin-drv = <0>;
192 };
193
194 i2s2_bus: i2s2-bus {
195 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
196 "gpc1-4";
197 samsung,pin-function = <2>;
198 samsung,pin-pud = <0>;
199 samsung,pin-drv = <0>;
200 };
201
202 pcm2_bus: pcm2-bus {
203 samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
204 "gpc1-4";
205 samsung,pin-function = <3>;
206 samsung,pin-pud = <0>;
207 samsung,pin-drv = <0>;
208 };
209
210 i2c6_bus: i2c6-bus {
211 samsung,pins = "gpc1-3", "gpc1-4";
212 samsung,pin-function = <4>;
213 samsung,pin-pud = <3>;
214 samsung,pin-drv = <0>;
215 };
216
217 spi2_bus: spi2-bus {
218 samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4";
219 samsung,pin-function = <5>;
220 samsung,pin-pud = <3>;
221 samsung,pin-drv = <0>;
222 };
223
224 pwm0_out: pwm0-out {
225 samsung,pins = "gpd0-0";
226 samsung,pin-function = <2>;
227 samsung,pin-pud = <0>;
228 samsung,pin-drv = <0>;
229 };
230
231 pwm1_out: pwm1-out {
232 samsung,pins = "gpd0-1";
233 samsung,pin-function = <2>;
234 samsung,pin-pud = <0>;
235 samsung,pin-drv = <0>;
236 };
237
238 pwm2_out: pwm2-out {
239 samsung,pins = "gpd0-2";
240 samsung,pin-function = <2>;
241 samsung,pin-pud = <0>;
242 samsung,pin-drv = <0>;
243 };
244
245 pwm3_out: pwm3-out {
246 samsung,pins = "gpd0-3";
247 samsung,pin-function = <2>;
248 samsung,pin-pud = <0>;
249 samsung,pin-drv = <0>;
250 };
251
252 i2c7_bus: i2c7-bus {
253 samsung,pins = "gpd0-2", "gpd0-3";
254 samsung,pin-function = <3>;
255 samsung,pin-pud = <3>;
256 samsung,pin-drv = <0>;
257 };
258
259 i2c0_bus: i2c0-bus {
260 samsung,pins = "gpd1-0", "gpd1-1";
261 samsung,pin-function = <2>;
262 samsung,pin-pud = <3>;
263 samsung,pin-drv = <0>;
264 };
265
266 i2c1_bus: i2c1-bus {
267 samsung,pins = "gpd1-2", "gpd1-3";
268 samsung,pin-function = <2>;
269 samsung,pin-pud = <3>;
270 samsung,pin-drv = <0>;
271 };
272};
273
274&pinctrl_1 {
275 gpk0: gpk0 {
276 gpio-controller;
277 #gpio-cells = <2>;
278
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 };
282
283 gpk1: gpk1 {
284 gpio-controller;
285 #gpio-cells = <2>;
286
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 gpk2: gpk2 {
292 gpio-controller;
293 #gpio-cells = <2>;
294
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
298
299 gpk3: gpk3 {
300 gpio-controller;
301 #gpio-cells = <2>;
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 gpl0: gpl0 {
308 gpio-controller;
309 #gpio-cells = <2>;
310
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314
315 gpm0: gpm0 {
316 gpio-controller;
317 #gpio-cells = <2>;
318
319 interrupt-controller;
320 #interrupt-cells = <2>;
321 };
322
323 gpm1: gpm1 {
324 gpio-controller;
325 #gpio-cells = <2>;
326
327 interrupt-controller;
328 #interrupt-cells = <2>;
329 };
330
331 gpm2: gpm2 {
332 gpio-controller;
333 #gpio-cells = <2>;
334
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338
339 gpm3: gpm3 {
340 gpio-controller;
341 #gpio-cells = <2>;
342
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 };
346
347 gpm4: gpm4 {
348 gpio-controller;
349 #gpio-cells = <2>;
350
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpx0: gpx0 {
356 gpio-controller;
357 #gpio-cells = <2>;
358
359 interrupt-controller;
360 interrupt-parent = <&gic>;
361 interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
362 <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
363 #interrupt-cells = <2>;
364 };
365
366 gpx1: gpx1 {
367 gpio-controller;
368 #gpio-cells = <2>;
369
370 interrupt-controller;
371 interrupt-parent = <&gic>;
372 interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
373 <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
374 #interrupt-cells = <2>;
375 };
376
377 gpx2: gpx2 {
378 gpio-controller;
379 #gpio-cells = <2>;
380
381 interrupt-controller;
382 #interrupt-cells = <2>;
383 };
384
385 gpx3: gpx3 {
386 gpio-controller;
387 #gpio-cells = <2>;
388
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 };
392
393 sd0_clk: sd0-clk {
394 samsung,pins = "gpk0-0";
395 samsung,pin-function = <2>;
396 samsung,pin-pud = <0>;
397 samsung,pin-drv = <3>;
398 };
399
400 sd0_cmd: sd0-cmd {
401 samsung,pins = "gpk0-1";
402 samsung,pin-function = <2>;
403 samsung,pin-pud = <0>;
404 samsung,pin-drv = <3>;
405 };
406
407 sd0_cd: sd0-cd {
408 samsung,pins = "gpk0-2";
409 samsung,pin-function = <2>;
410 samsung,pin-pud = <3>;
411 samsung,pin-drv = <3>;
412 };
413
414 sd0_rdqs: sd0-rdqs {
415 samsung,pins = "gpk0-7";
416 samsung,pin-function = <2>;
417 samsung,pin-pud = <0>;
418 samsung,pin-drv = <3>;
419 };
420
421 sd0_bus1: sd0-bus-width1 {
422 samsung,pins = "gpk0-3";
423 samsung,pin-function = <2>;
424 samsung,pin-pud = <3>;
425 samsung,pin-drv = <3>;
426 };
427
428 sd0_bus4: sd0-bus-width4 {
429 samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
430 samsung,pin-function = <2>;
431 samsung,pin-pud = <3>;
432 samsung,pin-drv = <3>;
433 };
434
435 sd0_bus8: sd0-bus-width8 {
436 samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
437 samsung,pin-function = <2>;
438 samsung,pin-pud = <3>;
439 samsung,pin-drv = <3>;
440 };
441
442 sd1_clk: sd1-clk {
443 samsung,pins = "gpk1-0";
444 samsung,pin-function = <2>;
445 samsung,pin-pud = <0>;
446 samsung,pin-drv = <3>;
447 };
448
449 sd1_cmd: sd1-cmd {
450 samsung,pins = "gpk1-1";
451 samsung,pin-function = <2>;
452 samsung,pin-pud = <0>;
453 samsung,pin-drv = <3>;
454 };
455
456 sd1_cd: sd1-cd {
457 samsung,pins = "gpk1-2";
458 samsung,pin-function = <2>;
459 samsung,pin-pud = <3>;
460 samsung,pin-drv = <3>;
461 };
462
463 sd1_bus1: sd1-bus-width1 {
464 samsung,pins = "gpk1-3";
465 samsung,pin-function = <2>;
466 samsung,pin-pud = <3>;
467 samsung,pin-drv = <3>;
468 };
469
470 sd1_bus4: sd1-bus-width4 {
471 samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
472 samsung,pin-function = <2>;
473 samsung,pin-pud = <3>;
474 samsung,pin-drv = <3>;
475 };
476
477 sd2_clk: sd2-clk {
478 samsung,pins = "gpk2-0";
479 samsung,pin-function = <2>;
480 samsung,pin-pud = <0>;
481 samsung,pin-drv = <4>;
482 };
483
484 sd2_cmd: sd2-cmd {
485 samsung,pins = "gpk2-1";
486 samsung,pin-function = <2>;
487 samsung,pin-pud = <0>;
488 samsung,pin-drv = <4>;
489 };
490
491 sd2_cd: sd2-cd {
492 samsung,pins = "gpk2-2";
493 samsung,pin-function = <2>;
494 samsung,pin-pud = <3>;
495 samsung,pin-drv = <3>;
496 };
497
498 sd2_bus1: sd2-bus-width1 {
499 samsung,pins = "gpk2-3";
500 samsung,pin-function = <2>;
501 samsung,pin-pud = <3>;
502 samsung,pin-drv = <4>;
503 };
504
505 sd2_bus4: sd2-bus-width4 {
506 samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6";
507 samsung,pin-function = <2>;
508 samsung,pin-pud = <3>;
509 samsung,pin-drv = <4>;
510 };
511
512 cam_port_b_io: cam-port-b-io {
513 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
514 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
515 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
516 samsung,pin-function = <3>;
517 samsung,pin-pud = <3>;
518 samsung,pin-drv = <0>;
519 };
520
521 cam_port_b_clk_active: cam-port-b-clk-active {
522 samsung,pins = "gpm2-2";
523 samsung,pin-function = <3>;
524 samsung,pin-pud = <0>;
525 samsung,pin-drv = <3>;
526 };
527
528 cam_port_b_clk_idle: cam-port-b-clk-idle {
529 samsung,pins = "gpm2-2";
530 samsung,pin-function = <0>;
531 samsung,pin-pud = <0>;
532 samsung,pin-drv = <0>;
533 };
534
535 fimc_is_i2c0: fimc-is-i2c0 {
536 samsung,pins = "gpm4-0", "gpm4-1";
537 samsung,pin-function = <2>;
538 samsung,pin-pud = <0>;
539 samsung,pin-drv = <0>;
540 };
541
542 fimc_is_i2c1: fimc-is-i2c1 {
543 samsung,pins = "gpm4-2", "gpm4-3";
544 samsung,pin-function = <2>;
545 samsung,pin-pud = <0>;
546 samsung,pin-drv = <0>;
547 };
548
549 fimc_is_uart: fimc-is-uart {
550 samsung,pins = "gpm3-5", "gpm3-7";
551 samsung,pin-function = <3>;
552 samsung,pin-pud = <0>;
553 samsung,pin-drv = <0>;
554 };
555};
556
557&pinctrl_2 {
558 gpz: gpz {
559 gpio-controller;
560 #gpio-cells = <2>;
561
562 interrupt-controller;
563 #interrupt-cells = <2>;
564 };
565
566 i2s0_bus: i2s0-bus {
567 samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
568 "gpz-4", "gpz-5", "gpz-6";
569 samsung,pin-function = <2>;
570 samsung,pin-pud = <0>;
571 samsung,pin-drv = <0>;
572 };
573};
diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi
new file mode 100644
index 000000000000..c1c9b37340d9
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4415.dtsi
@@ -0,0 +1,604 @@
1/*
2 * Samsung's Exynos4415 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 *
6 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
7 * based board files can include this file and provide values for board
8 * specific bindings.
9 *
10 * Note: This file does not include device nodes for all the controllers in
11 * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
12 * nodes can be added to this file.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include "skeleton.dtsi"
20#include <dt-bindings/clock/exynos4415.h>
21#include <dt-bindings/clock/exynos-audss-clk.h>
22
23/ {
24 compatible = "samsung,exynos4415";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;
29 pinctrl1 = &pinctrl_1;
30 pinctrl2 = &pinctrl_2;
31 mshc0 = &mshc_0;
32 mshc1 = &mshc_1;
33 mshc2 = &mshc_2;
34 spi0 = &spi_0;
35 spi1 = &spi_1;
36 spi2 = &spi_2;
37 i2c0 = &i2c_0;
38 i2c1 = &i2c_1;
39 i2c2 = &i2c_2;
40 i2c3 = &i2c_3;
41 i2c4 = &i2c_4;
42 i2c5 = &i2c_5;
43 i2c6 = &i2c_6;
44 i2c7 = &i2c_7;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@a00 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a9";
54 reg = <0xa00>;
55 clock-frequency = <1600000000>;
56 };
57
58 cpu1: cpu@a01 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a9";
61 reg = <0xa01>;
62 clock-frequency = <1600000000>;
63 };
64
65 cpu2: cpu@a02 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a9";
68 reg = <0xa02>;
69 clock-frequency = <1600000000>;
70 };
71
72 cpu3: cpu@a03 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a9";
75 reg = <0xa03>;
76 clock-frequency = <1600000000>;
77 };
78 };
79
80 soc: soc {
81 compatible = "simple-bus";
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 sysram@02020000 {
87 compatible = "mmio-sram";
88 reg = <0x02020000 0x50000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges = <0 0x02020000 0x50000>;
92
93 smp-sysram@0 {
94 compatible = "samsung,exynos4210-sysram";
95 reg = <0x0 0x1000>;
96 };
97
98 smp-sysram@4f000 {
99 compatible = "samsung,exynos4210-sysram-ns";
100 reg = <0x4f000 0x1000>;
101 };
102 };
103
104 pinctrl_2: pinctrl@03860000 {
105 compatible = "samsung,exynos4415-pinctrl";
106 reg = <0x03860000 0x1000>;
107 interrupts = <0 242 0>;
108 };
109
110 chipid@10000000 {
111 compatible = "samsung,exynos4210-chipid";
112 reg = <0x10000000 0x100>;
113 };
114
115 sysreg_system_controller: syscon@10010000 {
116 compatible = "samsung,exynos4-sysreg", "syscon";
117 reg = <0x10010000 0x400>;
118 };
119
120 pmu_system_controller: system-controller@10020000 {
121 compatible = "samsung,exynos4415-pmu", "syscon";
122 reg = <0x10020000 0x4000>;
123 };
124
125 mipi_phy: video-phy@10020710 {
126 compatible = "samsung,s5pv210-mipi-video-phy";
127 reg = <0x10020710 8>;
128 #phy-cells = <1>;
129 };
130
131 pd_cam: cam-power-domain@10024000 {
132 compatible = "samsung,exynos4210-pd";
133 reg = <0x10024000 0x20>;
134 };
135
136 pd_tv: tv-power-domain@10024020 {
137 compatible = "samsung,exynos4210-pd";
138 reg = <0x10024020 0x20>;
139 };
140
141 pd_mfc: mfc-power-domain@10024040 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10024040 0x20>;
144 };
145
146 pd_g3d: g3d-power-domain@10024060 {
147 compatible = "samsung,exynos4210-pd";
148 reg = <0x10024060 0x20>;
149 };
150
151 pd_lcd0: lcd0-power-domain@10024080 {
152 compatible = "samsung,exynos4210-pd";
153 reg = <0x10024080 0x20>;
154 };
155
156 pd_isp0: isp0-power-domain@100240A0 {
157 compatible = "samsung,exynos4210-pd";
158 reg = <0x100240A0 0x20>;
159 };
160
161 pd_isp1: isp1-power-domain@100240E0 {
162 compatible = "samsung,exynos4210-pd";
163 reg = <0x100240E0 0x20>;
164 };
165
166 cmu: clock-controller@10030000 {
167 compatible = "samsung,exynos4415-cmu";
168 reg = <0x10030000 0x18000>;
169 #clock-cells = <1>;
170 };
171
172 rtc: rtc@10070000 {
173 compatible = "samsung,exynos3250-rtc";
174 reg = <0x10070000 0x100>;
175 interrupts = <0 73 0>, <0 74 0>;
176 status = "disabled";
177 };
178
179 mct@10050000 {
180 compatible = "samsung,exynos4210-mct";
181 reg = <0x10050000 0x800>;
182 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
183 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
184 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
185 clock-names = "fin_pll", "mct";
186 };
187
188 gic: interrupt-controller@10481000 {
189 compatible = "arm,cortex-a9-gic";
190 #interrupt-cells = <3>;
191 interrupt-controller;
192 reg = <0x10481000 0x1000>,
193 <0x10482000 0x1000>,
194 <0x10484000 0x2000>,
195 <0x10486000 0x2000>;
196 interrupts = <1 9 0xf04>;
197 };
198
199 l2c: l2-cache-controller@10502000 {
200 compatible = "arm,pl310-cache";
201 reg = <0x10502000 0x1000>;
202 cache-unified;
203 cache-level = <2>;
204 arm,tag-latency = <2 2 1>;
205 arm,data-latency = <3 2 1>;
206 arm,double-linefill = <1>;
207 arm,double-linefill-incr = <0>;
208 arm,double-linefill-wrap = <1>;
209 arm,prefetch-drop = <1>;
210 arm,prefetch-offset = <7>;
211 };
212
213 cmu_dmc: clock-controller@105C0000 {
214 compatible = "samsung,exynos4415-cmu-dmc";
215 reg = <0x105C0000 0x3000>;
216 #clock-cells = <1>;
217 };
218
219 pinctrl_1: pinctrl@11000000 {
220 compatible = "samsung,exynos4415-pinctrl";
221 reg = <0x11000000 0x1000>;
222 interrupts = <0 225 0>;
223
224 wakeup-interrupt-controller {
225 compatible = "samsung,exynos4210-wakeup-eint";
226 interrupt-parent = <&gic>;
227 interrupts = <0 48 0>;
228 };
229 };
230
231 pinctrl_0: pinctrl@11400000 {
232 compatible = "samsung,exynos4415-pinctrl";
233 reg = <0x11400000 0x1000>;
234 interrupts = <0 240 0>;
235 };
236
237 hsotg: hsotg@12480000 {
238 compatible = "samsung,s3c6400-hsotg";
239 reg = <0x12480000 0x20000>;
240 interrupts = <0 141 0>;
241 clocks = <&cmu CLK_USBDEVICE>;
242 clock-names = "otg";
243 phys = <&exynos_usbphy 0>;
244 phy-names = "usb2-phy";
245 status = "disabled";
246 };
247
248 mshc_0: mshc@12510000 {
249 compatible = "samsung,exynos5250-dw-mshc";
250 reg = <0x12510000 0x1000>;
251 interrupts = <0 142 0>;
252 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
253 clock-names = "biu", "ciu";
254 fifo-depth = <0x80>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 status = "disabled";
258 };
259
260 mshc_1: mshc@12520000 {
261 compatible = "samsung,exynos5250-dw-mshc";
262 reg = <0x12520000 0x1000>;
263 interrupts = <0 143 0>;
264 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
265 clock-names = "biu", "ciu";
266 fifo-depth = <0x80>;
267 #address-cells = <1>;
268 #size-cells = <0>;
269 status = "disabled";
270 };
271
272 mshc_2: mshc@12530000 {
273 compatible = "samsung,exynos5250-dw-mshc";
274 reg = <0x12530000 0x1000>;
275 interrupts = <0 144 0>;
276 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
277 clock-names = "biu", "ciu";
278 fifo-depth = <0x80>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 status = "disabled";
282 };
283
284 ehci: ehci@12580000 {
285 compatible = "samsung,exynos4210-ehci";
286 reg = <0x12580000 0x100>;
287 interrupts = <0 140 0>;
288 clocks = <&cmu CLK_USBHOST>;
289 clock-names = "usbhost";
290 status = "disabled";
291 #address-cells = <1>;
292 #size-cells = <0>;
293 port@0 {
294 reg = <0>;
295 phys = <&exynos_usbphy 1>;
296 status = "disabled";
297 };
298 port@1 {
299 reg = <1>;
300 phys = <&exynos_usbphy 2>;
301 status = "disabled";
302 };
303 port@2 {
304 reg = <2>;
305 phys = <&exynos_usbphy 3>;
306 status = "disabled";
307 };
308 };
309
310 ohci: ohci@12590000 {
311 compatible = "samsung,exynos4210-ohci";
312 reg = <0x12590000 0x100>;
313 interrupts = <0 140 0>;
314 clocks = <&cmu CLK_USBHOST>;
315 clock-names = "usbhost";
316 status = "disabled";
317 #address-cells = <1>;
318 #size-cells = <0>;
319 port@0 {
320 reg = <0>;
321 phys = <&exynos_usbphy 1>;
322 status = "disabled";
323 };
324 };
325
326 exynos_usbphy: exynos-usbphy@125B0000 {
327 compatible = "samsung,exynos4x12-usb2-phy";
328 reg = <0x125B0000 0x100>;
329 samsung,pmureg-phandle = <&pmu_system_controller>;
330 samsung,sysreg-phandle = <&sysreg_system_controller>;
331 clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
332 clock-names = "phy", "ref";
333 #phy-cells = <1>;
334 status = "disabled";
335 };
336
337 amba {
338 compatible = "arm,amba-bus";
339 #address-cells = <1>;
340 #size-cells = <1>;
341 interrupt-parent = <&gic>;
342 ranges;
343
344 pdma0: pdma@12680000 {
345 compatible = "arm,pl330", "arm,primecell";
346 reg = <0x12680000 0x1000>;
347 interrupts = <0 138 0>;
348 clocks = <&cmu CLK_PDMA0>;
349 clock-names = "apb_pclk";
350 #dma-cells = <1>;
351 #dma-channels = <8>;
352 #dma-requests = <32>;
353 };
354
355 pdma1: pdma@12690000 {
356 compatible = "arm,pl330", "arm,primecell";
357 reg = <0x12690000 0x1000>;
358 interrupts = <0 139 0>;
359 clocks = <&cmu CLK_PDMA1>;
360 clock-names = "apb_pclk";
361 #dma-cells = <1>;
362 #dma-channels = <8>;
363 #dma-requests = <32>;
364 };
365 };
366
367 adc: adc@126C0000 {
368 compatible = "samsung,exynos3250-adc",
369 "samsung,exynos-adc-v2";
370 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
371 interrupts = <0 137 0>;
372 clock-names = "adc", "sclk";
373 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
374 #io-channel-cells = <1>;
375 io-channel-ranges;
376 status = "disabled";
377 };
378
379 serial_0: serial@13800000 {
380 compatible = "samsung,exynos4210-uart";
381 reg = <0x13800000 0x100>;
382 interrupts = <0 109 0>;
383 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
384 clock-names = "uart", "clk_uart_baud0";
385 status = "disabled";
386 };
387
388 serial_1: serial@13810000 {
389 compatible = "samsung,exynos4210-uart";
390 reg = <0x13810000 0x100>;
391 interrupts = <0 110 0>;
392 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
393 clock-names = "uart", "clk_uart_baud0";
394 status = "disabled";
395 };
396
397 serial_2: serial@13820000 {
398 compatible = "samsung,exynos4210-uart";
399 reg = <0x13820000 0x100>;
400 interrupts = <0 111 0>;
401 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
402 clock-names = "uart", "clk_uart_baud0";
403 status = "disabled";
404 };
405
406 serial_3: serial@13830000 {
407 compatible = "samsung,exynos4210-uart";
408 reg = <0x13830000 0x100>;
409 interrupts = <0 112 0>;
410 clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
411 clock-names = "uart", "clk_uart_baud0";
412 status = "disabled";
413 };
414
415 i2c_0: i2c@13860000 {
416 #address-cells = <1>;
417 #size-cells = <0>;
418 compatible = "samsung,s3c2440-i2c";
419 reg = <0x13860000 0x100>;
420 interrupts = <0 113 0>;
421 clocks = <&cmu CLK_I2C0>;
422 clock-names = "i2c";
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c0_bus>;
425 status = "disabled";
426 };
427
428 i2c_1: i2c@13870000 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "samsung,s3c2440-i2c";
432 reg = <0x13870000 0x100>;
433 interrupts = <0 114 0>;
434 clocks = <&cmu CLK_I2C1>;
435 clock-names = "i2c";
436 pinctrl-names = "default";
437 pinctrl-0 = <&i2c1_bus>;
438 status = "disabled";
439 };
440
441 i2c_2: i2c@13880000 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 compatible = "samsung,s3c2440-i2c";
445 reg = <0x13880000 0x100>;
446 interrupts = <0 115 0>;
447 clocks = <&cmu CLK_I2C2>;
448 clock-names = "i2c";
449 pinctrl-names = "default";
450 pinctrl-0 = <&i2c2_bus>;
451 status = "disabled";
452 };
453
454 i2c_3: i2c@13890000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "samsung,s3c2440-i2c";
458 reg = <0x13890000 0x100>;
459 interrupts = <0 116 0>;
460 clocks = <&cmu CLK_I2C3>;
461 clock-names = "i2c";
462 pinctrl-names = "default";
463 pinctrl-0 = <&i2c3_bus>;
464 status = "disabled";
465 };
466
467 i2c_4: i2c@138A0000 {
468 #address-cells = <1>;
469 #size-cells = <0>;
470 compatible = "samsung,s3c2440-i2c";
471 reg = <0x138A0000 0x100>;
472 interrupts = <0 117 0>;
473 clocks = <&cmu CLK_I2C4>;
474 clock-names = "i2c";
475 pinctrl-names = "default";
476 pinctrl-0 = <&i2c4_bus>;
477 status = "disabled";
478 };
479
480 i2c_5: i2c@138B0000 {
481 #address-cells = <1>;
482 #size-cells = <0>;
483 compatible = "samsung,s3c2440-i2c";
484 reg = <0x138B0000 0x100>;
485 interrupts = <0 118 0>;
486 clocks = <&cmu CLK_I2C5>;
487 clock-names = "i2c";
488 pinctrl-names = "default";
489 pinctrl-0 = <&i2c5_bus>;
490 status = "disabled";
491 };
492
493 i2c_6: i2c@138C0000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "samsung,s3c2440-i2c";
497 reg = <0x138C0000 0x100>;
498 interrupts = <0 119 0>;
499 clocks = <&cmu CLK_I2C6>;
500 clock-names = "i2c";
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2c6_bus>;
503 status = "disabled";
504 };
505
506 i2c_7: i2c@138D0000 {
507 #address-cells = <1>;
508 #size-cells = <0>;
509 compatible = "samsung,s3c2440-i2c";
510 reg = <0x138D0000 0x100>;
511 interrupts = <0 120 0>;
512 clocks = <&cmu CLK_I2C7>;
513 clock-names = "i2c";
514 pinctrl-names = "default";
515 pinctrl-0 = <&i2c7_bus>;
516 status = "disabled";
517 };
518
519 spi_0: spi@13920000 {
520 compatible = "samsung,exynos4210-spi";
521 reg = <0x13920000 0x100>;
522 interrupts = <0 121 0>;
523 dmas = <&pdma0 7>, <&pdma0 6>;
524 dma-names = "tx", "rx";
525 #address-cells = <1>;
526 #size-cells = <0>;
527 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
528 clock-names = "spi", "spi_busclk0";
529 samsung,spi-src-clk = <0>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&spi0_bus>;
532 status = "disabled";
533 };
534
535 spi_1: spi@13930000 {
536 compatible = "samsung,exynos4210-spi";
537 reg = <0x13930000 0x100>;
538 interrupts = <0 122 0>;
539 dmas = <&pdma1 7>, <&pdma1 6>;
540 dma-names = "tx", "rx";
541 #address-cells = <1>;
542 #size-cells = <0>;
543 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
544 clock-names = "spi", "spi_busclk0";
545 samsung,spi-src-clk = <0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&spi1_bus>;
548 status = "disabled";
549 };
550
551 spi_2: spi@13940000 {
552 compatible = "samsung,exynos4210-spi";
553 reg = <0x13940000 0x100>;
554 interrupts = <0 123 0>;
555 dmas = <&pdma0 9>, <&pdma0 8>;
556 dma-names = "tx", "rx";
557 #address-cells = <1>;
558 #size-cells = <0>;
559 clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
560 clock-names = "spi", "spi_busclk0";
561 samsung,spi-src-clk = <0>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&spi2_bus>;
564 status = "disabled";
565 };
566
567 clock_audss: clock-controller@03810000 {
568 compatible = "samsung,exynos4210-audss-clock";
569 reg = <0x03810000 0x0C>;
570 #clock-cells = <1>;
571 };
572
573 i2s0: i2s@3830000 {
574 compatible = "samsung,s5pv210-i2s";
575 reg = <0x03830000 0x100>;
576 interrupts = <0 124 0>;
577 clocks = <&clock_audss EXYNOS_I2S_BUS>,
578 <&clock_audss EXYNOS_SCLK_I2S>;
579 clock-names = "iis", "i2s_opclk0";
580 dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
581 dma-names = "tx", "rx", "tx-sec";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2s0_bus>;
584 samsung,idma-addr = <0x03000000>;
585 status = "disabled";
586 };
587
588 pwm: pwm@139D0000 {
589 compatible = "samsung,exynos4210-pwm";
590 reg = <0x139D0000 0x1000>;
591 interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
592 <0 107 0>, <0 108 0>;
593 #pwm-cells = <3>;
594 status = "disabled";
595 };
596
597 pmu {
598 compatible = "arm,cortex-a9-pmu";
599 interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
600 };
601 };
602};
603
604#include "exynos4415-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 0865a2e33f97..c141931378e7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -12,6 +12,22 @@
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13*/ 13*/
14 14
15#define PIN_PULL_NONE 0
16#define PIN_PULL_DOWN 1
17#define PIN_PULL_UP 3
18
19#define PIN_PDN_OUT0 0
20#define PIN_PDN_OUT1 1
21#define PIN_PDN_INPUT 2
22#define PIN_PDN_PREV 3
23
24#define PIN_SLP(_pin, _mode, _pull) \
25 _pin { \
26 samsung,pins = #_pin; \
27 samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \
28 samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \
29 }
30
15/ { 31/ {
16 pinctrl@11400000 { 32 pinctrl@11400000 {
17 gpa0: gpa0 { 33 gpa0: gpa0 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 861bb919f6d3..2e9f1f7be77b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -271,4 +271,14 @@
271 compatible = "samsung,exynos4x12-usb2-phy"; 271 compatible = "samsung,exynos4x12-usb2-phy";
272 samsung,sysreg-phandle = <&sys_reg>; 272 samsung,sysreg-phandle = <&sys_reg>;
273 }; 273 };
274
275 tmu@100C0000 {
276 compatible = "samsung,exynos4412-tmu";
277 interrupt-parent = <&combiner>;
278 interrupts = <2 4>;
279 reg = <0x100C0000 0x100>;
280 clocks = <&clock 383>;
281 clock-names = "tmu_apbif";
282 status = "disabled";
283 };
274}; 284};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3acd97eb6630..7e728a1b5559 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -7,12 +7,13 @@
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "exynos5250.dtsi" 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/input/input.h> 15#include <dt-bindings/input/input.h>
16#include "exynos5250.dtsi"
16 17
17/ { 18/ {
18 model = "Insignal Arndale evaluation board based on EXYNOS5250"; 19 model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -26,465 +27,52 @@
26 bootargs = "console=ttySAC2,115200"; 27 bootargs = "console=ttySAC2,115200";
27 }; 28 };
28 29
29 rtc@101E0000 {
30 status = "okay";
31 };
32
33 codec@11000000 {
34 samsung,mfc-r = <0x43000000 0x800000>;
35 samsung,mfc-l = <0x51000000 0x800000>;
36 };
37
38 i2c@12C60000 {
39 samsung,i2c-sda-delay = <100>;
40 samsung,i2c-max-bus-freq = <20000>;
41 samsung,i2c-slave-addr = <0x66>;
42 status = "okay";
43
44 s5m8767_pmic@66 {
45 compatible = "samsung,s5m8767-pmic";
46 reg = <0x66>;
47 interrupt-parent = <&gpx3>;
48 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
49
50 vinb1-supply = <&main_dc_reg>;
51 vinb2-supply = <&main_dc_reg>;
52 vinb3-supply = <&main_dc_reg>;
53 vinb4-supply = <&main_dc_reg>;
54 vinb5-supply = <&main_dc_reg>;
55 vinb6-supply = <&main_dc_reg>;
56 vinb7-supply = <&main_dc_reg>;
57 vinb8-supply = <&main_dc_reg>;
58 vinb9-supply = <&main_dc_reg>;
59
60 vinl1-supply = <&buck7_reg>;
61 vinl2-supply = <&buck7_reg>;
62 vinl3-supply = <&buck7_reg>;
63 vinl4-supply = <&main_dc_reg>;
64 vinl5-supply = <&main_dc_reg>;
65 vinl6-supply = <&main_dc_reg>;
66 vinl7-supply = <&main_dc_reg>;
67 vinl8-supply = <&buck8_reg>;
68 vinl9-supply = <&buck8_reg>;
69
70 s5m8767,pmic-buck2-dvs-voltage = <1300000>;
71 s5m8767,pmic-buck3-dvs-voltage = <1100000>;
72 s5m8767,pmic-buck4-dvs-voltage = <1200000>;
73 s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
74 <&gpd1 1 0>,
75 <&gpd1 2 0>;
76 s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
77 <&gpx2 4 0>,
78 <&gpx2 5 0>;
79 regulators {
80 ldo1_reg: LDO1 {
81 regulator-name = "VDD_ALIVE_1.0V";
82 regulator-min-microvolt = <1100000>;
83 regulator-max-microvolt = <1100000>;
84 regulator-always-on;
85 regulator-boot-on;
86 op_mode = <1>;
87 };
88
89 ldo2_reg: LDO2 {
90 regulator-name = "VDD_28IO_DP_1.35V";
91 regulator-min-microvolt = <1200000>;
92 regulator-max-microvolt = <1200000>;
93 regulator-always-on;
94 regulator-boot-on;
95 op_mode = <1>;
96 };
97
98 ldo3_reg: LDO3 {
99 regulator-name = "VDD_COMMON1_1.8V";
100 regulator-min-microvolt = <1800000>;
101 regulator-max-microvolt = <1800000>;
102 regulator-always-on;
103 regulator-boot-on;
104 op_mode = <1>;
105 };
106
107 ldo4_reg: LDO4 {
108 regulator-name = "VDD_IOPERI_1.8V";
109 regulator-min-microvolt = <1800000>;
110 regulator-max-microvolt = <1800000>;
111 regulator-always-on;
112 op_mode = <1>;
113 };
114
115 ldo5_reg: LDO5 {
116 regulator-name = "VDD_EXT_1.8V";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119 regulator-always-on;
120 regulator-boot-on;
121 op_mode = <1>;
122 };
123
124 ldo6_reg: LDO6 {
125 regulator-name = "VDD_MPLL_1.1V";
126 regulator-min-microvolt = <1100000>;
127 regulator-max-microvolt = <1100000>;
128 regulator-always-on;
129 regulator-boot-on;
130 op_mode = <1>;
131 };
132
133 ldo7_reg: LDO7 {
134 regulator-name = "VDD_XPLL_1.1V";
135 regulator-min-microvolt = <1100000>;
136 regulator-max-microvolt = <1100000>;
137 regulator-always-on;
138 regulator-boot-on;
139 op_mode = <1>;
140 };
141
142 ldo8_reg: LDO8 {
143 regulator-name = "VDD_COMMON2_1.0V";
144 regulator-min-microvolt = <1000000>;
145 regulator-max-microvolt = <1000000>;
146 regulator-always-on;
147 regulator-boot-on;
148 op_mode = <1>;
149 };
150
151 ldo9_reg: LDO9 {
152 regulator-name = "VDD_33ON_3.0V";
153 regulator-min-microvolt = <3000000>;
154 regulator-max-microvolt = <3000000>;
155 op_mode = <1>;
156 };
157
158 ldo10_reg: LDO10 {
159 regulator-name = "VDD_COMMON3_1.8V";
160 regulator-min-microvolt = <1800000>;
161 regulator-max-microvolt = <1800000>;
162 regulator-always-on;
163 regulator-boot-on;
164 op_mode = <1>;
165 };
166
167 ldo11_reg: LDO11 {
168 regulator-name = "VDD_ABB2_1.8V";
169 regulator-min-microvolt = <1800000>;
170 regulator-max-microvolt = <1800000>;
171 regulator-always-on;
172 regulator-boot-on;
173 op_mode = <1>;
174 };
175
176 ldo12_reg: LDO12 {
177 regulator-name = "VDD_USB_3.0V";
178 regulator-min-microvolt = <3000000>;
179 regulator-max-microvolt = <3000000>;
180 regulator-always-on;
181 regulator-boot-on;
182 op_mode = <1>;
183 };
184
185 ldo13_reg: LDO13 {
186 regulator-name = "VDDQ_C2C_W_1.8V";
187 regulator-min-microvolt = <1800000>;
188 regulator-max-microvolt = <1800000>;
189 regulator-always-on;
190 regulator-boot-on;
191 op_mode = <1>;
192 };
193
194 ldo14_reg: LDO14 {
195 regulator-name = "VDD18_ABB0_3_1.8V";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <1800000>;
198 regulator-always-on;
199 regulator-boot-on;
200 op_mode = <1>;
201 };
202
203 ldo15_reg: LDO15 {
204 regulator-name = "VDD10_COMMON4_1.0V";
205 regulator-min-microvolt = <1000000>;
206 regulator-max-microvolt = <1000000>;
207 regulator-always-on;
208 regulator-boot-on;
209 op_mode = <1>;
210 };
211
212 ldo16_reg: LDO16 {
213 regulator-name = "VDD18_HSIC_1.8V";
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <1800000>;
216 regulator-always-on;
217 regulator-boot-on;
218 op_mode = <1>;
219 };
220
221 ldo17_reg: LDO17 {
222 regulator-name = "VDDQ_MMC2_3_2.8V";
223 regulator-min-microvolt = <2800000>;
224 regulator-max-microvolt = <2800000>;
225 regulator-always-on;
226 regulator-boot-on;
227 op_mode = <1>;
228 };
229
230 ldo18_reg: LDO18 {
231 regulator-name = "VDD_33ON_2.8V";
232 regulator-min-microvolt = <2800000>;
233 regulator-max-microvolt = <2800000>;
234 op_mode = <1>;
235 };
236
237 ldo22_reg: LDO22 {
238 regulator-name = "EXT_33_OFF";
239 regulator-min-microvolt = <3300000>;
240 regulator-max-microvolt = <3300000>;
241 op_mode = <1>;
242 };
243
244 ldo23_reg: LDO23 {
245 regulator-name = "EXT_28_OFF";
246 regulator-min-microvolt = <2800000>;
247 regulator-max-microvolt = <2800000>;
248 op_mode = <1>;
249 };
250
251 ldo25_reg: LDO25 {
252 regulator-name = "PVDD_LDO25";
253 regulator-min-microvolt = <1200000>;
254 regulator-max-microvolt = <1200000>;
255 op_mode = <1>;
256 };
257
258 ldo26_reg: LDO26 {
259 regulator-name = "EXT_18_OFF";
260 regulator-min-microvolt = <1800000>;
261 regulator-max-microvolt = <1800000>;
262 op_mode = <1>;
263 };
264
265 buck1_reg: BUCK1 {
266 regulator-name = "vdd_mif";
267 regulator-min-microvolt = <950000>;
268 regulator-max-microvolt = <1200000>;
269 regulator-always-on;
270 regulator-boot-on;
271 op_mode = <1>;
272 };
273
274 buck2_reg: BUCK2 {
275 regulator-name = "vdd_arm";
276 regulator-min-microvolt = <912500>;
277 regulator-max-microvolt = <1300000>;
278 regulator-always-on;
279 regulator-boot-on;
280 op_mode = <1>;
281 };
282
283 buck3_reg: BUCK3 {
284 regulator-name = "vdd_int";
285 regulator-min-microvolt = <900000>;
286 regulator-max-microvolt = <1200000>;
287 regulator-always-on;
288 regulator-boot-on;
289 op_mode = <1>;
290 };
291
292 buck4_reg: BUCK4 {
293 regulator-name = "vdd_g3d";
294 regulator-min-microvolt = <1000000>;
295 regulator-max-microvolt = <1000000>;
296 regulator-always-on;
297 regulator-boot-on;
298 op_mode = <1>;
299 };
300
301 buck5_reg: BUCK5 {
302 regulator-name = "VDD_MEM_1.35V";
303 regulator-min-microvolt = <750000>;
304 regulator-max-microvolt = <1355000>;
305 regulator-always-on;
306 regulator-boot-on;
307 op_mode = <1>;
308 };
309
310 buck7_reg: BUCK7 {
311 regulator-name = "PVDD_BUCK7";
312 regulator-always-on;
313 op_mode = <1>;
314 };
315
316 buck8_reg: BUCK8 {
317 regulator-name = "PVDD_BUCK8";
318 regulator-always-on;
319 op_mode = <1>;
320 };
321
322 buck9_reg: BUCK9 {
323 regulator-name = "VDD_33_OFF_EXT1";
324 regulator-min-microvolt = <750000>;
325 regulator-max-microvolt = <3000000>;
326 op_mode = <1>;
327 };
328 };
329 };
330 };
331
332 i2c@12C80000 {
333 status = "okay";
334
335 samsung,i2c-sda-delay = <100>;
336 samsung,i2c-max-bus-freq = <66000>;
337 samsung,i2c-slave-addr = <0x50>;
338
339 hdmiddc@50 {
340 compatible = "samsung,exynos4210-hdmiddc";
341 reg = <0x50>;
342 };
343 };
344
345 i2c@12C90000 {
346 status = "okay";
347
348 wm1811a@1a {
349
350 compatible = "wlf,wm1811";
351 reg = <0x1a>;
352
353 AVDD2-supply = <&main_dc_reg>;
354 CPVDD-supply = <&main_dc_reg>;
355 DBVDD1-supply = <&main_dc_reg>;
356 DBVDD2-supply = <&main_dc_reg>;
357 DBVDD3-supply = <&main_dc_reg>;
358 LDO1VDD-supply = <&main_dc_reg>;
359 SPKVDD1-supply = <&main_dc_reg>;
360 SPKVDD2-supply = <&main_dc_reg>;
361
362 wlf,ldo1ena = <&gpb0 0 0>;
363 wlf,ldo2ena = <&gpb0 1 0>;
364 };
365 };
366
367 i2c@12CE0000 {
368 status = "okay";
369
370 samsung,i2c-sda-delay = <100>;
371 samsung,i2c-max-bus-freq = <66000>;
372 samsung,i2c-slave-addr = <0x38>;
373
374 hdmiphy@38 {
375 compatible = "samsung,exynos4212-hdmiphy";
376 reg = <0x38>;
377 };
378 };
379
380 i2c@121D0000 {
381 status = "okay";
382 samsung,i2c-sda-delay = <100>;
383 samsung,i2c-max-bus-freq = <40000>;
384 samsung,i2c-slave-addr = <0x38>;
385
386 sata_phy_i2c:sata-phy@38 {
387 compatible = "samsung,exynos-sataphy-i2c";
388 reg = <0x38>;
389 };
390 };
391
392 sata@122F0000 {
393 status = "okay";
394 };
395
396 sata-phy@12170000 {
397 status = "okay";
398 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
399 };
400
401 mmc_0: mmc@12200000 {
402 status = "okay";
403 num-slots = <1>;
404 broken-cd;
405 card-detect-delay = <200>;
406 samsung,dw-mshc-ciu-div = <3>;
407 samsung,dw-mshc-sdr-timing = <2 3>;
408 samsung,dw-mshc-ddr-timing = <1 2>;
409 vmmc-supply = <&mmc_reg>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
412 bus-width = <8>;
413 cap-mmc-highspeed;
414 };
415
416 mmc_2: mmc@12220000 {
417 status = "okay";
418 num-slots = <1>;
419 card-detect-delay = <200>;
420 samsung,dw-mshc-ciu-div = <3>;
421 samsung,dw-mshc-sdr-timing = <2 3>;
422 samsung,dw-mshc-ddr-timing = <1 2>;
423 vmmc-supply = <&mmc_reg>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
426 bus-width = <4>;
427 disable-wp;
428 cap-sd-highspeed;
429 };
430
431 i2s0: i2s@03830000 {
432 status = "okay";
433 };
434
435 gpio_keys { 30 gpio_keys {
436 compatible = "gpio-keys"; 31 compatible = "gpio-keys";
437 32
438 menu { 33 menu {
439 label = "SW-TACT2"; 34 label = "SW-TACT2";
440 gpios = <&gpx1 4 1>; 35 gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
441 linux,code = <KEY_MENU>; 36 linux,code = <KEY_MENU>;
442 gpio-key,wakeup; 37 gpio-key,wakeup;
443 }; 38 };
444 39
445 home { 40 home {
446 label = "SW-TACT3"; 41 label = "SW-TACT3";
447 gpios = <&gpx1 5 1>; 42 gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
448 linux,code = <KEY_HOME>; 43 linux,code = <KEY_HOME>;
449 gpio-key,wakeup; 44 gpio-key,wakeup;
450 }; 45 };
451 46
452 up { 47 up {
453 label = "SW-TACT4"; 48 label = "SW-TACT4";
454 gpios = <&gpx1 6 1>; 49 gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
455 linux,code = <KEY_UP>; 50 linux,code = <KEY_UP>;
456 gpio-key,wakeup; 51 gpio-key,wakeup;
457 }; 52 };
458 53
459 down { 54 down {
460 label = "SW-TACT5"; 55 label = "SW-TACT5";
461 gpios = <&gpx1 7 1>; 56 gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
462 linux,code = <KEY_DOWN>; 57 linux,code = <KEY_DOWN>;
463 gpio-key,wakeup; 58 gpio-key,wakeup;
464 }; 59 };
465 60
466 back { 61 back {
467 label = "SW-TACT6"; 62 label = "SW-TACT6";
468 gpios = <&gpx2 0 1>; 63 gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
469 linux,code = <KEY_BACK>; 64 linux,code = <KEY_BACK>;
470 gpio-key,wakeup; 65 gpio-key,wakeup;
471 }; 66 };
472 67
473 wakeup { 68 wakeup {
474 label = "SW-TACT7"; 69 label = "SW-TACT7";
475 gpios = <&gpx2 1 1>; 70 gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
476 linux,code = <KEY_WAKEUP>; 71 linux,code = <KEY_WAKEUP>;
477 gpio-key,wakeup; 72 gpio-key,wakeup;
478 }; 73 };
479 }; 74 };
480 75
481 hdmi {
482 hpd-gpio = <&gpx3 7 2>;
483 vdd_osc-supply = <&ldo10_reg>;
484 vdd_pll-supply = <&ldo8_reg>;
485 vdd-supply = <&ldo8_reg>;
486 };
487
488 regulators { 76 regulators {
489 compatible = "simple-bus"; 77 compatible = "simple-bus";
490 #address-cells = <1>; 78 #address-cells = <1>;
@@ -502,7 +90,7 @@
502 regulator-name = "VDD_33ON_2.8V"; 90 regulator-name = "VDD_33ON_2.8V";
503 regulator-min-microvolt = <2800000>; 91 regulator-min-microvolt = <2800000>;
504 regulator-max-microvolt = <2800000>; 92 regulator-max-microvolt = <2800000>;
505 gpio = <&gpx1 1 1>; 93 gpio = <&gpx1 1 GPIO_ACTIVE_LOW>;
506 enable-active-high; 94 enable-active-high;
507 }; 95 };
508 96
@@ -520,46 +108,455 @@
520 }; 108 };
521 }; 109 };
522 110
523 dp-controller@145B0000 { 111 // SMSC USB3503 connected in hardware only mode as a PHY
524 samsung,color-space = <0>; 112 usb_hub: usb-hub {
525 samsung,dynamic-range = <0>; 113 compatible = "smsc,usb3503a";
526 samsung,ycbcr-coeff = <0>; 114
527 samsung,color-depth = <1>; 115 reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
528 samsung,link-rate = <0x0a>; 116 connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>;
529 samsung,lane-count = <4>;
530 status = "okay";
531 }; 117 };
118};
532 119
533 fimd: fimd@14400000 { 120&dp {
534 status = "okay"; 121 status = "okay";
535 display-timings { 122 samsung,color-space = <0>;
536 native-mode = <&timing0>; 123 samsung,dynamic-range = <0>;
537 timing0: timing@0 { 124 samsung,ycbcr-coeff = <0>;
538 /* 2560x1600 DP panel */ 125 samsung,color-depth = <1>;
539 clock-frequency = <50000>; 126 samsung,link-rate = <0x0a>;
540 hactive = <2560>; 127 samsung,lane-count = <4>;
541 vactive = <1600>; 128};
542 hfront-porch = <48>; 129
543 hback-porch = <80>; 130&fimd {
544 hsync-len = <32>; 131 status = "okay";
545 vback-porch = <16>; 132
546 vfront-porch = <8>; 133 display-timings {
547 vsync-len = <6>; 134 native-mode = <&timing0>;
548 }; 135
136 timing0: timing@0 {
137 /* 2560x1600 DP panel */
138 clock-frequency = <50000>;
139 hactive = <2560>;
140 vactive = <1600>;
141 hfront-porch = <48>;
142 hback-porch = <80>;
143 hsync-len = <32>;
144 vback-porch = <16>;
145 vfront-porch = <8>;
146 vsync-len = <6>;
549 }; 147 };
550 }; 148 };
149};
551 150
552 usb_hub_bus { 151&hdmi {
553 compatible = "simple-bus"; 152 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>;
554 #address-cells = <1>; 153 vdd_osc-supply = <&ldo10_reg>;
555 #size-cells = <0>; 154 vdd_pll-supply = <&ldo8_reg>;
155 vdd-supply = <&ldo8_reg>;
156};
157
158&i2c_0 {
159 status = "okay";
160 samsung,i2c-sda-delay = <100>;
161 samsung,i2c-max-bus-freq = <20000>;
162 samsung,i2c-slave-addr = <0x66>;
163
164 s5m8767_pmic@66 {
165 compatible = "samsung,s5m8767-pmic";
166 reg = <0x66>;
167 interrupt-parent = <&gpx3>;
168 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
169
170 vinb1-supply = <&main_dc_reg>;
171 vinb2-supply = <&main_dc_reg>;
172 vinb3-supply = <&main_dc_reg>;
173 vinb4-supply = <&main_dc_reg>;
174 vinb5-supply = <&main_dc_reg>;
175 vinb6-supply = <&main_dc_reg>;
176 vinb7-supply = <&main_dc_reg>;
177 vinb8-supply = <&main_dc_reg>;
178 vinb9-supply = <&main_dc_reg>;
179
180 vinl1-supply = <&buck7_reg>;
181 vinl2-supply = <&buck7_reg>;
182 vinl3-supply = <&buck7_reg>;
183 vinl4-supply = <&main_dc_reg>;
184 vinl5-supply = <&main_dc_reg>;
185 vinl6-supply = <&main_dc_reg>;
186 vinl7-supply = <&main_dc_reg>;
187 vinl8-supply = <&buck8_reg>;
188 vinl9-supply = <&buck8_reg>;
189
190 s5m8767,pmic-buck2-dvs-voltage = <1300000>;
191 s5m8767,pmic-buck3-dvs-voltage = <1100000>;
192 s5m8767,pmic-buck4-dvs-voltage = <1200000>;
193 s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
194 <&gpd1 1 GPIO_ACTIVE_HIGH>,
195 <&gpd1 2 GPIO_ACTIVE_HIGH>;
196 s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
197 <&gpx2 4 GPIO_ACTIVE_HIGH>,
198 <&gpx2 5 GPIO_ACTIVE_HIGH>;
199
200 regulators {
201 ldo1_reg: LDO1 {
202 regulator-name = "VDD_ALIVE_1.0V";
203 regulator-min-microvolt = <1100000>;
204 regulator-max-microvolt = <1100000>;
205 regulator-always-on;
206 regulator-boot-on;
207 op_mode = <1>;
208 };
556 209
557 // SMSC USB3503 connected in hardware only mode as a PHY 210 ldo2_reg: LDO2 {
558 usb_hub: usb_hub { 211 regulator-name = "VDD_28IO_DP_1.35V";
559 compatible = "smsc,usb3503a"; 212 regulator-min-microvolt = <1200000>;
213 regulator-max-microvolt = <1200000>;
214 regulator-always-on;
215 regulator-boot-on;
216 op_mode = <1>;
217 };
218
219 ldo3_reg: LDO3 {
220 regulator-name = "VDD_COMMON1_1.8V";
221 regulator-min-microvolt = <1800000>;
222 regulator-max-microvolt = <1800000>;
223 regulator-always-on;
224 regulator-boot-on;
225 op_mode = <1>;
226 };
227
228 ldo4_reg: LDO4 {
229 regulator-name = "VDD_IOPERI_1.8V";
230 regulator-min-microvolt = <1800000>;
231 regulator-max-microvolt = <1800000>;
232 regulator-always-on;
233 op_mode = <1>;
234 };
235
236 ldo5_reg: LDO5 {
237 regulator-name = "VDD_EXT_1.8V";
238 regulator-min-microvolt = <1800000>;
239 regulator-max-microvolt = <1800000>;
240 regulator-always-on;
241 regulator-boot-on;
242 op_mode = <1>;
243 };
244
245 ldo6_reg: LDO6 {
246 regulator-name = "VDD_MPLL_1.1V";
247 regulator-min-microvolt = <1100000>;
248 regulator-max-microvolt = <1100000>;
249 regulator-always-on;
250 regulator-boot-on;
251 op_mode = <1>;
252 };
560 253
561 reset-gpios = <&gpx3 5 1>; 254 ldo7_reg: LDO7 {
562 connect-gpios = <&gpd1 7 1>; 255 regulator-name = "VDD_XPLL_1.1V";
256 regulator-min-microvolt = <1100000>;
257 regulator-max-microvolt = <1100000>;
258 regulator-always-on;
259 regulator-boot-on;
260 op_mode = <1>;
261 };
262
263 ldo8_reg: LDO8 {
264 regulator-name = "VDD_COMMON2_1.0V";
265 regulator-min-microvolt = <1000000>;
266 regulator-max-microvolt = <1000000>;
267 regulator-always-on;
268 regulator-boot-on;
269 op_mode = <1>;
270 };
271
272 ldo9_reg: LDO9 {
273 regulator-name = "VDD_33ON_3.0V";
274 regulator-min-microvolt = <3000000>;
275 regulator-max-microvolt = <3000000>;
276 op_mode = <1>;
277 };
278
279 ldo10_reg: LDO10 {
280 regulator-name = "VDD_COMMON3_1.8V";
281 regulator-min-microvolt = <1800000>;
282 regulator-max-microvolt = <1800000>;
283 regulator-always-on;
284 regulator-boot-on;
285 op_mode = <1>;
286 };
287
288 ldo11_reg: LDO11 {
289 regulator-name = "VDD_ABB2_1.8V";
290 regulator-min-microvolt = <1800000>;
291 regulator-max-microvolt = <1800000>;
292 regulator-always-on;
293 regulator-boot-on;
294 op_mode = <1>;
295 };
296
297 ldo12_reg: LDO12 {
298 regulator-name = "VDD_USB_3.0V";
299 regulator-min-microvolt = <3000000>;
300 regulator-max-microvolt = <3000000>;
301 regulator-always-on;
302 regulator-boot-on;
303 op_mode = <1>;
304 };
305
306 ldo13_reg: LDO13 {
307 regulator-name = "VDDQ_C2C_W_1.8V";
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-always-on;
311 regulator-boot-on;
312 op_mode = <1>;
313 };
314
315 ldo14_reg: LDO14 {
316 regulator-name = "VDD18_ABB0_3_1.8V";
317 regulator-min-microvolt = <1800000>;
318 regulator-max-microvolt = <1800000>;
319 regulator-always-on;
320 regulator-boot-on;
321 op_mode = <1>;
322 };
323
324 ldo15_reg: LDO15 {
325 regulator-name = "VDD10_COMMON4_1.0V";
326 regulator-min-microvolt = <1000000>;
327 regulator-max-microvolt = <1000000>;
328 regulator-always-on;
329 regulator-boot-on;
330 op_mode = <1>;
331 };
332
333 ldo16_reg: LDO16 {
334 regulator-name = "VDD18_HSIC_1.8V";
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <1800000>;
337 regulator-always-on;
338 regulator-boot-on;
339 op_mode = <1>;
340 };
341
342 ldo17_reg: LDO17 {
343 regulator-name = "VDDQ_MMC2_3_2.8V";
344 regulator-min-microvolt = <2800000>;
345 regulator-max-microvolt = <2800000>;
346 regulator-always-on;
347 regulator-boot-on;
348 op_mode = <1>;
349 };
350
351 ldo18_reg: LDO18 {
352 regulator-name = "VDD_33ON_2.8V";
353 regulator-min-microvolt = <2800000>;
354 regulator-max-microvolt = <2800000>;
355 op_mode = <1>;
356 };
357
358 ldo22_reg: LDO22 {
359 regulator-name = "EXT_33_OFF";
360 regulator-min-microvolt = <3300000>;
361 regulator-max-microvolt = <3300000>;
362 op_mode = <1>;
363 };
364
365 ldo23_reg: LDO23 {
366 regulator-name = "EXT_28_OFF";
367 regulator-min-microvolt = <2800000>;
368 regulator-max-microvolt = <2800000>;
369 op_mode = <1>;
370 };
371
372 ldo25_reg: LDO25 {
373 regulator-name = "PVDD_LDO25";
374 regulator-min-microvolt = <1200000>;
375 regulator-max-microvolt = <1200000>;
376 op_mode = <1>;
377 };
378
379 ldo26_reg: LDO26 {
380 regulator-name = "EXT_18_OFF";
381 regulator-min-microvolt = <1800000>;
382 regulator-max-microvolt = <1800000>;
383 op_mode = <1>;
384 };
385
386 buck1_reg: BUCK1 {
387 regulator-name = "vdd_mif";
388 regulator-min-microvolt = <950000>;
389 regulator-max-microvolt = <1200000>;
390 regulator-always-on;
391 regulator-boot-on;
392 op_mode = <1>;
393 };
394
395 buck2_reg: BUCK2 {
396 regulator-name = "vdd_arm";
397 regulator-min-microvolt = <912500>;
398 regulator-max-microvolt = <1300000>;
399 regulator-always-on;
400 regulator-boot-on;
401 op_mode = <1>;
402 };
403
404 buck3_reg: BUCK3 {
405 regulator-name = "vdd_int";
406 regulator-min-microvolt = <900000>;
407 regulator-max-microvolt = <1200000>;
408 regulator-always-on;
409 regulator-boot-on;
410 op_mode = <1>;
411 };
412
413 buck4_reg: BUCK4 {
414 regulator-name = "vdd_g3d";
415 regulator-min-microvolt = <1000000>;
416 regulator-max-microvolt = <1000000>;
417 regulator-always-on;
418 regulator-boot-on;
419 op_mode = <1>;
420 };
421
422 buck5_reg: BUCK5 {
423 regulator-name = "VDD_MEM_1.35V";
424 regulator-min-microvolt = <750000>;
425 regulator-max-microvolt = <1355000>;
426 regulator-always-on;
427 regulator-boot-on;
428 op_mode = <1>;
429 };
430
431 buck7_reg: BUCK7 {
432 regulator-name = "PVDD_BUCK7";
433 regulator-always-on;
434 op_mode = <1>;
435 };
436
437 buck8_reg: BUCK8 {
438 regulator-name = "PVDD_BUCK8";
439 regulator-always-on;
440 op_mode = <1>;
441 };
442
443 buck9_reg: BUCK9 {
444 regulator-name = "VDD_33_OFF_EXT1";
445 regulator-min-microvolt = <750000>;
446 regulator-max-microvolt = <3000000>;
447 op_mode = <1>;
448 };
563 }; 449 };
564 }; 450 };
565}; 451};
452
453&i2c_2 {
454 status = "okay";
455
456 samsung,i2c-sda-delay = <100>;
457 samsung,i2c-max-bus-freq = <66000>;
458 samsung,i2c-slave-addr = <0x50>;
459
460 hdmiddc@50 {
461 compatible = "samsung,exynos4210-hdmiddc";
462 reg = <0x50>;
463 };
464};
465
466&i2c_3 {
467 status = "okay";
468
469 wm1811a@1a {
470 compatible = "wlf,wm1811";
471 reg = <0x1a>;
472
473 AVDD2-supply = <&main_dc_reg>;
474 CPVDD-supply = <&main_dc_reg>;
475 DBVDD1-supply = <&main_dc_reg>;
476 DBVDD2-supply = <&main_dc_reg>;
477 DBVDD3-supply = <&main_dc_reg>;
478 LDO1VDD-supply = <&main_dc_reg>;
479 SPKVDD1-supply = <&main_dc_reg>;
480 SPKVDD2-supply = <&main_dc_reg>;
481
482 wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>;
483 wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>;
484 };
485};
486
487&i2c_8 {
488 status = "okay";
489
490 samsung,i2c-sda-delay = <100>;
491 samsung,i2c-max-bus-freq = <66000>;
492 samsung,i2c-slave-addr = <0x38>;
493
494 hdmiphy@38 {
495 compatible = "samsung,exynos4212-hdmiphy";
496 reg = <0x38>;
497 };
498};
499
500&i2c_9 {
501 status = "okay";
502 samsung,i2c-sda-delay = <100>;
503 samsung,i2c-max-bus-freq = <40000>;
504 samsung,i2c-slave-addr = <0x38>;
505
506 sata_phy_i2c:sata-phy@38 {
507 compatible = "samsung,exynos-sataphy-i2c";
508 reg = <0x38>;
509 };
510};
511
512&i2s0 {
513 status = "okay";
514};
515
516&mfc {
517 samsung,mfc-r = <0x43000000 0x800000>;
518 samsung,mfc-l = <0x51000000 0x800000>;
519};
520
521&mmc_0 {
522 status = "okay";
523 num-slots = <1>;
524 broken-cd;
525 card-detect-delay = <200>;
526 samsung,dw-mshc-ciu-div = <3>;
527 samsung,dw-mshc-sdr-timing = <2 3>;
528 samsung,dw-mshc-ddr-timing = <1 2>;
529 vmmc-supply = <&mmc_reg>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
532 bus-width = <8>;
533 cap-mmc-highspeed;
534};
535
536&mmc_2 {
537 status = "okay";
538 num-slots = <1>;
539 card-detect-delay = <200>;
540 samsung,dw-mshc-ciu-div = <3>;
541 samsung,dw-mshc-sdr-timing = <2 3>;
542 samsung,dw-mshc-ddr-timing = <1 2>;
543 vmmc-supply = <&mmc_reg>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
546 bus-width = <4>;
547 disable-wp;
548 cap-sd-highspeed;
549};
550
551&rtc {
552 status = "okay";
553};
554
555&sata {
556 status = "okay";
557};
558
559&sata_phy {
560 status = "okay";
561 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
562};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6a0f4c0ff763..bc27cc2558fe 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -7,9 +7,11 @@
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
13#include "exynos5250.dtsi" 15#include "exynos5250.dtsi"
14 16
15/ { 17/ {
@@ -27,165 +29,6 @@
27 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; 29 bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
28 }; 30 };
29 31
30 rtc@101E0000 {
31 status = "okay";
32 };
33
34 i2c@12C60000 {
35 samsung,i2c-sda-delay = <100>;
36 samsung,i2c-max-bus-freq = <20000>;
37 status = "okay";
38
39 eeprom@50 {
40 compatible = "samsung,s524ad0xd1";
41 reg = <0x50>;
42 };
43
44 max77686@09 {
45 compatible = "maxim,max77686";
46 reg = <0x09>;
47 interrupt-parent = <&gpx3>;
48 interrupts = <2 0>;
49
50 voltage-regulators {
51 ldo1_reg: LDO1 {
52 regulator-name = "P1.0V_LDO_OUT1";
53 regulator-min-microvolt = <1000000>;
54 regulator-max-microvolt = <1000000>;
55 regulator-always-on;
56 };
57
58 ldo2_reg: LDO2 {
59 regulator-name = "P1.2V_LDO_OUT2";
60 regulator-min-microvolt = <1200000>;
61 regulator-max-microvolt = <1200000>;
62 regulator-always-on;
63 };
64
65 ldo3_reg: LDO3 {
66 regulator-name = "P1.8V_LDO_OUT3";
67 regulator-min-microvolt = <1800000>;
68 regulator-max-microvolt = <1800000>;
69 regulator-always-on;
70 };
71
72 ldo4_reg: LDO4 {
73 regulator-name = "P2.8V_LDO_OUT4";
74 regulator-min-microvolt = <2800000>;
75 regulator-max-microvolt = <2800000>;
76 };
77
78 ldo5_reg: LDO5 {
79 regulator-name = "P1.8V_LDO_OUT5";
80 regulator-min-microvolt = <1800000>;
81 regulator-max-microvolt = <1800000>;
82 };
83
84 ldo6_reg: LDO6 {
85 regulator-name = "P1.1V_LDO_OUT6";
86 regulator-min-microvolt = <1100000>;
87 regulator-max-microvolt = <1100000>;
88 regulator-always-on;
89 };
90
91 ldo7_reg: LDO7 {
92 regulator-name = "P1.1V_LDO_OUT7";
93 regulator-min-microvolt = <1100000>;
94 regulator-max-microvolt = <1100000>;
95 regulator-always-on;
96 };
97
98 ldo8_reg: LDO8 {
99 regulator-name = "P1.0V_LDO_OUT8";
100 regulator-min-microvolt = <1000000>;
101 regulator-max-microvolt = <1000000>;
102 };
103
104 ldo10_reg: LDO10 {
105 regulator-name = "P1.8V_LDO_OUT10";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 };
109
110 ldo11_reg: LDO11 {
111 regulator-name = "P1.8V_LDO_OUT11";
112 regulator-min-microvolt = <1800000>;
113 regulator-max-microvolt = <1800000>;
114 };
115
116 ldo12_reg: LDO12 {
117 regulator-name = "P3.0V_LDO_OUT12";
118 regulator-min-microvolt = <3000000>;
119 regulator-max-microvolt = <3000000>;
120 };
121
122 ldo13_reg: LDO13 {
123 regulator-name = "P1.8V_LDO_OUT13";
124 regulator-min-microvolt = <1800000>;
125 regulator-max-microvolt = <1800000>;
126 };
127
128 ldo14_reg: LDO14 {
129 regulator-name = "P1.8V_LDO_OUT14";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <1800000>;
132 };
133
134 ldo15_reg: LDO15 {
135 regulator-name = "P1.0V_LDO_OUT15";
136 regulator-min-microvolt = <1000000>;
137 regulator-max-microvolt = <1000000>;
138 };
139
140 ldo16_reg: LDO16 {
141 regulator-name = "P1.8V_LDO_OUT16";
142 regulator-min-microvolt = <1800000>;
143 regulator-max-microvolt = <1800000>;
144 };
145
146 buck1_reg: BUCK1 {
147 regulator-name = "vdd_mif";
148 regulator-min-microvolt = <950000>;
149 regulator-max-microvolt = <1300000>;
150 regulator-always-on;
151 regulator-boot-on;
152 };
153
154 buck2_reg: BUCK2 {
155 regulator-name = "vdd_arm";
156 regulator-min-microvolt = <850000>;
157 regulator-max-microvolt = <1350000>;
158 regulator-always-on;
159 regulator-boot-on;
160 };
161
162 buck3_reg: BUCK3 {
163 regulator-name = "vdd_int";
164 regulator-min-microvolt = <900000>;
165 regulator-max-microvolt = <1200000>;
166 regulator-always-on;
167 regulator-boot-on;
168 };
169
170 buck4_reg: BUCK4 {
171 regulator-name = "vdd_g3d";
172 regulator-min-microvolt = <850000>;
173 regulator-max-microvolt = <1300000>;
174 regulator-always-on;
175 regulator-boot-on;
176 };
177
178 buck5_reg: BUCK5 {
179 regulator-name = "P1.8V_BUCK_OUT5";
180 regulator-min-microvolt = <1800000>;
181 regulator-max-microvolt = <1800000>;
182 regulator-always-on;
183 regulator-boot-on;
184 };
185 };
186 };
187 };
188
189 vdd: fixed-regulator@0 { 32 vdd: fixed-regulator@0 {
190 compatible = "regulator-fixed"; 33 compatible = "regulator-fixed";
191 regulator-name = "vdd-supply"; 34 regulator-name = "vdd-supply";
@@ -210,199 +53,360 @@
210 regulator-always-on; 53 regulator-always-on;
211 }; 54 };
212 55
213 i2c@12C70000 { 56 sound {
214 samsung,i2c-sda-delay = <100>; 57 compatible = "samsung,smdk-wm8994";
215 samsung,i2c-max-bus-freq = <20000>;
216 status = "okay";
217 58
218 eeprom@51 { 59 samsung,i2s-controller = <&i2s0>;
219 compatible = "samsung,s524ad0xd1"; 60 samsung,audio-codec = <&wm8994>;
220 reg = <0x51>; 61 };
62
63 fixed-rate-clocks {
64 xxti {
65 compatible = "samsung,clock-xxti";
66 clock-frequency = <24000000>;
221 }; 67 };
222 68
223 wm8994: wm8994@1a { 69 codec_mclk: codec-mclk {
224 compatible = "wlf,wm8994"; 70 compatible = "fixed-clock";
225 reg = <0x1a>; 71 #clock-cells = <0>;
72 clock-frequency = <16934000>;
73 };
74 };
75};
226 76
227 gpio-controller; 77&dp {
228 #gpio-cells = <2>; 78 samsung,color-space = <0>;
79 samsung,dynamic-range = <0>;
80 samsung,ycbcr-coeff = <0>;
81 samsung,color-depth = <1>;
82 samsung,link-rate = <0x0a>;
83 samsung,lane-count = <4>;
84
85 pinctrl-names = "default";
86 pinctrl-0 = <&dp_hpd>;
87 status = "okay";
88};
229 89
230 clocks = <&codec_mclk>; 90&ehci {
231 clock-names = "MCLK1"; 91 samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
92};
232 93
233 AVDD2-supply = <&vdd>; 94&fimd {
234 CPVDD-supply = <&vdd>; 95 status = "okay";
235 DBVDD-supply = <&dbvdd>; 96
236 SPKVDD1-supply = <&spkvdd>; 97 display-timings {
237 SPKVDD2-supply = <&spkvdd>; 98 native-mode = <&timing0>;
99
100 timing0: timing@0 {
101 /* 1280x800 */
102 clock-frequency = <50000>;
103 hactive = <1280>;
104 vactive = <800>;
105 hfront-porch = <4>;
106 hback-porch = <4>;
107 hsync-len = <4>;
108 vback-porch = <4>;
109 vfront-porch = <4>;
110 vsync-len = <4>;
238 }; 111 };
239 }; 112 };
113};
240 114
241 i2c@121D0000 { 115&hdmi {
242 samsung,i2c-sda-delay = <100>; 116 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
243 samsung,i2c-max-bus-freq = <40000>; 117};
244 samsung,i2c-slave-addr = <0x38>;
245 status = "okay";
246 118
247 sata_phy_i2c:sata-phy@38 { 119&i2c_0 {
248 compatible = "samsung,exynos-sataphy-i2c"; 120 status = "okay";
249 reg = <0x38>; 121 samsung,i2c-sda-delay = <100>;
250 }; 122 samsung,i2c-max-bus-freq = <20000>;
123
124 eeprom@50 {
125 compatible = "samsung,s524ad0xd1";
126 reg = <0x50>;
251 }; 127 };
252 128
253 i2c@12C80000 { 129 max77686@09 {
254 samsung,i2c-sda-delay = <100>; 130 compatible = "maxim,max77686";
255 samsung,i2c-max-bus-freq = <66000>; 131 reg = <0x09>;
256 status = "okay"; 132 interrupt-parent = <&gpx3>;
133 interrupts = <2 IRQ_TYPE_NONE>;
134
135 voltage-regulators {
136 ldo1_reg: LDO1 {
137 regulator-name = "P1.0V_LDO_OUT1";
138 regulator-min-microvolt = <1000000>;
139 regulator-max-microvolt = <1000000>;
140 regulator-always-on;
141 };
257 142
258 hdmiddc@50 { 143 ldo2_reg: LDO2 {
259 compatible = "samsung,exynos4210-hdmiddc"; 144 regulator-name = "P1.2V_LDO_OUT2";
260 reg = <0x50>; 145 regulator-min-microvolt = <1200000>;
261 }; 146 regulator-max-microvolt = <1200000>;
262 }; 147 regulator-always-on;
148 };
263 149
264 i2c@12CE0000 { 150 ldo3_reg: LDO3 {
265 samsung,i2c-sda-delay = <100>; 151 regulator-name = "P1.8V_LDO_OUT3";
266 samsung,i2c-max-bus-freq = <66000>; 152 regulator-min-microvolt = <1800000>;
267 status = "okay"; 153 regulator-max-microvolt = <1800000>;
154 regulator-always-on;
155 };
268 156
269 hdmiphy@38 { 157 ldo4_reg: LDO4 {
270 compatible = "samsung,exynos4212-hdmiphy"; 158 regulator-name = "P2.8V_LDO_OUT4";
271 reg = <0x38>; 159 regulator-min-microvolt = <2800000>;
272 }; 160 regulator-max-microvolt = <2800000>;
273 }; 161 };
274 162
275 sata@122F0000 { 163 ldo5_reg: LDO5 {
276 status = "okay"; 164 regulator-name = "P1.8V_LDO_OUT5";
277 }; 165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
167 };
278 168
279 sata-phy@12170000 { 169 ldo6_reg: LDO6 {
280 status = "okay"; 170 regulator-name = "P1.1V_LDO_OUT6";
281 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; 171 regulator-min-microvolt = <1100000>;
282 }; 172 regulator-max-microvolt = <1100000>;
173 regulator-always-on;
174 };
283 175
284 mmc@12200000 { 176 ldo7_reg: LDO7 {
285 status = "okay"; 177 regulator-name = "P1.1V_LDO_OUT7";
286 num-slots = <1>; 178 regulator-min-microvolt = <1100000>;
287 broken-cd; 179 regulator-max-microvolt = <1100000>;
288 card-detect-delay = <200>; 180 regulator-always-on;
289 samsung,dw-mshc-ciu-div = <3>; 181 };
290 samsung,dw-mshc-sdr-timing = <2 3>;
291 samsung,dw-mshc-ddr-timing = <1 2>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
294 bus-width = <8>;
295 cap-mmc-highspeed;
296 };
297 182
298 mmc@12220000 { 183 ldo8_reg: LDO8 {
299 status = "okay"; 184 regulator-name = "P1.0V_LDO_OUT8";
300 num-slots = <1>; 185 regulator-min-microvolt = <1000000>;
301 card-detect-delay = <200>; 186 regulator-max-microvolt = <1000000>;
302 samsung,dw-mshc-ciu-div = <3>; 187 };
303 samsung,dw-mshc-sdr-timing = <2 3>; 188
304 samsung,dw-mshc-ddr-timing = <1 2>; 189 ldo10_reg: LDO10 {
305 pinctrl-names = "default"; 190 regulator-name = "P1.8V_LDO_OUT10";
306 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 191 regulator-min-microvolt = <1800000>;
307 bus-width = <4>; 192 regulator-max-microvolt = <1800000>;
308 disable-wp; 193 };
309 cap-sd-highspeed;
310 };
311 194
312 spi_1: spi@12d30000 { 195 ldo11_reg: LDO11 {
313 cs-gpios = <&gpa2 5 0>; 196 regulator-name = "P1.8V_LDO_OUT11";
314 status = "okay"; 197 regulator-min-microvolt = <1800000>;
198 regulator-max-microvolt = <1800000>;
199 };
315 200
316 w25q80bw@0 { 201 ldo12_reg: LDO12 {
317 #address-cells = <1>; 202 regulator-name = "P3.0V_LDO_OUT12";
318 #size-cells = <1>; 203 regulator-min-microvolt = <3000000>;
319 compatible = "w25x80"; 204 regulator-max-microvolt = <3000000>;
320 reg = <0>; 205 };
321 spi-max-frequency = <1000000>;
322 206
323 controller-data { 207 ldo13_reg: LDO13 {
324 samsung,spi-feedback-delay = <0>; 208 regulator-name = "P1.8V_LDO_OUT13";
209 regulator-min-microvolt = <1800000>;
210 regulator-max-microvolt = <1800000>;
325 }; 211 };
326 212
327 partition@0 { 213 ldo14_reg: LDO14 {
328 label = "U-Boot"; 214 regulator-name = "P1.8V_LDO_OUT14";
329 reg = <0x0 0x40000>; 215 regulator-min-microvolt = <1800000>;
330 read-only; 216 regulator-max-microvolt = <1800000>;
331 }; 217 };
332 218
333 partition@40000 { 219 ldo15_reg: LDO15 {
334 label = "Kernel"; 220 regulator-name = "P1.0V_LDO_OUT15";
335 reg = <0x40000 0xc0000>; 221 regulator-min-microvolt = <1000000>;
222 regulator-max-microvolt = <1000000>;
223 };
224
225 ldo16_reg: LDO16 {
226 regulator-name = "P1.8V_LDO_OUT16";
227 regulator-min-microvolt = <1800000>;
228 regulator-max-microvolt = <1800000>;
229 };
230
231 buck1_reg: BUCK1 {
232 regulator-name = "vdd_mif";
233 regulator-min-microvolt = <950000>;
234 regulator-max-microvolt = <1300000>;
235 regulator-always-on;
236 regulator-boot-on;
237 };
238
239 buck2_reg: BUCK2 {
240 regulator-name = "vdd_arm";
241 regulator-min-microvolt = <850000>;
242 regulator-max-microvolt = <1350000>;
243 regulator-always-on;
244 regulator-boot-on;
245 };
246
247 buck3_reg: BUCK3 {
248 regulator-name = "vdd_int";
249 regulator-min-microvolt = <900000>;
250 regulator-max-microvolt = <1200000>;
251 regulator-always-on;
252 regulator-boot-on;
253 };
254
255 buck4_reg: BUCK4 {
256 regulator-name = "vdd_g3d";
257 regulator-min-microvolt = <850000>;
258 regulator-max-microvolt = <1300000>;
259 regulator-always-on;
260 regulator-boot-on;
261 };
262
263 buck5_reg: BUCK5 {
264 regulator-name = "P1.8V_BUCK_OUT5";
265 regulator-min-microvolt = <1800000>;
266 regulator-max-microvolt = <1800000>;
267 regulator-always-on;
268 regulator-boot-on;
336 }; 269 };
337 }; 270 };
338 }; 271 };
272};
339 273
340 hdmi { 274&i2c_1 {
341 hpd-gpio = <&gpx3 7 0>; 275 status = "okay";
342 }; 276 samsung,i2c-sda-delay = <100>;
277 samsung,i2c-max-bus-freq = <20000>;
343 278
344 codec@11000000 { 279 eeprom@51 {
345 samsung,mfc-r = <0x43000000 0x800000>; 280 compatible = "samsung,s524ad0xd1";
346 samsung,mfc-l = <0x51000000 0x800000>; 281 reg = <0x51>;
347 }; 282 };
348 283
349 i2s0: i2s@03830000 { 284 wm8994: wm8994@1a {
350 status = "okay"; 285 compatible = "wlf,wm8994";
286 reg = <0x1a>;
287
288 gpio-controller;
289 #gpio-cells = <2>;
290
291 clocks = <&codec_mclk>;
292 clock-names = "MCLK1";
293
294 AVDD2-supply = <&vdd>;
295 CPVDD-supply = <&vdd>;
296 DBVDD-supply = <&dbvdd>;
297 SPKVDD1-supply = <&spkvdd>;
298 SPKVDD2-supply = <&spkvdd>;
351 }; 299 };
300};
352 301
353 sound { 302&i2c_2 {
354 compatible = "samsung,smdk-wm8994"; 303 status = "okay";
304 samsung,i2c-sda-delay = <100>;
305 samsung,i2c-max-bus-freq = <66000>;
355 306
356 samsung,i2s-controller = <&i2s0>; 307 hdmiddc@50 {
357 samsung,audio-codec = <&wm8994>; 308 compatible = "samsung,exynos4210-hdmiddc";
309 reg = <0x50>;
358 }; 310 };
311};
312
313&i2c_8 {
314 status = "okay";
315 samsung,i2c-sda-delay = <100>;
316 samsung,i2c-max-bus-freq = <66000>;
359 317
360 usb@12110000 { 318 hdmiphy@38 {
361 samsung,vbus-gpio = <&gpx2 6 0>; 319 compatible = "samsung,exynos4212-hdmiphy";
320 reg = <0x38>;
362 }; 321 };
322};
323
324&i2c_9 {
325 status = "okay";
326 samsung,i2c-sda-delay = <100>;
327 samsung,i2c-max-bus-freq = <40000>;
328 samsung,i2c-slave-addr = <0x38>;
363 329
364 dp-controller@145B0000 { 330 sata_phy_i2c: sata-phy@38 {
365 samsung,color-space = <0>; 331 compatible = "samsung,exynos-sataphy-i2c";
366 samsung,dynamic-range = <0>; 332 reg = <0x38>;
367 samsung,ycbcr-coeff = <0>;
368 samsung,color-depth = <1>;
369 samsung,link-rate = <0x0a>;
370 samsung,lane-count = <4>;
371
372 pinctrl-names = "default";
373 pinctrl-0 = <&dp_hpd>;
374 status = "okay";
375 }; 333 };
334};
376 335
377 fimd@14400000 { 336&i2s0 {
378 status = "okay"; 337 status = "okay";
379 display-timings { 338};
380 native-mode = <&timing0>; 339
381 timing0: timing@0 { 340&mfc {
382 /* 1280x800 */ 341 samsung,mfc-r = <0x43000000 0x800000>;
383 clock-frequency = <50000>; 342 samsung,mfc-l = <0x51000000 0x800000>;
384 hactive = <1280>; 343};
385 vactive = <800>; 344
386 hfront-porch = <4>; 345&mmc_0 {
387 hback-porch = <4>; 346 status = "okay";
388 hsync-len = <4>; 347 num-slots = <1>;
389 vback-porch = <4>; 348 broken-cd;
390 vfront-porch = <4>; 349 card-detect-delay = <200>;
391 vsync-len = <4>; 350 samsung,dw-mshc-ciu-div = <3>;
392 }; 351 samsung,dw-mshc-sdr-timing = <2 3>;
352 samsung,dw-mshc-ddr-timing = <1 2>;
353 pinctrl-names = "default";
354 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
355 bus-width = <8>;
356 cap-mmc-highspeed;
357};
358
359&mmc_2 {
360 status = "okay";
361 num-slots = <1>;
362 card-detect-delay = <200>;
363 samsung,dw-mshc-ciu-div = <3>;
364 samsung,dw-mshc-sdr-timing = <2 3>;
365 samsung,dw-mshc-ddr-timing = <1 2>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
368 bus-width = <4>;
369 disable-wp;
370 cap-sd-highspeed;
371};
372
373&rtc {
374 status = "okay";
375};
376
377&sata {
378 status = "okay";
379};
380
381&sata_phy {
382 status = "okay";
383 samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
384};
385
386&spi_1 {
387 status = "okay";
388 cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>;
389
390 w25q80bw@0 {
391 #address-cells = <1>;
392 #size-cells = <1>;
393 compatible = "w25x80";
394 reg = <0>;
395 spi-max-frequency = <1000000>;
396
397 controller-data {
398 samsung,spi-feedback-delay = <0>;
393 }; 399 };
394 };
395 400
396 fixed-rate-clocks { 401 partition@0 {
397 xxti { 402 label = "U-Boot";
398 compatible = "samsung,clock-xxti"; 403 reg = <0x0 0x40000>;
399 clock-frequency = <24000000>; 404 read-only;
400 }; 405 };
401 406
402 codec_mclk: codec-mclk { 407 partition@40000 {
403 compatible = "fixed-clock"; 408 label = "Kernel";
404 #clock-cells = <0>; 409 reg = <0x40000 0xc0000>;
405 clock-frequency = <16934000>;
406 }; 410 };
407 }; 411 };
408}; 412};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 60429ad1c5d8..effaf2af41bc 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -6,10 +6,13 @@
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9*/ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/clock/maxim,max77686.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/input/input.h>
13#include "exynos5250.dtsi" 16#include "exynos5250.dtsi"
14 17
15/ { 18/ {
@@ -25,76 +28,7 @@
25 }; 28 };
26 29
27 chosen { 30 chosen {
28 }; 31 bootargs = "console=tty1";
29
30 rtc@101E0000 {
31 status = "okay";
32 };
33
34 pinctrl@11400000 {
35 ec_irq: ec-irq {
36 samsung,pins = "gpx1-6";
37 samsung,pin-function = <0>;
38 samsung,pin-pud = <0>;
39 samsung,pin-drv = <0>;
40 };
41
42 sd3_clk: sd3-clk {
43 samsung,pin-drv = <0>;
44 };
45
46 sd3_cmd: sd3-cmd {
47 samsung,pin-pud = <3>;
48 samsung,pin-drv = <0>;
49 };
50
51 sd3_bus4: sd3-bus-width4 {
52 samsung,pin-drv = <0>;
53 };
54
55 max98095_en: max98095-en {
56 samsung,pins = "gpx1-7";
57 samsung,pin-function = <0>;
58 samsung,pin-pud = <3>;
59 samsung,pin-drv = <0>;
60 };
61
62 tps65090_irq: tps65090-irq {
63 samsung,pins = "gpx2-6";
64 samsung,pin-function = <0>;
65 samsung,pin-pud = <0>;
66 samsung,pin-drv = <0>;
67 };
68
69 usb3_vbus_en: usb3-vbus-en {
70 samsung,pins = "gpx2-7";
71 samsung,pin-function = <1>;
72 samsung,pin-pud = <0>;
73 samsung,pin-drv = <0>;
74 };
75
76 hdmi_hpd_irq: hdmi-hpd-irq {
77 samsung,pins = "gpx3-7";
78 samsung,pin-function = <0>;
79 samsung,pin-pud = <1>;
80 samsung,pin-drv = <0>;
81 };
82 };
83
84 pinctrl@13400000 {
85 arb_their_claim: arb-their-claim {
86 samsung,pins = "gpe0-4";
87 samsung,pin-function = <0>;
88 samsung,pin-pud = <3>;
89 samsung,pin-drv = <0>;
90 };
91
92 arb_our_claim: arb-our-claim {
93 samsung,pins = "gpf0-3";
94 samsung,pin-function = <1>;
95 samsung,pin-pud = <0>;
96 samsung,pin-drv = <0>;
97 };
98 }; 32 };
99 33
100 gpio-keys { 34 gpio-keys {
@@ -102,14 +36,14 @@
102 36
103 power { 37 power {
104 label = "Power"; 38 label = "Power";
105 gpios = <&gpx1 3 1>; 39 gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
106 linux,code = <116>; /* KEY_POWER */ 40 linux,code = <KEY_POWER>;
107 gpio-key,wakeup; 41 gpio-key,wakeup;
108 }; 42 };
109 43
110 lid-switch { 44 lid-switch {
111 label = "Lid"; 45 label = "Lid";
112 gpios = <&gpx3 5 1>; 46 gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
113 linux,input-type = <5>; /* EV_SW */ 47 linux,input-type = <5>; /* EV_SW */
114 linux,code = <0>; /* SW_LID */ 48 linux,code = <0>; /* SW_LID */
115 debounce-interval = <1>; 49 debounce-interval = <1>;
@@ -130,8 +64,8 @@
130 64
131 i2c-parent = <&{/i2c@12CA0000}>; 65 i2c-parent = <&{/i2c@12CA0000}>;
132 66
133 our-claim-gpio = <&gpf0 3 1>; 67 our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
134 their-claim-gpios = <&gpe0 4 1>; 68 their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
135 slew-delay-us = <10>; 69 slew-delay-us = <10>;
136 wait-retry-us = <3000>; 70 wait-retry-us = <3000>;
137 wait-free-us = <50000>; 71 wait-free-us = <50000>;
@@ -154,7 +88,7 @@
154 cros_ec: embedded-controller { 88 cros_ec: embedded-controller {
155 compatible = "google,cros-ec-i2c"; 89 compatible = "google,cros-ec-i2c";
156 reg = <0x1e>; 90 reg = <0x1e>;
157 interrupts = <6 0>; 91 interrupts = <6 IRQ_TYPE_NONE>;
158 interrupt-parent = <&gpx1>; 92 interrupt-parent = <&gpx1>;
159 pinctrl-names = "default"; 93 pinctrl-names = "default";
160 pinctrl-0 = <&ec_irq>; 94 pinctrl-0 = <&ec_irq>;
@@ -241,13 +175,6 @@
241 }; 175 };
242 176
243 i2c@12CD0000 { 177 i2c@12CD0000 {
244 max98095: codec@11 {
245 compatible = "maxim,max98095";
246 reg = <0x11>;
247 pinctrl-0 = <&max98095_en>;
248 pinctrl-names = "default";
249 };
250
251 ptn3460: lvds-bridge@20 { 178 ptn3460: lvds-bridge@20 {
252 compatible = "nxp,ptn3460"; 179 compatible = "nxp,ptn3460";
253 reg = <0x20>; 180 reg = <0x20>;
@@ -258,10 +185,6 @@
258 }; 185 };
259 }; 186 };
260 187
261 i2s0: i2s@03830000 {
262 status = "okay";
263 };
264
265 sound { 188 sound {
266 compatible = "google,snow-audio-max98095"; 189 compatible = "google,snow-audio-max98095";
267 190
@@ -275,20 +198,12 @@
275 regulator-name = "P5.0V_USB3CON"; 198 regulator-name = "P5.0V_USB3CON";
276 regulator-min-microvolt = <5000000>; 199 regulator-min-microvolt = <5000000>;
277 regulator-max-microvolt = <5000000>; 200 regulator-max-microvolt = <5000000>;
278 gpio = <&gpx2 7 0>; 201 gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>;
279 pinctrl-names = "default"; 202 pinctrl-names = "default";
280 pinctrl-0 = <&usb3_vbus_en>; 203 pinctrl-0 = <&usb3_vbus_en>;
281 enable-active-high; 204 enable-active-high;
282 }; 205 };
283 206
284 phy@12100000 {
285 vbus-supply = <&usb3_vbus_reg>;
286 };
287
288 usb@12110000 {
289 samsung,vbus-gpio = <&gpx1 1 0>;
290 };
291
292 fixed-rate-clocks { 207 fixed-rate-clocks {
293 xxti { 208 xxti {
294 compatible = "samsung,clock-xxti"; 209 compatible = "samsung,clock-xxti";
@@ -296,18 +211,6 @@
296 }; 211 };
297 }; 212 };
298 213
299 hdmi {
300 hpd-gpio = <&gpx3 7 0>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&hdmi_hpd_irq>;
303 phy = <&hdmiphy>;
304 ddc = <&i2c_2>;
305 hdmi-en-supply = <&tps65090_fet7>;
306 vdd-supply = <&ldo8_reg>;
307 vdd_osc-supply = <&ldo10_reg>;
308 vdd_pll-supply = <&ldo8_reg>;
309 };
310
311 backlight: backlight { 214 backlight: backlight {
312 compatible = "pwm-backlight"; 215 compatible = "pwm-backlight";
313 pwms = <&pwm 0 1000000 0>; 216 pwms = <&pwm 0 1000000 0>;
@@ -319,30 +222,46 @@
319 pinctrl-names = "default"; 222 pinctrl-names = "default";
320 }; 223 };
321 224
322 fimd@14400000 {
323 status = "okay";
324 samsung,invert-vclk;
325 };
326
327 panel: panel { 225 panel: panel {
328 compatible = "auo,b116xw03"; 226 compatible = "auo,b116xw03";
329 power-supply = <&fet6>; 227 power-supply = <&fet6>;
330 backlight = <&backlight>; 228 backlight = <&backlight>;
331 }; 229 };
230};
332 231
333 dp-controller@145B0000 { 232&dp {
334 status = "okay"; 233 status = "okay";
335 pinctrl-names = "default"; 234 pinctrl-names = "default";
336 pinctrl-0 = <&dp_hpd>; 235 pinctrl-0 = <&dp_hpd>;
337 samsung,color-space = <0>; 236 samsung,color-space = <0>;
338 samsung,dynamic-range = <0>; 237 samsung,dynamic-range = <0>;
339 samsung,ycbcr-coeff = <0>; 238 samsung,ycbcr-coeff = <0>;
340 samsung,color-depth = <1>; 239 samsung,color-depth = <1>;
341 samsung,link-rate = <0x0a>; 240 samsung,link-rate = <0x0a>;
342 samsung,lane-count = <2>; 241 samsung,lane-count = <2>;
343 samsung,hpd-gpio = <&gpx0 7 0>; 242 samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
344 bridge = <&ptn3460>; 243 bridge = <&ptn3460>;
345 }; 244};
245
246&ehci {
247 samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
248};
249
250&fimd {
251 status = "okay";
252 samsung,invert-vclk;
253};
254
255&hdmi {
256 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&hdmi_hpd_irq>;
259 phy = <&hdmiphy>;
260 ddc = <&i2c_2>;
261 hdmi-en-supply = <&tps65090_fet7>;
262 vdd-supply = <&ldo8_reg>;
263 vdd_osc-supply = <&ldo10_reg>;
264 vdd_pll-supply = <&ldo8_reg>;
346}; 265};
347 266
348&i2c_0 { 267&i2c_0 {
@@ -350,10 +269,10 @@
350 samsung,i2c-sda-delay = <100>; 269 samsung,i2c-sda-delay = <100>;
351 samsung,i2c-max-bus-freq = <378000>; 270 samsung,i2c-max-bus-freq = <378000>;
352 271
353 max77686@09 { 272 max77686: max77686@09 {
354 compatible = "maxim,max77686"; 273 compatible = "maxim,max77686";
355 interrupt-parent = <&gpx3>; 274 interrupt-parent = <&gpx3>;
356 interrupts = <2 0>; 275 interrupts = <2 IRQ_TYPE_NONE>;
357 pinctrl-names = "default"; 276 pinctrl-names = "default";
358 pinctrl-0 = <&max77686_irq>; 277 pinctrl-0 = <&max77686_irq>;
359 wakeup-source; 278 wakeup-source;
@@ -503,7 +422,7 @@
503 trackpad { 422 trackpad {
504 reg = <0x67>; 423 reg = <0x67>;
505 compatible = "cypress,cyapa"; 424 compatible = "cypress,cyapa";
506 interrupts = <2 0>; 425 interrupts = <2 IRQ_TYPE_NONE>;
507 interrupt-parent = <&gpx1>; 426 interrupt-parent = <&gpx1>;
508 wakeup-source; 427 wakeup-source;
509 }; 428 };
@@ -550,6 +469,13 @@
550 status = "okay"; 469 status = "okay";
551 samsung,i2c-sda-delay = <100>; 470 samsung,i2c-sda-delay = <100>;
552 samsung,i2c-max-bus-freq = <66000>; 471 samsung,i2c-max-bus-freq = <66000>;
472
473 max98095: codec@11 {
474 compatible = "maxim,max98095";
475 reg = <0x11>;
476 pinctrl-0 = <&max98095_en>;
477 pinctrl-names = "default";
478 };
553}; 479};
554 480
555&i2c_8 { 481&i2c_8 {
@@ -563,6 +489,10 @@
563 }; 489 };
564}; 490};
565 491
492&i2s0 {
493 status = "okay";
494};
495
566&mmc_0 { 496&mmc_0 {
567 status = "okay"; 497 status = "okay";
568 num-slots = <1>; 498 num-slots = <1>;
@@ -587,7 +517,7 @@
587 pinctrl-names = "default"; 517 pinctrl-names = "default";
588 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; 518 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
589 bus-width = <4>; 519 bus-width = <4>;
590 wp-gpios = <&gpc2 1 0>; 520 wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>;
591 cap-sd-highspeed; 521 cap-sd-highspeed;
592}; 522};
593 523
@@ -610,12 +540,82 @@
610}; 540};
611 541
612&pinctrl_0 { 542&pinctrl_0 {
543 ec_irq: ec-irq {
544 samsung,pins = "gpx1-6";
545 samsung,pin-function = <0>;
546 samsung,pin-pud = <0>;
547 samsung,pin-drv = <0>;
548 };
549
550 max98095_en: max98095-en {
551 samsung,pins = "gpx1-7";
552 samsung,pin-function = <0>;
553 samsung,pin-pud = <3>;
554 samsung,pin-drv = <0>;
555 };
556
557 tps65090_irq: tps65090-irq {
558 samsung,pins = "gpx2-6";
559 samsung,pin-function = <0>;
560 samsung,pin-pud = <0>;
561 samsung,pin-drv = <0>;
562 };
563
564 usb3_vbus_en: usb3-vbus-en {
565 samsung,pins = "gpx2-7";
566 samsung,pin-function = <1>;
567 samsung,pin-pud = <0>;
568 samsung,pin-drv = <0>;
569 };
570
613 max77686_irq: max77686-irq { 571 max77686_irq: max77686-irq {
614 samsung,pins = "gpx3-2"; 572 samsung,pins = "gpx3-2";
615 samsung,pin-function = <0>; 573 samsung,pin-function = <0>;
616 samsung,pin-pud = <0>; 574 samsung,pin-pud = <0>;
617 samsung,pin-drv = <0>; 575 samsung,pin-drv = <0>;
618 }; 576 };
577
578 hdmi_hpd_irq: hdmi-hpd-irq {
579 samsung,pins = "gpx3-7";
580 samsung,pin-function = <0>;
581 samsung,pin-pud = <1>;
582 samsung,pin-drv = <0>;
583 };
584};
585
586&pinctrl_1 {
587 arb_their_claim: arb-their-claim {
588 samsung,pins = "gpe0-4";
589 samsung,pin-function = <0>;
590 samsung,pin-pud = <3>;
591 samsung,pin-drv = <0>;
592 };
593
594 arb_our_claim: arb-our-claim {
595 samsung,pins = "gpf0-3";
596 samsung,pin-function = <1>;
597 samsung,pin-pud = <0>;
598 samsung,pin-drv = <0>;
599 };
600};
601
602&rtc {
603 status = "okay";
604 clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
605 clock-names = "rtc", "rtc_src";
606};
607
608&sd3_bus4 {
609 samsung,pin-drv = <0>;
610};
611
612&sd3_clk {
613 samsung,pin-drv = <0>;
614};
615
616&sd3_cmd {
617 samsung,pin-pud = <3>;
618 samsung,pin-drv = <0>;
619}; 619};
620 620
621&spi_1 { 621&spi_1 {
@@ -628,4 +628,8 @@
628 dr_mode = "host"; 628 dr_mode = "host";
629}; 629};
630 630
631&usbdrd_phy {
632 vbus-supply = <&usb3_vbus_reg>;
633};
634
631#include "cros-ec-keyboard.dtsi" 635#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
new file mode 100644
index 000000000000..f02775487cd4
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -0,0 +1,566 @@
1/*
2 * Google Spring board device tree source
3 *
4 * Copyright (c) 2013 Google, Inc
5 * Copyright (c) 2014 SUSE LINUX Products GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12/dts-v1/;
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/input/input.h>
16#include "exynos5250.dtsi"
17
18/ {
19 model = "Google Spring";
20 compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5";
21
22 memory {
23 reg = <0x40000000 0x80000000>;
24 };
25
26 chosen {
27 bootargs = "console=tty1";
28 };
29
30 gpio-keys {
31 compatible = "gpio-keys";
32 pinctrl-names = "default";
33 pinctrl-0 = <&power_key_irq>, <&lid_irq>;
34
35 power {
36 label = "Power";
37 gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
38 linux,code = <KEY_POWER>;
39 gpio-key,wakeup;
40 };
41
42 lid-switch {
43 label = "Lid";
44 gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
45 linux,input-type = <5>; /* EV_SW */
46 linux,code = <0>; /* SW_LID */
47 debounce-interval = <1>;
48 gpio-key,wakeup;
49 };
50 };
51
52 usb-hub {
53 compatible = "smsc,usb3503a";
54 reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>;
55 pinctrl-names = "default";
56 pinctrl-0 = <&hsic_reset>;
57 };
58
59 fixed-rate-clocks {
60 xxti {
61 compatible = "samsung,clock-xxti";
62 clock-frequency = <24000000>;
63 };
64 };
65};
66
67&dp {
68 status = "okay";
69 pinctrl-names = "default";
70 pinctrl-0 = <&dp_hpd_gpio>;
71 samsung,color-space = <0>;
72 samsung,dynamic-range = <0>;
73 samsung,ycbcr-coeff = <0>;
74 samsung,color-depth = <1>;
75 samsung,link-rate = <0x0a>;
76 samsung,lane-count = <1>;
77 samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
78};
79
80&ehci {
81 samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
82};
83
84&fimd {
85 status = "okay";
86 samsung,invert-vclk;
87};
88
89&hdmi {
90 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&hdmi_hpd_irq>;
93 phy = <&hdmiphy>;
94 ddc = <&i2c_2>;
95 hdmi-en-supply = <&ldo8_reg>;
96 vdd-supply = <&ldo8_reg>;
97 vdd_osc-supply = <&ldo10_reg>;
98 vdd_pll-supply = <&ldo8_reg>;
99};
100
101&i2c_0 {
102 status = "okay";
103 samsung,i2c-sda-delay = <100>;
104 samsung,i2c-max-bus-freq = <378000>;
105
106 s5m8767-pmic@66 {
107 compatible = "samsung,s5m8767-pmic";
108 reg = <0x66>;
109 interrupt-parent = <&gpx3>;
110 interrupts = <2 IRQ_TYPE_NONE>;
111 pinctrl-names = "default";
112 pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>;
113 wakeup-source;
114
115 s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
116 <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
117 <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
118
119 s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
120 <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
121 <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
122
123 /*
124 * The following arrays of DVS voltages are not used, since we are
125 * not using GPIOs to control PMIC bucks, but they must be defined
126 * to please the driver.
127 */
128 s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
129 <1250000>, <1200000>,
130 <1150000>, <1100000>,
131 <1000000>, <950000>;
132
133 s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
134 <1100000>, <1100000>,
135 <1000000>, <1000000>,
136 <1000000>, <1000000>;
137
138 s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
139 <1200000>, <1200000>,
140 <1200000>, <1200000>,
141 <1200000>, <1200000>;
142
143 clocks {
144 compatible = "samsung,s5m8767-clk";
145 #clock-cells = <1>;
146 clock-output-names = "en32khz_ap",
147 "en32khz_cp",
148 "en32khz_bt";
149 };
150
151 regulators {
152 ldo4_reg: LDO4 {
153 regulator-name = "P1.0V_LDO_OUT4";
154 regulator-min-microvolt = <1000000>;
155 regulator-max-microvolt = <1000000>;
156 regulator-always-on;
157 op_mode = <0>;
158 };
159
160 ldo5_reg: LDO5 {
161 regulator-name = "P1.0V_LDO_OUT5";
162 regulator-min-microvolt = <1000000>;
163 regulator-max-microvolt = <1000000>;
164 regulator-always-on;
165 op_mode = <0>;
166 };
167
168 ldo6_reg: LDO6 {
169 regulator-name = "vdd_mydp";
170 regulator-min-microvolt = <1000000>;
171 regulator-max-microvolt = <1000000>;
172 regulator-always-on;
173 op_mode = <3>;
174 };
175
176 ldo7_reg: LDO7 {
177 regulator-name = "P1.1V_LDO_OUT7";
178 regulator-min-microvolt = <1100000>;
179 regulator-max-microvolt = <1100000>;
180 regulator-always-on;
181 op_mode = <3>;
182 };
183
184 ldo8_reg: LDO8 {
185 regulator-name = "P1.0V_LDO_OUT8";
186 regulator-min-microvolt = <1000000>;
187 regulator-max-microvolt = <1000000>;
188 regulator-always-on;
189 op_mode = <3>;
190 };
191
192 ldo10_reg: LDO10 {
193 regulator-name = "P1.8V_LDO_OUT10";
194 regulator-min-microvolt = <1800000>;
195 regulator-max-microvolt = <1800000>;
196 regulator-always-on;
197 op_mode = <3>;
198 };
199
200 ldo11_reg: LDO11 {
201 regulator-name = "P1.8V_LDO_OUT11";
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <1800000>;
204 regulator-always-on;
205 op_mode = <0>;
206 };
207
208 ldo12_reg: LDO12 {
209 regulator-name = "P3.0V_LDO_OUT12";
210 regulator-min-microvolt = <3000000>;
211 regulator-max-microvolt = <3000000>;
212 regulator-always-on;
213 op_mode = <3>;
214 };
215
216 ldo13_reg: LDO13 {
217 regulator-name = "P1.8V_LDO_OUT13";
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <1800000>;
220 regulator-always-on;
221 op_mode = <0>;
222 };
223
224 ldo14_reg: LDO14 {
225 regulator-name = "P1.8V_LDO_OUT14";
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-always-on;
229 op_mode = <3>;
230 };
231
232 ldo15_reg: LDO15 {
233 regulator-name = "P1.0V_LDO_OUT15";
234 regulator-min-microvolt = <1000000>;
235 regulator-max-microvolt = <1000000>;
236 regulator-always-on;
237 op_mode = <3>;
238 };
239
240 ldo16_reg: LDO16 {
241 regulator-name = "P1.8V_LDO_OUT16";
242 regulator-min-microvolt = <1800000>;
243 regulator-max-microvolt = <1800000>;
244 regulator-always-on;
245 op_mode = <3>;
246 };
247
248 ldo17_reg: LDO17 {
249 regulator-name = "P2.8V_LDO_OUT17";
250 regulator-min-microvolt = <2800000>;
251 regulator-max-microvolt = <2800000>;
252 regulator-always-on;
253 op_mode = <0>;
254 };
255
256 ldo25_reg: LDO25 {
257 regulator-name = "vdd_bridge";
258 regulator-min-microvolt = <1200000>;
259 regulator-max-microvolt = <1200000>;
260 regulator-always-on;
261 op_mode = <1>;
262 };
263
264 buck1_reg: BUCK1 {
265 regulator-name = "vdd_mif";
266 regulator-min-microvolt = <950000>;
267 regulator-max-microvolt = <1300000>;
268 regulator-always-on;
269 regulator-boot-on;
270 op_mode = <3>;
271 };
272
273 buck2_reg: BUCK2 {
274 regulator-name = "vdd_arm";
275 regulator-min-microvolt = <850000>;
276 regulator-max-microvolt = <1350000>;
277 regulator-always-on;
278 regulator-boot-on;
279 op_mode = <3>;
280 };
281
282 buck3_reg: BUCK3 {
283 regulator-name = "vdd_int";
284 regulator-min-microvolt = <900000>;
285 regulator-max-microvolt = <1200000>;
286 regulator-always-on;
287 regulator-boot-on;
288 op_mode = <3>;
289 };
290
291 buck4_reg: BUCK4 {
292 regulator-name = "vdd_g3d";
293 regulator-min-microvolt = <850000>;
294 regulator-max-microvolt = <1300000>;
295 regulator-boot-on;
296 op_mode = <3>;
297 };
298
299 buck5_reg: BUCK5 {
300 regulator-name = "P1.8V_BUCK_OUT5";
301 regulator-min-microvolt = <1800000>;
302 regulator-max-microvolt = <1800000>;
303 regulator-always-on;
304 regulator-boot-on;
305 op_mode = <1>;
306 };
307
308 buck6_reg: BUCK6 {
309 regulator-name = "P1.2V_BUCK_OUT6";
310 regulator-min-microvolt = <1200000>;
311 regulator-max-microvolt = <1200000>;
312 regulator-always-on;
313 regulator-boot-on;
314 op_mode = <0>;
315 };
316
317 buck9_reg: BUCK9 {
318 regulator-name = "vdd_ummc";
319 regulator-min-microvolt = <950000>;
320 regulator-max-microvolt = <3000000>;
321 regulator-always-on;
322 regulator-boot-on;
323 op_mode = <3>;
324 };
325 };
326 };
327};
328
329&i2c_1 {
330 status = "okay";
331 samsung,i2c-sda-delay = <100>;
332 samsung,i2c-max-bus-freq = <378000>;
333
334 trackpad@4b {
335 compatible = "atmel,maxtouch";
336 reg = <0x4b>;
337 interrupt-parent = <&gpx1>;
338 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&trackpad_irq>;
341 linux,gpio-keymap = <KEY_RESERVED
342 KEY_RESERVED
343 KEY_RESERVED
344 KEY_RESERVED
345 KEY_RESERVED
346 BTN_LEFT>;
347 wakeup-source;
348 };
349};
350
351/*
352 * Disabled pullups since external part has its own pullups and
353 * double-pulling gets us out of spec in some cases.
354 */
355&i2c2_bus {
356 samsung,pin-pud = <0>;
357};
358
359&i2c_2 {
360 status = "okay";
361 samsung,i2c-sda-delay = <100>;
362 samsung,i2c-max-bus-freq = <66000>;
363
364 hdmiddc@50 {
365 compatible = "samsung,exynos4210-hdmiddc";
366 reg = <0x50>;
367 };
368};
369
370&i2c_3 {
371 status = "okay";
372 samsung,i2c-sda-delay = <100>;
373 samsung,i2c-max-bus-freq = <66000>;
374};
375
376&i2c_4 {
377 status = "okay";
378 samsung,i2c-sda-delay = <100>;
379 samsung,i2c-max-bus-freq = <66000>;
380
381 cros_ec: embedded-controller {
382 compatible = "google,cros-ec-i2c";
383 reg = <0x1e>;
384 interrupts = <6 IRQ_TYPE_NONE>;
385 interrupt-parent = <&gpx1>;
386 wakeup-source;
387 pinctrl-names = "default";
388 pinctrl-0 = <&ec_irq>;
389 };
390};
391
392&i2c_5 {
393 status = "okay";
394 samsung,i2c-sda-delay = <100>;
395 samsung,i2c-max-bus-freq = <66000>;
396};
397
398&i2c_7 {
399 status = "okay";
400 samsung,i2c-sda-delay = <100>;
401 samsung,i2c-max-bus-freq = <66000>;
402
403 temperature-sensor@4c {
404 compatible = "gmt,g781";
405 reg = <0x4c>;
406 };
407};
408
409&i2c_8 {
410 status = "okay";
411 samsung,i2c-sda-delay = <100>;
412 samsung,i2c-max-bus-freq = <378000>;
413
414 hdmiphy: hdmiphy@38 {
415 compatible = "samsung,exynos4212-hdmiphy";
416 reg = <0x38>;
417 };
418};
419
420&i2s0 {
421 status = "okay";
422};
423
424&mfc {
425 samsung,mfc-r = <0x43000000 0x800000>;
426 samsung,mfc-l = <0x51000000 0x800000>;
427};
428
429&mmc_0 {
430 status = "okay";
431 num-slots = <1>;
432 supports-highspeed;
433 broken-cd;
434 card-detect-delay = <200>;
435 samsung,dw-mshc-ciu-div = <3>;
436 samsung,dw-mshc-sdr-timing = <2 3>;
437 samsung,dw-mshc-ddr-timing = <1 2>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
440
441 slot@0 {
442 reg = <0>;
443 bus-width = <8>;
444 };
445};
446
447/*
448 * On Spring we've got SIP WiFi and so can keep drive strengths low to
449 * reduce EMI.
450 */
451&mmc_1 {
452 status = "okay";
453 num-slots = <1>;
454 supports-highspeed;
455 broken-cd;
456 card-detect-delay = <200>;
457 samsung,dw-mshc-ciu-div = <3>;
458 samsung,dw-mshc-sdr-timing = <2 3>;
459 samsung,dw-mshc-ddr-timing = <1 2>;
460 pinctrl-names = "default";
461 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
462
463 slot@0 {
464 reg = <0>;
465 bus-width = <4>;
466 };
467};
468
469&pinctrl_0 {
470 s5m8767_dvs: s5m8767-dvs {
471 samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2";
472 samsung,pin-function = <0>;
473 samsung,pin-pud = <1>;
474 samsung,pin-drv = <0>;
475 };
476
477 dp_hpd_gpio: dp-hpd-gpio {
478 samsung,pins = "gpc3-0";
479 samsung,pin-function = <0>;
480 samsung,pin-pud = <3>;
481 samsung,pin-drv = <0>;
482 };
483
484 trackpad_irq: trackpad-irq {
485 samsung,pins = "gpx1-2";
486 samsung,pin-function = <0xf>;
487 samsung,pin-pud = <0>;
488 samsung,pin-drv = <0>;
489 };
490
491 power_key_irq: power-key-irq {
492 samsung,pins = "gpx1-3";
493 samsung,pin-function = <0>;
494 samsung,pin-pud = <0>;
495 samsung,pin-drv = <0>;
496 };
497
498 ec_irq: ec-irq {
499 samsung,pins = "gpx1-6";
500 samsung,pin-function = <0>;
501 samsung,pin-pud = <0>;
502 samsung,pin-drv = <0>;
503 };
504
505 s5m8767_ds: s5m8767-ds {
506 samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5";
507 samsung,pin-function = <0>;
508 samsung,pin-pud = <1>;
509 samsung,pin-drv = <0>;
510 };
511
512 s5m8767_irq: s5m8767-irq {
513 samsung,pins = "gpx3-2";
514 samsung,pin-function = <0>;
515 samsung,pin-pud = <0>;
516 samsung,pin-drv = <0>;
517 };
518
519 lid_irq: lid-irq {
520 samsung,pins = "gpx3-5";
521 samsung,pin-function = <0>;
522 samsung,pin-pud = <0>;
523 samsung,pin-drv = <0>;
524 };
525
526 hdmi_hpd_irq: hdmi-hpd-irq {
527 samsung,pins = "gpx3-7";
528 samsung,pin-function = <0>;
529 samsung,pin-pud = <1>;
530 samsung,pin-drv = <0>;
531 };
532};
533
534&pinctrl_1 {
535 hsic_reset: hsic-reset {
536 samsung,pins = "gpe1-0";
537 samsung,pin-function = <1>;
538 samsung,pin-pud = <0>;
539 samsung,pin-drv = <0>;
540 };
541};
542
543&sd1_bus4 {
544 samsung,pin-drv = <0>;
545};
546
547&sd1_cd {
548 samsung,pin-drv = <0>;
549};
550
551&sd1_clk {
552 samsung,pin-drv = <0>;
553};
554
555&sd1_cmd {
556 samsung,pin-pud = <3>;
557 samsung,pin-drv = <0>;
558};
559
560&spi_1 {
561 status = "okay";
562 samsung,spi-src-clk = <0>;
563 num-cs = <1>;
564};
565
566#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index d55c1a2eb798..d45a07ea3402 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -218,7 +218,7 @@
218 clock-names = "fimg2d"; 218 clock-names = "fimg2d";
219 }; 219 };
220 220
221 codec@11000000 { 221 mfc: codec@11000000 {
222 compatible = "samsung,mfc-v6"; 222 compatible = "samsung,mfc-v6";
223 reg = <0x11000000 0x10000>; 223 reg = <0x11000000 0x10000>;
224 interrupts = <0 96 0>; 224 interrupts = <0 96 0>;
@@ -227,7 +227,7 @@
227 clock-names = "mfc"; 227 clock-names = "mfc";
228 }; 228 };
229 229
230 rtc@101E0000 { 230 rtc: rtc@101E0000 {
231 clocks = <&clock CLK_RTC>; 231 clocks = <&clock CLK_RTC>;
232 clock-names = "rtc"; 232 clock-names = "rtc";
233 status = "disabled"; 233 status = "disabled";
@@ -261,7 +261,7 @@
261 clock-names = "uart", "clk_uart_baud0"; 261 clock-names = "uart", "clk_uart_baud0";
262 }; 262 };
263 263
264 sata@122F0000 { 264 sata: sata@122F0000 {
265 compatible = "snps,dwc-ahci"; 265 compatible = "snps,dwc-ahci";
266 samsung,sata-freq = <66>; 266 samsung,sata-freq = <66>;
267 reg = <0x122F0000 0x1ff>; 267 reg = <0x122F0000 0x1ff>;
@@ -293,6 +293,7 @@
293 clock-names = "i2c"; 293 clock-names = "i2c";
294 pinctrl-names = "default"; 294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c0_bus>; 295 pinctrl-0 = <&i2c0_bus>;
296 samsung,sysreg-phandle = <&sysreg_system_controller>;
296 status = "disabled"; 297 status = "disabled";
297 }; 298 };
298 299
@@ -306,6 +307,7 @@
306 clock-names = "i2c"; 307 clock-names = "i2c";
307 pinctrl-names = "default"; 308 pinctrl-names = "default";
308 pinctrl-0 = <&i2c1_bus>; 309 pinctrl-0 = <&i2c1_bus>;
310 samsung,sysreg-phandle = <&sysreg_system_controller>;
309 status = "disabled"; 311 status = "disabled";
310 }; 312 };
311 313
@@ -319,6 +321,7 @@
319 clock-names = "i2c"; 321 clock-names = "i2c";
320 pinctrl-names = "default"; 322 pinctrl-names = "default";
321 pinctrl-0 = <&i2c2_bus>; 323 pinctrl-0 = <&i2c2_bus>;
324 samsung,sysreg-phandle = <&sysreg_system_controller>;
322 status = "disabled"; 325 status = "disabled";
323 }; 326 };
324 327
@@ -332,6 +335,7 @@
332 clock-names = "i2c"; 335 clock-names = "i2c";
333 pinctrl-names = "default"; 336 pinctrl-names = "default";
334 pinctrl-0 = <&i2c3_bus>; 337 pinctrl-0 = <&i2c3_bus>;
338 samsung,sysreg-phandle = <&sysreg_system_controller>;
335 status = "disabled"; 339 status = "disabled";
336 }; 340 };
337 341
@@ -573,7 +577,7 @@
573 #phy-cells = <1>; 577 #phy-cells = <1>;
574 }; 578 };
575 579
576 usb@12110000 { 580 ehci: usb@12110000 {
577 compatible = "samsung,exynos4210-ehci"; 581 compatible = "samsung,exynos4210-ehci";
578 reg = <0x12110000 0x100>; 582 reg = <0x12110000 0x100>;
579 interrupts = <0 71 0>; 583 interrupts = <0 71 0>;
@@ -588,7 +592,7 @@
588 }; 592 };
589 }; 593 };
590 594
591 usb@12120000 { 595 ohci: usb@12120000 {
592 compatible = "samsung,exynos4210-ohci"; 596 compatible = "samsung,exynos4210-ohci";
593 reg = <0x12120000 0x100>; 597 reg = <0x12120000 0x100>;
594 interrupts = <0 71 0>; 598 interrupts = <0 71 0>;
@@ -710,7 +714,7 @@
710 clock-names = "gscl"; 714 clock-names = "gscl";
711 }; 715 };
712 716
713 hdmi { 717 hdmi: hdmi {
714 compatible = "samsung,exynos4212-hdmi"; 718 compatible = "samsung,exynos4212-hdmi";
715 reg = <0x14530000 0x70000>; 719 reg = <0x14530000 0x70000>;
716 interrupts = <0 95 0>; 720 interrupts = <0 95 0>;
@@ -736,14 +740,14 @@
736 #phy-cells = <0>; 740 #phy-cells = <0>;
737 }; 741 };
738 742
739 dp-controller@145B0000 { 743 dp: dp-controller@145B0000 {
740 clocks = <&clock CLK_DP>; 744 clocks = <&clock CLK_DP>;
741 clock-names = "dp"; 745 clock-names = "dp";
742 phys = <&dp_phy>; 746 phys = <&dp_phy>;
743 phy-names = "dp"; 747 phy-names = "dp";
744 }; 748 };
745 749
746 fimd@14400000 { 750 fimd: fimd@14400000 {
747 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 751 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
748 clock-names = "sclk_fimd", "fimd"; 752 clock-names = "sclk_fimd", "fimd";
749 }; 753 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 82cdb74484cc..9a050e19a4dc 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -12,6 +12,7 @@
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/clock/maxim,max77802.h>
15#include "exynos5420.dtsi" 16#include "exynos5420.dtsi"
16 17
17/ { 18/ {
@@ -151,7 +152,7 @@
151 status = "okay"; 152 status = "okay";
152 clock-frequency = <400000>; 153 clock-frequency = <400000>;
153 154
154 max77802-pmic@9 { 155 max77802: max77802-pmic@9 {
155 compatible = "maxim,max77802"; 156 compatible = "maxim,max77802";
156 interrupt-parent = <&gpx3>; 157 interrupt-parent = <&gpx3>;
157 interrupts = <1 IRQ_TYPE_NONE>; 158 interrupts = <1 IRQ_TYPE_NONE>;
@@ -560,7 +561,7 @@
560 status = "okay"; 561 status = "okay";
561 num-slots = <1>; 562 num-slots = <1>;
562 broken-cd; 563 broken-cd;
563 caps2-mmc-hs200-1_8v; 564 mmc-hs200-1_8v;
564 cap-mmc-highspeed; 565 cap-mmc-highspeed;
565 non-removable; 566 non-removable;
566 card-detect-delay = <200>; 567 card-detect-delay = <200>;
@@ -727,6 +728,8 @@
727 728
728&rtc { 729&rtc {
729 status = "okay"; 730 status = "okay";
731 clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
732 clock-names = "rtc", "rtc_src";
730}; 733};
731 734
732&spi_2 { 735&spi_2 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8617a031cbc0..90bf4011e319 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -560,6 +560,7 @@
560 clock-names = "i2c"; 560 clock-names = "i2c";
561 pinctrl-names = "default"; 561 pinctrl-names = "default";
562 pinctrl-0 = <&i2c0_bus>; 562 pinctrl-0 = <&i2c0_bus>;
563 samsung,sysreg-phandle = <&sysreg_system_controller>;
563 status = "disabled"; 564 status = "disabled";
564 }; 565 };
565 566
@@ -573,6 +574,7 @@
573 clock-names = "i2c"; 574 clock-names = "i2c";
574 pinctrl-names = "default"; 575 pinctrl-names = "default";
575 pinctrl-0 = <&i2c1_bus>; 576 pinctrl-0 = <&i2c1_bus>;
577 samsung,sysreg-phandle = <&sysreg_system_controller>;
576 status = "disabled"; 578 status = "disabled";
577 }; 579 };
578 580
@@ -586,6 +588,7 @@
586 clock-names = "i2c"; 588 clock-names = "i2c";
587 pinctrl-names = "default"; 589 pinctrl-names = "default";
588 pinctrl-0 = <&i2c2_bus>; 590 pinctrl-0 = <&i2c2_bus>;
591 samsung,sysreg-phandle = <&sysreg_system_controller>;
589 status = "disabled"; 592 status = "disabled";
590 }; 593 };
591 594
@@ -599,6 +602,7 @@
599 clock-names = "i2c"; 602 clock-names = "i2c";
600 pinctrl-names = "default"; 603 pinctrl-names = "default";
601 pinctrl-0 = <&i2c3_bus>; 604 pinctrl-0 = <&i2c3_bus>;
605 samsung,sysreg-phandle = <&sysreg_system_controller>;
602 status = "disabled"; 606 status = "disabled";
603 }; 607 };
604 608
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 7bb1c8dd42dd..e8fdda827fc9 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
12#include <dt-bindings/input/input.h> 12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/clock/maxim,max77802.h>
15#include "exynos5800.dtsi" 16#include "exynos5800.dtsi"
16 17
17/ { 18/ {
@@ -150,7 +151,7 @@
150 status = "okay"; 151 status = "okay";
151 clock-frequency = <400000>; 152 clock-frequency = <400000>;
152 153
153 max77802-pmic@9 { 154 max77802: max77802-pmic@9 {
154 compatible = "maxim,max77802"; 155 compatible = "maxim,max77802";
155 interrupt-parent = <&gpx3>; 156 interrupt-parent = <&gpx3>;
156 interrupts = <1 IRQ_TYPE_NONE>; 157 interrupts = <1 IRQ_TYPE_NONE>;
@@ -548,7 +549,7 @@
548 status = "okay"; 549 status = "okay";
549 num-slots = <1>; 550 num-slots = <1>;
550 broken-cd; 551 broken-cd;
551 caps2-mmc-hs200-1_8v; 552 mmc-hs200-1_8v;
552 cap-mmc-highspeed; 553 cap-mmc-highspeed;
553 non-removable; 554 non-removable;
554 card-detect-delay = <200>; 555 card-detect-delay = <200>;
@@ -715,6 +716,8 @@
715 716
716&rtc { 717&rtc {
717 status = "okay"; 718 status = "okay";
719 clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
720 clock-names = "rtc", "rtc_src";
718}; 721};
719 722
720&spi_2 { 723&spi_2 {
diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
index 05b44c272c9a..721b09238f58 100644
--- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
+++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts
@@ -51,3 +51,36 @@
51&uart0 { 51&uart0 {
52 status = "okay"; 52 status = "okay";
53}; 53};
54
55&gmac0 {
56 #address-cells = <1>;
57 #size-cells = <0>;
58 phy-handle = <&phy2>;
59 phy-mode = "mii";
60 /* Placeholder, overwritten by bootloader */
61 mac-address = [00 00 00 00 00 00];
62 status = "okay";
63
64 phy2: ethernet-phy@2 {
65 reg = <2>;
66 };
67};
68
69&gmac1 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 phy-handle = <&phy1>;
73 phy-mode = "rgmii";
74 /* Placeholder, overwritten by bootloader */
75 mac-address = [00 00 00 00 00 00];
76 status = "okay";
77
78 phy1: ethernet-phy@1 {
79 reg = <1>;
80 };
81};
82
83&ahci {
84 phys = <&sata_phy>;
85 phy-names = "sata-phy";
86};
diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi
index f85ba2924ff7..c52722b14e4a 100644
--- a/arch/arm/boot/dts/hisi-x5hd2.dtsi
+++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi
@@ -131,6 +131,249 @@
131 clock-names = "apb_pclk"; 131 clock-names = "apb_pclk";
132 status = "disabled"; 132 status = "disabled";
133 }; 133 };
134
135 gpio0: gpio@b20000 {
136 compatible = "arm,pl061", "arm,primecell";
137 reg = <0xb20000 0x1000>;
138 interrupts = <0 108 0x4>;
139 gpio-controller;
140 #gpio-cells = <2>;
141 clocks = <&clock HIX5HD2_FIXED_100M>;
142 clock-names = "apb_pclk";
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 status = "disabled";
146 };
147
148 gpio1: gpio@b21000 {
149 compatible = "arm,pl061", "arm,primecell";
150 reg = <0xb21000 0x1000>;
151 interrupts = <0 109 0x4>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 clocks = <&clock HIX5HD2_FIXED_100M>;
155 clock-names = "apb_pclk";
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 status = "disabled";
159 };
160
161 gpio2: gpio@b22000 {
162 compatible = "arm,pl061", "arm,primecell";
163 reg = <0xb22000 0x1000>;
164 interrupts = <0 110 0x4>;
165 gpio-controller;
166 #gpio-cells = <2>;
167 clocks = <&clock HIX5HD2_FIXED_100M>;
168 clock-names = "apb_pclk";
169 interrupt-controller;
170 #interrupt-cells = <2>;
171 status = "disabled";
172 };
173
174 gpio3: gpio@b23000 {
175 compatible = "arm,pl061", "arm,primecell";
176 reg = <0xb23000 0x1000>;
177 interrupts = <0 111 0x4>;
178 gpio-controller;
179 #gpio-cells = <2>;
180 clocks = <&clock HIX5HD2_FIXED_100M>;
181 clock-names = "apb_pclk";
182 interrupt-controller;
183 #interrupt-cells = <2>;
184 status = "disabled";
185 };
186
187 gpio4: gpio@b24000 {
188 compatible = "arm,pl061", "arm,primecell";
189 reg = <0xb24000 0x1000>;
190 interrupts = <0 112 0x4>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 clocks = <&clock HIX5HD2_FIXED_100M>;
194 clock-names = "apb_pclk";
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 status = "disabled";
198 };
199
200 gpio5: gpio@004000 {
201 compatible = "arm,pl061", "arm,primecell";
202 reg = <0x004000 0x1000>;
203 interrupts = <0 113 0x4>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 clocks = <&clock HIX5HD2_FIXED_100M>;
207 clock-names = "apb_pclk";
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 status = "disabled";
211 };
212
213 gpio6: gpio@b26000 {
214 compatible = "arm,pl061", "arm,primecell";
215 reg = <0xb26000 0x1000>;
216 interrupts = <0 114 0x4>;
217 gpio-controller;
218 #gpio-cells = <2>;
219 clocks = <&clock HIX5HD2_FIXED_100M>;
220 clock-names = "apb_pclk";
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 status = "disabled";
224 };
225
226 gpio7: gpio@b27000 {
227 compatible = "arm,pl061", "arm,primecell";
228 reg = <0xb27000 0x1000>;
229 interrupts = <0 115 0x4>;
230 gpio-controller;
231 #gpio-cells = <2>;
232 clocks = <&clock HIX5HD2_FIXED_100M>;
233 clock-names = "apb_pclk";
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 status = "disabled";
237 };
238
239 gpio8: gpio@b28000 {
240 compatible = "arm,pl061", "arm,primecell";
241 reg = <0xb28000 0x1000>;
242 interrupts = <0 116 0x4>;
243 gpio-controller;
244 #gpio-cells = <2>;
245 clocks = <&clock HIX5HD2_FIXED_100M>;
246 clock-names = "apb_pclk";
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 status = "disabled";
250 };
251
252 gpio9: gpio@b29000 {
253 compatible = "arm,pl061", "arm,primecell";
254 reg = <0xb29000 0x1000>;
255 interrupts = <0 117 0x4>;
256 gpio-controller;
257 #gpio-cells = <2>;
258 clocks = <&clock HIX5HD2_FIXED_100M>;
259 clock-names = "apb_pclk";
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 status = "disabled";
263 };
264
265 gpio10: gpio@b2a000 {
266 compatible = "arm,pl061", "arm,primecell";
267 reg = <0xb2a000 0x1000>;
268 interrupts = <0 118 0x4>;
269 gpio-controller;
270 #gpio-cells = <2>;
271 clocks = <&clock HIX5HD2_FIXED_100M>;
272 clock-names = "apb_pclk";
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 status = "disabled";
276 };
277
278 gpio11: gpio@b2b000 {
279 compatible = "arm,pl061", "arm,primecell";
280 reg = <0xb2b000 0x1000>;
281 interrupts = <0 119 0x4>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 clocks = <&clock HIX5HD2_FIXED_100M>;
285 clock-names = "apb_pclk";
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 status = "disabled";
289 };
290
291 gpio12: gpio@b2c000 {
292 compatible = "arm,pl061", "arm,primecell";
293 reg = <0xb2c000 0x1000>;
294 interrupts = <0 120 0x4>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 clocks = <&clock HIX5HD2_FIXED_100M>;
298 clock-names = "apb_pclk";
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 status = "disabled";
302 };
303
304 gpio13: gpio@b2d000 {
305 compatible = "arm,pl061", "arm,primecell";
306 reg = <0xb2d000 0x1000>;
307 interrupts = <0 121 0x4>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 clocks = <&clock HIX5HD2_FIXED_100M>;
311 clock-names = "apb_pclk";
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 status = "disabled";
315 };
316
317 gpio14: gpio@b2e000 {
318 compatible = "arm,pl061", "arm,primecell";
319 reg = <0xb2e000 0x1000>;
320 interrupts = <0 122 0x4>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 clocks = <&clock HIX5HD2_FIXED_100M>;
324 clock-names = "apb_pclk";
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 status = "disabled";
328 };
329
330 gpio15: gpio@b2f000 {
331 compatible = "arm,pl061", "arm,primecell";
332 reg = <0xb2f000 0x1000>;
333 interrupts = <0 123 0x4>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 clocks = <&clock HIX5HD2_FIXED_100M>;
337 clock-names = "apb_pclk";
338 interrupt-controller;
339 #interrupt-cells = <2>;
340 status = "disabled";
341 };
342
343 gpio16: gpio@b30000 {
344 compatible = "arm,pl061", "arm,primecell";
345 reg = <0xb30000 0x1000>;
346 interrupts = <0 124 0x4>;
347 gpio-controller;
348 #gpio-cells = <2>;
349 clocks = <&clock HIX5HD2_FIXED_100M>;
350 clock-names = "apb_pclk";
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 status = "disabled";
354 };
355
356 gpio17: gpio@b31000 {
357 compatible = "arm,pl061", "arm,primecell";
358 reg = <0xb31000 0x1000>;
359 interrupts = <0 125 0x4>;
360 gpio-controller;
361 #gpio-cells = <2>;
362 clocks = <&clock HIX5HD2_FIXED_100M>;
363 clock-names = "apb_pclk";
364 interrupt-controller;
365 #interrupt-cells = <2>;
366 status = "disabled";
367 };
368
369 wdt0: watchdog@a2c000 {
370 compatible = "arm,sp805", "arm,primecell";
371 arm,primecell-periphid = <0x00141805>;
372 reg = <0xa2c000 0x1000>;
373 interrupts = <0 29 4>;
374 clocks = <&clock HIX5HD2_WDG0_RST>;
375 clock-names = "apb_pclk";
376 };
134 }; 377 };
135 378
136 local_timer@00a00600 { 379 local_timer@00a00600 {
@@ -148,9 +391,15 @@
148 }; 391 };
149 392
150 sysctrl: system-controller@00000000 { 393 sysctrl: system-controller@00000000 {
151 compatible = "hisilicon,sysctrl"; 394 compatible = "hisilicon,sysctrl", "syscon";
152 reg = <0x00000000 0x1000>; 395 reg = <0x00000000 0x1000>;
153 reboot-offset = <0x4>; 396 };
397
398 reboot {
399 compatible = "syscon-reboot";
400 regmap = <&sysctrl>;
401 offset = <0x4>;
402 mask = <0xdeadbeef>;
154 }; 403 };
155 404
156 cpuctrl@00a22000 { 405 cpuctrl@00a22000 {
@@ -166,5 +415,142 @@
166 #clock-cells = <1>; 415 #clock-cells = <1>;
167 }; 416 };
168 }; 417 };
418
419 /* unremovable emmc as mmcblk0 */
420 mmc: mmc@1830000 {
421 compatible = "snps,dw-mshc";
422 reg = <0x1830000 0x1000>;
423 interrupts = <0 35 4>;
424 clocks = <&clock HIX5HD2_MMC_CIU_RST>,
425 <&clock HIX5HD2_MMC_BIU_CLK>;
426 clock-names = "ciu", "biu";
427 };
428
429 sd: mmc@1820000 {
430 compatible = "snps,dw-mshc";
431 reg = <0x1820000 0x1000>;
432 interrupts = <0 34 4>;
433 clocks = <&clock HIX5HD2_SD_CIU_RST>,
434 <&clock HIX5HD2_SD_BIU_CLK>;
435 clock-names = "ciu","biu";
436 };
437
438 gmac0: ethernet@1840000 {
439 compatible = "hisilicon,hix5hd2-gmac";
440 reg = <0x1840000 0x1000>,<0x184300c 0x4>;
441 interrupts = <0 71 4>;
442 clocks = <&clock HIX5HD2_MAC0_CLK>;
443 status = "disabled";
444 };
445
446 gmac1: ethernet@1841000 {
447 compatible = "hisilicon,hix5hd2-gmac";
448 reg = <0x1841000 0x1000>,<0x1843010 0x4>;
449 interrupts = <0 72 4>;
450 clocks = <&clock HIX5HD2_MAC1_CLK>;
451 status = "disabled";
452 };
453
454 usb0: ehci@1890000 {
455 compatible = "generic-ehci";
456 reg = <0x1890000 0x1000>;
457 interrupts = <0 66 4>;
458 clocks = <&clock HIX5HD2_USB_CLK>;
459 };
460
461 usb1: ohci@1880000 {
462 compatible = "generic-ohci";
463 reg = <0x1880000 0x1000>;
464 interrupts = <0 67 4>;
465 clocks = <&clock HIX5HD2_USB_CLK>;
466 };
467
468 peripheral_ctrl: syscon@a20000 {
469 compatible = "syscon";
470 reg = <0xa20000 0x1000>;
471 };
472
473 sata_phy: phy@1900000 {
474 compatible = "hisilicon,hix5hd2-sata-phy";
475 reg = <0x1900000 0x10000>;
476 #phy-cells = <0>;
477 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
478 hisilicon,power-reg = <0x8 10>;
479 };
480
481 ahci: sata@1900000 {
482 compatible = "hisilicon,hisi-ahci";
483 reg = <0x1900000 0x10000>;
484 interrupts = <0 70 4>;
485 clocks = <&clock HIX5HD2_SATA_CLK>;
486 };
487
488 ir: ir@001000 {
489 compatible = "hisilicon,hix5hd2-ir";
490 reg = <0x001000 0x1000>;
491 interrupts = <0 47 4>;
492 clocks = <&clock HIX5HD2_FIXED_24M>;
493 hisilicon,power-syscon = <&sysctrl>;
494 };
495
496 i2c0: i2c@b10000 {
497 compatible = "hisilicon,hix5hd2-i2c";
498 reg = <0xb10000 0x1000>;
499 interrupts = <0 38 4>;
500 clocks = <&clock HIX5HD2_I2C0_RST>;
501 #address-cells = <1>;
502 #size-cells = <0>;
503 status = "disabled";
504 };
505
506 i2c1: i2c@b11000 {
507 compatible = "hisilicon,hix5hd2-i2c";
508 reg = <0xb11000 0x1000>;
509 interrupts = <0 39 4>;
510 clocks = <&clock HIX5HD2_I2C1_RST>;
511 #address-cells = <1>;
512 #size-cells = <0>;
513 status = "disabled";
514 };
515
516 i2c2: i2c@b12000 {
517 compatible = "hisilicon,hix5hd2-i2c";
518 reg = <0xb12000 0x1000>;
519 interrupts = <0 40 4>;
520 clocks = <&clock HIX5HD2_I2C2_RST>;
521 #address-cells = <1>;
522 #size-cells = <0>;
523 status = "disabled";
524 };
525
526 i2c3: i2c@b13000 {
527 compatible = "hisilicon,hix5hd2-i2c";
528 reg = <0xb13000 0x1000>;
529 interrupts = <0 41 4>;
530 clocks = <&clock HIX5HD2_I2C3_RST>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 status = "disabled";
534 };
535
536 i2c4: i2c@b16000 {
537 compatible = "hisilicon,hix5hd2-i2c";
538 reg = <0xb16000 0x1000>;
539 interrupts = <0 43 4>;
540 clocks = <&clock HIX5HD2_I2C4_RST>;
541 #address-cells = <1>;
542 #size-cells = <0>;
543 status = "disabled";
544 };
545
546 i2c5: i2c@b17000 {
547 compatible = "hisilicon,hix5hd2-i2c";
548 reg = <0xb17000 0x1000>;
549 interrupts = <0 44 4>;
550 clocks = <&clock HIX5HD2_I2C5_RST>;
551 #address-cells = <1>;
552 #size-cells = <0>;
553 status = "disabled";
554 };
169 }; 555 };
170}; 556};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 92660e1fe1fc..c0116cffc513 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -214,7 +214,9 @@
214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>; 215 reg = <0x70014000 0x4000>;
216 interrupts = <30>; 216 interrupts = <30>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
218 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
219 clock-names = "ipg", "baud";
218 dmas = <&sdma 24 1 0>, 220 dmas = <&sdma 24 1 0>,
219 <&sdma 25 1 0>; 221 <&sdma 25 1 0>;
220 dma-names = "rx", "tx"; 222 dma-names = "rx", "tx";
@@ -504,7 +506,9 @@
504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 506 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
505 reg = <0x83fcc000 0x4000>; 507 reg = <0x83fcc000 0x4000>;
506 interrupts = <29>; 508 interrupts = <29>;
507 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 509 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
510 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
511 clock-names = "ipg", "baud";
508 dmas = <&sdma 28 0 0>, 512 dmas = <&sdma 28 0 0>,
509 <&sdma 29 0 0>; 513 <&sdma 29 0 0>;
510 dma-names = "rx", "tx"; 514 dma-names = "rx", "tx";
@@ -560,7 +564,9 @@
560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 564 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
561 reg = <0x83fe8000 0x4000>; 565 reg = <0x83fe8000 0x4000>;
562 interrupts = <96>; 566 interrupts = <96>;
563 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 567 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
568 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
569 clock-names = "ipg", "baud";
564 dmas = <&sdma 46 0 0>, 570 dmas = <&sdma 46 0 0>,
565 <&sdma 47 0 0>; 571 <&sdma 47 0 0>;
566 dma-names = "rx", "tx"; 572 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index f91725b2e8ab..a30bddfdbdb6 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -46,10 +46,21 @@
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 cpu@0 { 49 cpu0: cpu@0 {
50 device_type = "cpu"; 50 device_type = "cpu";
51 compatible = "arm,cortex-a8"; 51 compatible = "arm,cortex-a8";
52 reg = <0x0>; 52 reg = <0x0>;
53 clocks = <&clks IMX5_CLK_ARM>;
54 clock-latency = <61036>;
55 voltage-tolerance = <5>;
56 operating-points = <
57 /* kHz */
58 166666 850000
59 400000 900000
60 800000 1050000
61 1000000 1200000
62 1200000 1300000
63 >;
53 }; 64 };
54 }; 65 };
55 66
@@ -227,7 +238,9 @@
227 "fsl,imx21-ssi"; 238 "fsl,imx21-ssi";
228 reg = <0x50014000 0x4000>; 239 reg = <0x50014000 0x4000>;
229 interrupts = <30>; 240 interrupts = <30>;
230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 241 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
242 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
243 clock-names = "ipg", "baud";
231 dmas = <&sdma 24 1 0>, 244 dmas = <&sdma 24 1 0>,
232 <&sdma 25 1 0>; 245 <&sdma 25 1 0>;
233 dma-names = "rx", "tx"; 246 dma-names = "rx", "tx";
@@ -675,7 +688,9 @@
675 "fsl,imx21-ssi"; 688 "fsl,imx21-ssi";
676 reg = <0x63fcc000 0x4000>; 689 reg = <0x63fcc000 0x4000>;
677 interrupts = <29>; 690 interrupts = <29>;
678 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 691 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
692 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
693 clock-names = "ipg", "baud";
679 dmas = <&sdma 28 0 0>, 694 dmas = <&sdma 28 0 0>,
680 <&sdma 29 0 0>; 695 <&sdma 29 0 0>;
681 dma-names = "rx", "tx"; 696 dma-names = "rx", "tx";
@@ -703,7 +718,9 @@
703 "fsl,imx21-ssi"; 718 "fsl,imx21-ssi";
704 reg = <0x63fe8000 0x4000>; 719 reg = <0x63fe8000 0x4000>;
705 interrupts = <96>; 720 interrupts = <96>;
706 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 721 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
722 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
723 clock-names = "ipg", "baud";
707 dmas = <&sdma 46 0 0>, 724 dmas = <&sdma 46 0 0>,
708 <&sdma 47 0 0>; 725 <&sdma 47 0 0>;
709 dma-names = "rx", "tx"; 726 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index b453e0e28aee..1ac2fe732867 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -13,6 +13,10 @@
13#include "imx6qdl.dtsi" 13#include "imx6qdl.dtsi"
14 14
15/ { 15/ {
16 aliases {
17 i2c3 = &i2c4;
18 };
19
16 cpus { 20 cpus {
17 #address-cells = <1>; 21 #address-cells = <1>;
18 #size-cells = <0>; 22 #size-cells = <0>;
@@ -114,3 +118,7 @@
114 "di0_sel", "di1_sel", 118 "di0_sel", "di1_sel",
115 "di0", "di1"; 119 "di0", "di1";
116}; 120};
121
122&vpu {
123 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
124};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
new file mode 100644
index 000000000000..a43abfa21e33
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -0,0 +1,432 @@
1/*
2 * Copyright 2014 Soeren Moch <smoch@web.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49
50#include "imx6q.dtsi"
51#include <dt-bindings/gpio/gpio.h>
52#include <dt-bindings/input/input.h>
53
54/ {
55 model = "TBS2910 Matrix ARM mini PC";
56 compatible = "tbs,imx6q-tbs2910", "fsl,imx6q";
57
58 chosen {
59 stdout-path = &uart1;
60 };
61
62 memory {
63 reg = <0x10000000 0x80000000>;
64 };
65
66 fan {
67 compatible = "gpio-fan";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_gpio_fan>;
70 gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
71 gpio-fan,speed-map = <0 0
72 3000 1>;
73 };
74
75 ir_recv {
76 compatible = "gpio-ir-receiver";
77 gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_ir>;
80 };
81
82 leds {
83 compatible = "gpio-leds";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_gpio_leds>;
86
87 blue {
88 label = "blue_status_led";
89 gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
90 default-state = "keep";
91 };
92 };
93
94 regulators {
95 compatible = "simple-bus";
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 reg_2p5v: regulator@0 {
100 compatible = "regulator-fixed";
101 reg = <0>;
102 regulator-name = "2P5V";
103 regulator-min-microvolt = <2500000>;
104 regulator-max-microvolt = <2500000>;
105 };
106
107 reg_3p3v: regulator@1 {
108 compatible = "regulator-fixed";
109 reg = <1>;
110 regulator-name = "3P3V";
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 };
114
115 reg_5p0v: regulator@2 {
116 compatible = "regulator-fixed";
117 reg = <2>;
118 regulator-name = "5P0V";
119 regulator-min-microvolt = <5000000>;
120 regulator-max-microvolt = <5000000>;
121 };
122 };
123
124 sound-sgtl5000 {
125 audio-codec = <&sgtl5000>;
126 audio-routing =
127 "MIC_IN", "Mic Jack",
128 "Mic Jack", "Mic Bias",
129 "Headphone Jack", "HP_OUT";
130 compatible = "fsl,imx-audio-sgtl5000";
131 model = "On-board Codec";
132 mux-ext-port = <3>;
133 mux-int-port = <1>;
134 ssi-controller = <&ssi1>;
135 };
136
137 sound-spdif {
138 compatible = "fsl,imx-audio-spdif";
139 model = "On-board SPDIF";
140 spdif-controller = <&spdif>;
141 spdif-out;
142 };
143};
144
145&audmux {
146 status = "okay";
147};
148
149&fec {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_enet>;
152 phy-mode = "rgmii";
153 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
154 status = "okay";
155};
156
157&hdmi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_hdmi>;
160 ddc-i2c-bus = <&i2c2>;
161 status = "okay";
162};
163
164&i2c1 {
165 clock-frequency = <100000>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c1>;
168 status = "okay";
169
170 sgtl5000: sgtl5000@0a {
171 clocks = <&clks 201>;
172 compatible = "fsl,sgtl5000";
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_sgtl5000>;
175 reg = <0x0a>;
176 VDDA-supply = <&reg_2p5v>;
177 VDDIO-supply = <&reg_3p3v>;
178 };
179};
180
181&i2c2 {
182 clock-frequency = <100000>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&pinctrl_i2c2>;
185 status = "okay";
186};
187
188&i2c3 {
189 clock-frequency = <100000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c3>;
192 status = "okay";
193
194 rtc: ds1307@68 {
195 compatible = "dallas,ds1307";
196 reg = <0x68>;
197 };
198};
199
200&pcie {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_pcie>;
203 reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
204 status = "okay";
205};
206
207&sata {
208 status = "okay";
209};
210
211&snvs_poweroff {
212 status = "okay";
213};
214
215&spdif {
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_spdif>;
218 status = "okay";
219};
220
221&ssi1 {
222 status = "okay";
223};
224
225&uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_uart1>;
228 status = "okay";
229};
230
231&uart2 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_uart2>;
234 status = "okay";
235};
236
237&usbh1 {
238 vbus-supply = <&reg_5p0v>;
239 status = "okay";
240};
241
242&usbotg {
243 vbus-supply = <&reg_5p0v>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_usbotg>;
246 disable-over-current;
247 status = "okay";
248};
249
250&usdhc2 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_usdhc2>;
253 bus-width = <4>;
254 cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
255 vmmc-supply = <&reg_3p3v>;
256 status = "okay";
257};
258
259&usdhc3 {
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_usdhc3>;
262 bus-width = <4>;
263 cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
264 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
265 vmmc-supply = <&reg_3p3v>;
266 status = "okay";
267};
268
269&usdhc4 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_usdhc4>;
272 bus-width = <8>;
273 non-removable;
274 no-1-8-v;
275 status = "okay";
276};
277
278&iomuxc {
279 imx6q-tbs2910 {
280 pinctrl_enet: enetgrp {
281 fsl,pins = <
282 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
283 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
284 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
285 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
286 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
287 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
288 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
289 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
290 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
291 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
292 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
293 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
294 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
295 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
296 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
297 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
298 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
299 >;
300 };
301
302 pinctrl_hdmi: hdmigrp {
303 fsl,pins = <
304 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
305 >;
306 };
307
308 pinctrl_i2c1: i2c1grp {
309 fsl,pins = <
310 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
311 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
312 >;
313 };
314
315 pinctrl_i2c2: i2c2grp {
316 fsl,pins = <
317 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
318 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
319 >;
320 };
321
322 pinctrl_i2c3: i2c3grp {
323 fsl,pins = <
324 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
325 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
326 >;
327 };
328
329 pinctrl_ir: irgrp {
330 fsl,pins = <
331 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
332 >;
333 };
334
335 pinctrl_pcie: pciegrp {
336 fsl,pins = <
337 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
338 >;
339 };
340
341 pinctrl_sgtl5000: sgtl5000grp {
342 fsl,pins = <
343 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
344 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
345 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
346 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
347 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
348 >;
349 };
350
351 pinctrl_spdif: spdifgrp {
352 fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091
353 >;
354 };
355
356 pinctrl_uart1: uart1grp {
357 fsl,pins = <
358 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
359 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
360 >;
361 };
362
363 pinctrl_uart2: uart2grp {
364 fsl,pins = <
365 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
366 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
367 >;
368 };
369
370 pinctrl_usbotg: usbotggrp {
371 fsl,pins = <
372 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
373 >;
374 };
375
376 pinctrl_usdhc2: usdhc2grp {
377 fsl,pins = <
378 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
379 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
380 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
381 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
382 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
383 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
384 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
385 >;
386 };
387
388 pinctrl_usdhc3: usdhc3grp {
389 fsl,pins = <
390 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
391 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
392 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
393 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
394 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
395 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
396 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
397 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
398 >;
399 };
400
401 pinctrl_usdhc4: usdhc4grp {
402 fsl,pins = <
403 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
404 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
405 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
406 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
407 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
408 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
409 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
410 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
411 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
412 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
413 >;
414 };
415 };
416
417 gpio_fan {
418 pinctrl_gpio_fan: gpiofangrp {
419 fsl,pins = <
420 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
421 >;
422 };
423 };
424
425 gpio_leds {
426 pinctrl_gpio_leds: gpioledsgrp {
427 fsl,pins = <
428 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
429 >;
430 };
431 };
432};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9f3646d1760..85f72e6b5bad 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -308,3 +308,7 @@
308 }; 308 };
309 }; 309 };
310}; 310};
311
312&vpu {
313 compatible = "fsl,imx6q-vpu", "cnm,coda960";
314};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..585b4f6986c1 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,17 +9,103 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
12/ { 14/ {
13 chosen { 15 chosen {
14 linux,stdout-path = &uart4; 16 linux,stdout-path = &uart4;
15 }; 17 };
18
19 regulators {
20 sound_1v8: regulator@2 {
21 compatible = "regulator-fixed";
22 reg = <2>;
23 regulator-name = "i2s-audio-1v8";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 };
27
28 sound_3v3: regulator@3 {
29 compatible = "regulator-fixed";
30 reg = <3>;
31 regulator-name = "i2s-audio-3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 };
35 };
36
37 tlv320_mclk: oscillator {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <19200000>;
41 clock-output-names = "tlv320-mclk";
42 };
43
44 sound {
45 compatible = "simple-audio-card";
46 simple-audio-card,name = "OnboardTLV320AIC3007";
47 simple-audio-card,format = "i2s";
48 simple-audio-card,bitclock-master = <&dailink_master>;
49 simple-audio-card,frame-master = <&dailink_master>;
50 simple-audio-card,widgets =
51 "Microphone", "Mic Jack",
52 "Line", "Line In",
53 "Line", "Line Out",
54 "Speaker", "Speaker",
55 "Headphone", "Headphone Jack";
56 simple-audio-card,routing =
57 "Line Out", "LLOUT",
58 "Line Out", "RLOUT",
59 "Speaker", "SPOP",
60 "Speaker", "SPOM",
61 "Headphone Jack", "HPLOUT",
62 "Headphone Jack", "HPROUT",
63 "MIC3L", "Mic Jack",
64 "MIC3R", "Mic Jack",
65 "Mic Jack", "Mic Bias",
66 "LINE1L", "Line In",
67 "LINE1R", "Line In";
68
69 simple-audio-card,cpu {
70 sound-dai = <&ssi2>;
71 };
72
73 dailink_master: simple-audio-card,codec {
74 sound-dai = <&codec>;
75 clocks = <&tlv320_mclk>;
76 };
77 };
78
16}; 79};
17 80
18&fec { 81&audmux {
19 status = "okay"; 82 status = "okay";
83
84 ssi2 {
85 fsl,audmux-port = <1>;
86 fsl,port-config = <
87 (IMX_AUDMUX_V2_PTCR_TFSDIR |
88 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
89 IMX_AUDMUX_V2_PTCR_TCLKDIR |
90 IMX_AUDMUX_V2_PTCR_TCSEL(4))
91 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
92 >;
93 };
94
95 pins5 {
96 fsl,audmux-port = <4>;
97 fsl,port-config = <
98 0x00000000
99 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
100 >;
101 };
20}; 102};
21 103
22&gpmi { 104&can1 {
105 status = "okay";
106};
107
108&fec {
23 status = "okay"; 109 status = "okay";
24}; 110};
25 111
@@ -28,14 +114,18 @@
28}; 114};
29 115
30&i2c2 { 116&i2c2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_i2c2>;
33 clock-frequency = <100000>;
34 status = "okay"; 117 status = "okay";
35 118
36 tlv320@18 { 119 codec: tlv320@18 {
37 compatible = "ti,tlv320aic3x"; 120 compatible = "ti,tlv320aic3007";
121 #sound-dai-cells = <0>;
38 reg = <0x18>; 122 reg = <0x18>;
123 ai3x-micbias-vg = <2>;
124
125 AVDD-supply = <&sound_3v3>;
126 IOVDD-supply = <&sound_3v3>;
127 DRVDD-supply = <&sound_3v3>;
128 DVDD-supply = <&sound_1v8>;
39 }; 129 };
40 130
41 stmpe@41 { 131 stmpe@41 {
@@ -55,9 +145,14 @@
55}; 145};
56 146
57&i2c3 { 147&i2c3 {
58 pinctrl-names = "default"; 148 status = "okay";
59 pinctrl-0 = <&pinctrl_i2c3>; 149};
60 clock-frequency = <100000>; 150
151&pcie {
152 status = "okay";
153};
154
155&ssi2 {
61 status = "okay"; 156 status = "okay";
62}; 157};
63 158
@@ -84,19 +179,3 @@
84&usdhc3 { 179&usdhc3 {
85 status = "okay"; 180 status = "okay";
86}; 181};
87
88&iomuxc {
89 pinctrl_i2c2: i2c2grp {
90 fsl,pins = <
91 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
92 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
93 >;
94 };
95
96 pinctrl_i2c3: i2c3grp {
97 fsl,pins = <
98 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
99 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
100 >;
101 };
102};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..19cc269a08d4 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,18 @@
58 }; 58 };
59}; 59};
60 60
61&audmux {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_audmux>;
64 status = "disabled";
65};
66
67&can1 {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan1>;
70 status = "disabled";
71};
72
61&ecspi3 { 73&ecspi3 {
62 pinctrl-names = "default"; 74 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_ecspi3>; 75 pinctrl-0 = <&pinctrl_ecspi3>;
@@ -72,6 +84,22 @@
72 }; 84 };
73}; 85};
74 86
87&fec {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_enet>;
90 phy-mode = "rgmii";
91 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
92 phy-supply = <&vdd_eth_io_reg>;
93 status = "disabled";
94};
95
96&gpmi {
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_gpmi_nand>;
99 nand-on-flash-bbt;
100 status = "okay";
101};
102
75&i2c1 { 103&i2c1 {
76 pinctrl-names = "default"; 104 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_i2c1>; 105 pinctrl-0 = <&pinctrl_i2c1>;
@@ -85,8 +113,8 @@
85 pmic@58 { 113 pmic@58 {
86 compatible = "dlg,da9063"; 114 compatible = "dlg,da9063";
87 reg = <0x58>; 115 reg = <0x58>;
88 interrupt-parent = <&gpio4>; 116 interrupt-parent = <&gpio2>;
89 interrupts = <17 0x8>; /* active-low GPIO4_17 */ 117 interrupts = <9 0x8>; /* active-low GPIO2_9 */
90 118
91 regulators { 119 regulators {
92 vddcore_reg: bcore1 { 120 vddcore_reg: bcore1 {
@@ -162,6 +190,18 @@
162 }; 190 };
163}; 191};
164 192
193&i2c2 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_i2c2>;
196 clock-frequency = <100000>;
197};
198
199&i2c3 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c3>;
202 clock-frequency = <100000>;
203};
204
165&iomuxc { 205&iomuxc {
166 pinctrl-names = "default"; 206 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_hog>; 207 pinctrl-0 = <&pinctrl_hog>;
@@ -171,7 +211,7 @@
171 fsl,pins = < 211 fsl,pins = <
172 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 212 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
173 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ 213 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
174 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ 214 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
175 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ 215 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
176 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ 216 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
177 >; 217 >;
@@ -206,6 +246,13 @@
206 >; 246 >;
207 }; 247 };
208 248
249 pinctrl_flexcan1: flexcan1grp {
250 fsl,pins = <
251 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
252 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
253 >;
254 };
255
209 pinctrl_gpmi_nand: gpminandgrp { 256 pinctrl_gpmi_nand: gpminandgrp {
210 fsl,pins = < 257 fsl,pins = <
211 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 258 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
@@ -235,6 +282,24 @@
235 >; 282 >;
236 }; 283 };
237 284
285 pinctrl_i2c2: i2c2grp {
286 fsl,pins = <
287 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
288 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
289 >;
290 };
291
292 pinctrl_i2c3: i2c3grp {
293 fsl,pins = <
294 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
295 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
296 >;
297 };
298
299 pinctrl_pcie: pciegrp {
300 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
301 };
302
238 pinctrl_uart3: uart3grp { 303 pinctrl_uart3: uart3grp {
239 fsl,pins = < 304 fsl,pins = <
240 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 305 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
@@ -293,22 +358,22 @@
293 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 358 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
294 >; 359 >;
295 }; 360 };
296 };
297};
298 361
299&fec { 362 pinctrl_audmux: audmuxgrp {
300 pinctrl-names = "default"; 363 fsl,pins = <
301 pinctrl-0 = <&pinctrl_enet>; 364 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
302 phy-mode = "rgmii"; 365 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
303 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 366 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
304 phy-supply = <&vdd_eth_io_reg>; 367 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
305 status = "disabled"; 368 >;
369 };
370 };
306}; 371};
307 372
308&gpmi { 373&pcie {
309 pinctrl-names = "default"; 374 pinctrl-name = "default";
310 pinctrl-0 = <&pinctrl_gpmi_nand>; 375 pinctrl-0 = <&pinctrl_pcie>;
311 nand-on-flash-bbt; 376 reset-gpio = <&gpio4 17 0>;
312 status = "disabled"; 377 status = "disabled";
313}; 378};
314 379
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 5db4a2417d94..f1cd2147421d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -529,6 +529,10 @@
529 status = "okay"; 529 status = "okay";
530}; 530};
531 531
532&snvs_poweroff {
533 status = "okay";
534};
535
532&ssi2 { 536&ssi2 {
533 status = "okay"; 537 status = "okay";
534}; 538};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9596ed5867e6..4fc03b7f1cee 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -333,9 +333,17 @@
333 }; 333 };
334 334
335 vpu: vpu@02040000 { 335 vpu: vpu@02040000 {
336 compatible = "cnm,coda960";
336 reg = <0x02040000 0x3c000>; 337 reg = <0x02040000 0x3c000>;
337 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, 338 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
338 <0 12 IRQ_TYPE_LEVEL_HIGH>; 339 <0 12 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-names = "bit", "jpeg";
341 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
342 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
343 <&clks IMX6QDL_CLK_OCRAM>;
344 clock-names = "per", "ahb", "ocram";
345 resets = <&src 1>;
346 iram = <&ocram>;
339 }; 347 };
340 348
341 aipstz@0207c000 { /* AIPSTZ1 */ 349 aipstz@0207c000 { /* AIPSTZ1 */
@@ -657,6 +665,12 @@
657 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 665 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
658 <0 20 IRQ_TYPE_LEVEL_HIGH>; 666 <0 20 IRQ_TYPE_LEVEL_HIGH>;
659 }; 667 };
668
669 snvs_poweroff: snvs-poweroff@38 {
670 compatible = "fsl,sec-v4.0-poweroff";
671 reg = <0x38 0x4>;
672 status = "disabled";
673 };
660 }; 674 };
661 675
662 epit1: epit@020d0000 { /* EPIT1 */ 676 epit1: epit@020d0000 { /* EPIT1 */
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 898d14fd765f..fda4932faefd 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -580,6 +580,10 @@
580 status = "okay"; 580 status = "okay";
581}; 581};
582 582
583&snvs_poweroff {
584 status = "okay";
585};
586
583&ssi2 { 587&ssi2 {
584 status = "okay"; 588 status = "okay";
585}; 589};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index dfd83e6d8087..36ab8e054cee 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -574,6 +574,12 @@
574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 574 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
575 <0 20 IRQ_TYPE_LEVEL_HIGH>; 575 <0 20 IRQ_TYPE_LEVEL_HIGH>;
576 }; 576 };
577
578 snvs_poweroff: snvs-poweroff@38 {
579 compatible = "fsl,sec-v4.0-poweroff";
580 reg = <0x38 0x4>;
581 status = "disabled";
582 };
577 }; 583 };
578 584
579 epit1: epit@020d0000 { 585 epit1: epit@020d0000 {
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
index 82d6b34527b7..1e6e5cc1c14c 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -105,6 +105,30 @@
105 gpio = <&gpio3 27 0>; 105 gpio = <&gpio3 27 0>;
106 enable-active-high; 106 enable-active-high;
107 }; 107 };
108
109 reg_peri_3v3: regulator@5 {
110 compatible = "regulator-fixed";
111 reg = <5>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_peri_3v3>;
114 regulator-name = "peri_3v3";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
118 enable-active-high;
119 regulator-always-on;
120 };
121
122 reg_enet_3v3: regulator@6 {
123 compatible = "regulator-fixed";
124 reg = <6>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_enet_3v3>;
127 regulator-name = "enet_3v3";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
131 };
108 }; 132 };
109 133
110 sound { 134 sound {
@@ -133,6 +157,14 @@
133&fec1 { 157&fec1 {
134 pinctrl-names = "default"; 158 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_enet1>; 159 pinctrl-0 = <&pinctrl_enet1>;
160 phy-supply = <&reg_enet_3v3>;
161 phy-mode = "rgmii";
162 status = "okay";
163};
164
165&fec2 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_enet2>;
136 phy-mode = "rgmii"; 168 phy-mode = "rgmii";
137 status = "okay"; 169 status = "okay";
138}; 170};
@@ -304,6 +336,10 @@
304 status = "okay"; 336 status = "okay";
305}; 337};
306 338
339&snvs_poweroff {
340 status = "okay";
341};
342
307&ssi2 { 343&ssi2 {
308 status = "okay"; 344 status = "okay";
309}; 345};
@@ -394,6 +430,30 @@
394 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 430 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
395 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 431 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
396 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 432 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
433 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
434 >;
435 };
436
437 pinctrl_enet_3v3: enet3v3grp {
438 fsl,pins = <
439 MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
440 >;
441 };
442
443 pinctrl_enet2: enet2grp {
444 fsl,pins = <
445 MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
446 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
447 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
448 MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
449 MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
450 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
451 MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
452 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
453 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
454 MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
455 MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
456 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
397 >; 457 >;
398 }; 458 };
399 459
@@ -452,6 +512,12 @@
452 >; 512 >;
453 }; 513 };
454 514
515 pinctrl_peri_3v3: peri3v3grp {
516 fsl,pins = <
517 MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
518 >;
519 };
520
455 pinctrl_pwm3: pwm3grp-1 { 521 pinctrl_pwm3: pwm3grp-1 {
456 fsl,pins = < 522 fsl,pins = <
457 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 523 MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index f3e88c03b1e4..7a24fee1e7ae 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -671,6 +671,12 @@
671 reg = <0x34 0x58>; 671 reg = <0x34 0x58>;
672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 672 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
673 }; 673 };
674
675 snvs_poweroff: snvs-poweroff@38 {
676 compatible = "fsl,sec-v4.0-poweroff";
677 reg = <0x38 0x4>;
678 status = "disabled";
679 };
674 }; 680 };
675 681
676 epit1: epit@020d0000 { 682 epit1: epit@020d0000 {
@@ -877,7 +883,7 @@
877 }; 883 };
878 884
879 fec2: ethernet@021b4000 { 885 fec2: ethernet@021b4000 {
880 compatible = "fsl,imx6sx-fec"; 886 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
881 reg = <0x021b4000 0x4000>; 887 reg = <0x021b4000 0x4000>;
882 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 888 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 889 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
index c568f067604d..560d62150ade 100644
--- a/arch/arm/boot/dts/k2e-evm.dts
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -139,3 +139,15 @@
139 }; 139 };
140 }; 140 };
141}; 141};
142
143&mdio {
144 ethphy0: ethernet-phy@0 {
145 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
146 reg = <0>;
147 };
148
149 ethphy1: ethernet-phy@1 {
150 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
151 reg = <1>;
152 };
153};
diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi
index c358b4b9a073..5fc14683d6df 100644
--- a/arch/arm/boot/dts/k2e.dtsi
+++ b/arch/arm/boot/dts/k2e.dtsi
@@ -85,6 +85,51 @@
85 #gpio-cells = <2>; 85 #gpio-cells = <2>;
86 gpio,syscon-dev = <&devctrl 0x240>; 86 gpio,syscon-dev = <&devctrl 0x240>;
87 }; 87 };
88
89 pcie@21020000 {
90 compatible = "ti,keystone-pcie","snps,dw-pcie";
91 clocks = <&clkpcie1>;
92 clock-names = "pcie";
93 #address-cells = <3>;
94 #size-cells = <2>;
95 reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
96 ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
97 0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
98
99 device_type = "pci";
100 num-lanes = <2>;
101
102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0 0 0 7>;
104 interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
105 <0 0 0 2 &pcie_intc1 1>, /* INT B */
106 <0 0 0 3 &pcie_intc1 2>, /* INT C */
107 <0 0 0 4 &pcie_intc1 3>; /* INT D */
108
109 pcie_msi_intc1: msi-interrupt-controller {
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 interrupt-parent = <&gic>;
113 interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>,
116 <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>,
117 <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>,
118 <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>,
120 <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>;
121 };
122
123 pcie_intc1: legacy-interrupt-controller {
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 interrupt-parent = <&gic>;
127 interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
128 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
129 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
130 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>;
131 };
132 };
88 }; 133 };
89}; 134};
90 135
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
index fec43128a2e0..85cc7f2872d7 100644
--- a/arch/arm/boot/dts/k2l-evm.dts
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -116,3 +116,15 @@
116 }; 116 };
117 }; 117 };
118}; 118};
119
120&mdio {
121 ethphy0: ethernet-phy@0 {
122 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
123 reg = <0>;
124 };
125
126 ethphy1: ethernet-phy@1 {
127 compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22";
128 reg = <1>;
129 };
130};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 5d3e83fa2242..c06542b2c954 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -285,5 +285,50 @@
285 #interrupt-cells = <1>; 285 #interrupt-cells = <1>;
286 ti,syscon-dev = <&devctrl 0x2a0>; 286 ti,syscon-dev = <&devctrl 0x2a0>;
287 }; 287 };
288
289 pcie@21800000 {
290 compatible = "ti,keystone-pcie", "snps,dw-pcie";
291 clocks = <&clkpcie>;
292 clock-names = "pcie";
293 #address-cells = <3>;
294 #size-cells = <2>;
295 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
296 ranges = <0x81000000 0 0 0x23250000 0 0x4000
297 0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
298
299 device_type = "pci";
300 num-lanes = <2>;
301
302 #interrupt-cells = <1>;
303 interrupt-map-mask = <0 0 0 7>;
304 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
305 <0 0 0 2 &pcie_intc0 1>, /* INT B */
306 <0 0 0 3 &pcie_intc0 2>, /* INT C */
307 <0 0 0 4 &pcie_intc0 3>; /* INT D */
308
309 pcie_msi_intc0: msi-interrupt-controller {
310 interrupt-controller;
311 #interrupt-cells = <1>;
312 interrupt-parent = <&gic>;
313 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
314 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
315 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
316 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
317 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
318 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
319 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
320 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
321 };
322
323 pcie_intc0: legacy-interrupt-controller {
324 interrupt-controller;
325 #interrupt-cells = <1>;
326 interrupt-parent = <&gic>;
327 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
330 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
331 };
332 };
288 }; 333 };
289}; 334};
diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts
new file mode 100644
index 000000000000..786959ee9cbe
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dir665.dts
@@ -0,0 +1,278 @@
1/*
2 * Copyright (C) 2014 Claudio Leite <leitec@staticky.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9/dts-v1/;
10
11#include "kirkwood.dtsi"
12#include "kirkwood-6281.dtsi"
13
14/ {
15 model = "D-Link DIR-665";
16 compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood";
17
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x8000000>; /* 128 MB */
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,115200n8 earlyprintk";
25 stdout-path = &uart0;
26 };
27
28 mbus {
29 pcie-controller {
30 status = "okay";
31
32 pcie@1,0 {
33 status = "okay";
34 };
35 };
36 };
37
38 ocp@f1000000 {
39 pinctrl: pin-controller@10000 {
40 pinctrl-0 =< &pmx_led_usb
41 &pmx_led_internet_blue
42 &pmx_led_internet_amber
43 &pmx_led_5g &pmx_led_status_blue
44 &pmx_led_wps &pmx_led_status_amber
45 &pmx_led_24g
46 &pmx_btn_restart &pmx_btn_wps>;
47 pinctrl-names = "default";
48
49 pmx_led_usb: pmx-led-usb {
50 marvell,pins = "mpp12";
51 marvell,function = "gpio";
52 };
53 pmx_led_internet_blue: pmx-led-internet-blue {
54 marvell,pins = "mpp42";
55 marvell,function = "gpio";
56 };
57 pmx_led_internet_amber: pmx-led-internet-amber {
58 marvell,pins = "mpp43";
59 marvell,function = "gpio";
60 };
61 pmx_led_5g: pmx-led-5g {
62 marvell,pins = "mpp44";
63 marvell,function = "gpio";
64 };
65 pmx_led_status_blue: pmx-led-status-blue {
66 marvell,pins = "mpp45";
67 marvell,function = "gpio";
68 };
69 pmx_led_wps: pmx-led-wps {
70 marvell,pins = "mpp47";
71 marvell,function = "gpio";
72 };
73 pmx_led_status_amber: pmx-led-status-amber {
74 marvell,pins = "mpp48";
75 marvell,function = "gpio";
76 };
77 pmx_led_24g: pmx-led-24g {
78 marvell,pins = "mpp49";
79 marvell,function = "gpio";
80 };
81 pmx_btn_restart: pmx-btn-restart {
82 marvell,pins = "mpp28";
83 marvell,function = "gpio";
84 };
85 pmx_btn_wps: pmx-btn-wps {
86 marvell,pins = "mpp46";
87 marvell,function = "gpio";
88 };
89 };
90
91 spi@10600 {
92 status = "okay";
93 m25p80@0 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "mxicy,mx25l12805d";
97 spi-max-frequency = <50000000>;
98 reg = <0>;
99
100 partition@0 {
101 label = "uboot";
102 reg = <0x0 0x30000>;
103 read-only;
104 };
105
106 partition@30000 {
107 label = "nvram";
108 reg = <0x30000 0x10000>;
109 read-only;
110 };
111
112 partition@40000 {
113 label = "kernel";
114 reg = <0x40000 0x180000>;
115 };
116
117 partition@1c0000 {
118 label = "rootfs";
119 reg = <0x1c0000 0xe00000>;
120 };
121
122 cal_data: partition@fc0000 {
123 label = "cal_data";
124 reg = <0xfc0000 0x10000>;
125 read-only;
126 };
127
128 partition@fd0000 {
129 label = "lang_pack";
130 reg = <0xfd0000 0x30000>;
131 read-only;
132 };
133 };
134 };
135
136 serial@12000 {
137 status = "okay";
138 };
139
140 i2c@11000 {
141 status = "okay";
142 };
143
144 ehci@50000 {
145 status = "okay";
146 };
147 };
148
149 gpio-leds {
150 compatible = "gpio-leds";
151
152 blue-usb {
153 label = "dir665:blue:usb";
154 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
155 };
156 blue-internet {
157 /* Can only be turned on if the Internet
158 * Ethernet port has Link
159 */
160 label = "dir665:blue:internet";
161 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
162 };
163 amber-internet {
164 label = "dir665:amber:internet";
165 gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
166 };
167 blue-wifi5g {
168 label = "dir665:blue:5g";
169 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
170 };
171 blue-status {
172 label = "dir665:blue:status";
173 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
174 };
175 blue-wps {
176 label = "dir665:blue:wps";
177 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
178 };
179 amber-status {
180 label = "dir665:amber:status";
181 gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
182 };
183 blue-24g {
184 label = "dir665:blue:24g";
185 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
186 };
187 };
188
189 gpio-keys {
190 compatible = "gpio-keys";
191 #address-cells = <1>;
192 #size-cells = <0>;
193
194 reset {
195 label = "reset";
196 linux,code = <KEY_RESTART>;
197 gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
198 };
199 wps {
200 label = "wps";
201 linux,code = <KEY_WPS_BUTTON>;
202 gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
203 };
204 };
205
206 dsa@0 {
207 compatible = "marvell,dsa";
208 #address-cells = <2>;
209 #size-cells = <0>;
210
211 dsa,ethernet = <&eth0port>;
212 dsa,mii-bus = <&mdio>;
213
214 switch@0 {
215 #address-cells = <1>;
216 #size-cells = <0>;
217 reg = <0 0>; /* MDIO address 0, switch 0 in tree */
218
219 port@0 {
220 reg = <0>;
221 label = "lan4";
222 };
223
224 port@1 {
225 reg = <1>;
226 label = "lan3";
227 };
228
229 port@2 {
230 reg = <2>;
231 label = "lan2";
232 };
233
234 port@3 {
235 reg = <3>;
236 label = "lan1";
237 };
238
239 port@4 {
240 reg = <4>;
241 label = "wan";
242 };
243
244 port@6 {
245 reg = <6>;
246 label = "cpu";
247 };
248 };
249 };
250};
251
252&mdio {
253 status = "okay";
254};
255
256/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
257 * fixed speed and duplex. */
258&eth0 {
259 status = "okay";
260
261 ethernet0-port@0 {
262 speed = <1000>;
263 duplex = <1>;
264 };
265};
266
267/* eth1 is connected to the switch as well. However DSA only supports a
268 * single CPU port. So leave this port disabled to avoid confusion. */
269
270&eth1 {
271 status = "disabled";
272};
273
274/* There is no battery on the boards, so the RTC does not keep time
275 * when there is no power, making it useless. */
276&rtc {
277 status = "disabled";
278};
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 811e0971fc58..8be5b2e4626e 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -266,7 +266,7 @@
266 266
267 s35390a: s35390a@30 { 267 s35390a: s35390a@30 {
268 status = "disabled"; 268 status = "disabled";
269 compatible = "ssi,s35390a"; 269 compatible = "sii,s35390a";
270 reg = <0x30>; 270 reg = <0x30>;
271 }; 271 };
272 }; 272 };
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
new file mode 100644
index 000000000000..9c5e16ba8c95
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -0,0 +1,240 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "ls1021a.dtsi"
50
51/ {
52 model = "LS1021A QDS Board";
53
54 aliases {
55 enet0_rgmii_phy = &rgmii_phy1;
56 enet1_rgmii_phy = &rgmii_phy2;
57 enet2_rgmii_phy = &rgmii_phy3;
58 enet0_sgmii_phy = &sgmii_phy1c;
59 enet1_sgmii_phy = &sgmii_phy1d;
60 };
61};
62
63&dspi0 {
64 bus-num = <0>;
65 status = "okay";
66
67 dspiflash: at45db021d@0 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
71 spi-max-frequency = <16000000>;
72 spi-cpol;
73 spi-cpha;
74 reg = <0>;
75 };
76};
77
78&i2c0 {
79 status = "okay";
80
81 pca9547: mux@77 {
82 reg = <0x77>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 i2c@0 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 reg = <0x0>;
90
91 ds3232: rtc@68 {
92 compatible = "dallas,ds3232";
93 reg = <0x68>;
94 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
95 };
96 };
97
98 i2c@2 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0x2>;
102
103 ina220@40 {
104 compatible = "ti,ina220";
105 reg = <0x40>;
106 shunt-resistor = <1000>;
107 };
108
109 ina220@41 {
110 compatible = "ti,ina220";
111 reg = <0x41>;
112 shunt-resistor = <1000>;
113 };
114 };
115
116 i2c@3 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 reg = <0x3>;
120
121 eeprom@56 {
122 compatible = "atmel,24c512";
123 reg = <0x56>;
124 };
125
126 eeprom@57 {
127 compatible = "atmel,24c512";
128 reg = <0x57>;
129 };
130
131 adt7461a@4c {
132 compatible = "adi,adt7461a";
133 reg = <0x4c>;
134 };
135 };
136 };
137};
138
139&ifc {
140 #address-cells = <2>;
141 #size-cells = <1>;
142 /* NOR, NAND Flashes and FPGA on board */
143 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
144 0x2 0x0 0x0 0x7e800000 0x00010000
145 0x3 0x0 0x0 0x7fb00000 0x00000100>;
146 status = "okay";
147
148 nor@0,0 {
149 #address-cells = <1>;
150 #size-cells = <1>;
151 compatible = "cfi-flash";
152 reg = <0x0 0x0 0x8000000>;
153 bank-width = <2>;
154 device-width = <1>;
155 };
156
157 fpga: board-control@3,0 {
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "simple-bus";
161 reg = <0x3 0x0 0x0000100>;
162 bank-width = <1>;
163 device-width = <1>;
164 ranges = <0 3 0 0x100>;
165
166 mdio-mux-emi1 {
167 compatible = "mdio-mux-mmioreg";
168 mdio-parent-bus = <&mdio0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171 reg = <0x54 1>; /* BRDCFG4 */
172 mux-mask = <0xe0>; /* EMI1[2:0] */
173
174 /* Onboard PHYs */
175 ls1021amdio0: mdio@0 {
176 reg = <0>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 rgmii_phy1: ethernet-phy@1 {
180 reg = <0x1>;
181 };
182 };
183
184 ls1021amdio1: mdio@20 {
185 reg = <0x20>;
186 #address-cells = <1>;
187 #size-cells = <0>;
188 rgmii_phy2: ethernet-phy@2 {
189 reg = <0x2>;
190 };
191 };
192
193 ls1021amdio2: mdio@40 {
194 reg = <0x40>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 rgmii_phy3: ethernet-phy@3 {
198 reg = <0x3>;
199 };
200 };
201
202 ls1021amdio3: mdio@60 {
203 reg = <0x60>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 sgmii_phy1c: ethernet-phy@1c {
207 reg = <0x1c>;
208 };
209 };
210
211 ls1021amdio4: mdio@80 {
212 reg = <0x80>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 sgmii_phy1d: ethernet-phy@1d {
216 reg = <0x1d>;
217 };
218 };
219 };
220 };
221};
222
223&lpuart0 {
224 status = "okay";
225};
226
227&mdio0 {
228 tbi0: tbi-phy@8 {
229 reg = <0x8>;
230 device_type = "tbi-phy";
231 };
232};
233
234&uart0 {
235 status = "okay";
236};
237
238&uart1 {
239 status = "okay";
240};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
new file mode 100644
index 000000000000..a2c591e2d918
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -0,0 +1,127 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "ls1021a.dtsi"
50
51/ {
52 model = "LS1021A TWR Board";
53
54 aliases {
55 enet2_rgmii_phy = &rgmii_phy1;
56 enet0_sgmii_phy = &sgmii_phy2;
57 enet1_sgmii_phy = &sgmii_phy0;
58 };
59};
60
61&dspi1 {
62 bus-num = <0>;
63 status = "okay";
64
65 dspiflash: s25fl064k@0 {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 compatible = "spansion,s25fl064k";
69 spi-max-frequency = <16000000>;
70 spi-cpol;
71 spi-cpha;
72 reg = <0>;
73 };
74};
75
76&i2c0 {
77 status = "okay";
78};
79
80&i2c1 {
81 status = "okay";
82};
83
84&ifc {
85 #address-cells = <2>;
86 #size-cells = <1>;
87 /* NOR Flash on board */
88 ranges = <0x0 0x0 0x0 0x60000000 0x08000000>;
89 status = "okay";
90
91 nor@0,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "cfi-flash";
95 reg = <0x0 0x0 0x8000000>;
96 bank-width = <2>;
97 device-width = <1>;
98 };
99};
100
101&lpuart0 {
102 status = "okay";
103};
104
105&mdio0 {
106 sgmii_phy0: ethernet-phy@0 {
107 reg = <0x0>;
108 };
109 rgmii_phy1: ethernet-phy@1 {
110 reg = <0x1>;
111 };
112 sgmii_phy2: ethernet-phy@2 {
113 reg = <0x2>;
114 };
115 tbi1: tbi-phy@1f {
116 reg = <0x1f>;
117 device_type = "tbi-phy";
118 };
119};
120
121&uart0 {
122 status = "okay";
123};
124
125&uart1 {
126 status = "okay";
127};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
new file mode 100644
index 000000000000..657da14cb4b5
--- /dev/null
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -0,0 +1,408 @@
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50
51/ {
52 compatible = "fsl,ls1021a";
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &lpuart0;
57 serial1 = &lpuart1;
58 serial2 = &lpuart2;
59 serial3 = &lpuart3;
60 serial4 = &lpuart4;
61 serial5 = &lpuart5;
62 sysclk = &sysclk;
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 cpu@f00 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <0xf00>;
73 clocks = <&cluster1_clk>;
74 };
75
76 cpu@f01 {
77 compatible = "arm,cortex-a7";
78 device_type = "cpu";
79 reg = <0xf01>;
80 clocks = <&cluster1_clk>;
81 };
82 };
83
84 timer {
85 compatible = "arm,armv7-timer";
86 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
87 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
89 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
90 };
91
92 pmu {
93 compatible = "arm,cortex-a7-pmu";
94 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
96 };
97
98 soc {
99 compatible = "simple-bus";
100 #address-cells = <2>;
101 #size-cells = <2>;
102 device_type = "soc";
103 interrupt-parent = <&gic>;
104 ranges;
105
106 gic: interrupt-controller@1400000 {
107 compatible = "arm,cortex-a7-gic";
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 reg = <0x0 0x1401000 0x0 0x1000>,
111 <0x0 0x1402000 0x0 0x1000>,
112 <0x0 0x1404000 0x0 0x2000>,
113 <0x0 0x1406000 0x0 0x2000>;
114 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
115
116 };
117
118 ifc: ifc@1530000 {
119 compatible = "fsl,ifc", "simple-bus";
120 reg = <0x0 0x1530000 0x0 0x10000>;
121 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
122 };
123
124 dcfg: dcfg@1ee0000 {
125 compatible = "fsl,ls1021a-dcfg", "syscon";
126 reg = <0x0 0x1ee0000 0x0 0x10000>;
127 big-endian;
128 };
129
130 esdhc: esdhc@1560000 {
131 compatible = "fsl,esdhc";
132 reg = <0x0 0x1560000 0x0 0x10000>;
133 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
134 clock-frequency = <0>;
135 voltage-ranges = <1800 1800 3300 3300>;
136 sdhci,auto-cmd12;
137 big-endian;
138 bus-width = <4>;
139 status = "disabled";
140 };
141
142 scfg: scfg@1570000 {
143 compatible = "fsl,ls1021a-scfg", "syscon";
144 reg = <0x0 0x1570000 0x0 0x10000>;
145 };
146
147 clockgen: clocking@1ee1000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x1ee1000 0x10000>;
151
152 sysclk: sysclk {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-output-names = "sysclk";
156 };
157
158 cga_pll1: pll@800 {
159 compatible = "fsl,qoriq-core-pll-2.0";
160 #clock-cells = <1>;
161 reg = <0x800 0x10>;
162 clocks = <&sysclk>;
163 clock-output-names = "cga-pll1", "cga-pll1-div2",
164 "cga-pll1-div4";
165 };
166
167 platform_clk: pll@c00 {
168 compatible = "fsl,qoriq-core-pll-2.0";
169 #clock-cells = <1>;
170 reg = <0xc00 0x10>;
171 clocks = <&sysclk>;
172 clock-output-names = "platform-clk", "platform-clk-div2";
173 };
174
175 cluster1_clk: clk0c0@0 {
176 compatible = "fsl,qoriq-core-mux-2.0";
177 #clock-cells = <0>;
178 reg = <0x0 0x10>;
179 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
180 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
181 clock-output-names = "cluster1-clk";
182 };
183 };
184
185 dspi0: dspi@2100000 {
186 compatible = "fsl,vf610-dspi";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 reg = <0x0 0x2100000 0x0 0x10000>;
190 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
191 clock-names = "dspi";
192 clocks = <&platform_clk 1>;
193 spi-num-chipselects = <5>;
194 big-endian;
195 status = "disabled";
196 };
197
198 dspi1: dspi@2110000 {
199 compatible = "fsl,vf610-dspi";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x0 0x2110000 0x0 0x10000>;
203 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
204 clock-names = "dspi";
205 clocks = <&platform_clk 1>;
206 spi-num-chipselects = <5>;
207 big-endian;
208 status = "disabled";
209 };
210
211 i2c0: i2c@2180000 {
212 compatible = "fsl,vf610-i2c";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <0x0 0x2180000 0x0 0x10000>;
216 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
217 clock-names = "i2c";
218 clocks = <&platform_clk 1>;
219 status = "disabled";
220 };
221
222 i2c1: i2c@2190000 {
223 compatible = "fsl,vf610-i2c";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 reg = <0x0 0x2190000 0x0 0x10000>;
227 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
228 clock-names = "i2c";
229 clocks = <&platform_clk 1>;
230 status = "disabled";
231 };
232
233 i2c2: i2c@21a0000 {
234 compatible = "fsl,vf610-i2c";
235 #address-cells = <1>;
236 #size-cells = <0>;
237 reg = <0x0 0x21a0000 0x0 0x10000>;
238 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
239 clock-names = "i2c";
240 clocks = <&platform_clk 1>;
241 status = "disabled";
242 };
243
244 uart0: serial@21c0500 {
245 compatible = "fsl,16550-FIFO64", "ns16550a";
246 reg = <0x0 0x21c0500 0x0 0x100>;
247 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
248 clock-frequency = <0>;
249 fifo-size = <15>;
250 status = "disabled";
251 };
252
253 uart1: serial@21c0600 {
254 compatible = "fsl,16550-FIFO64", "ns16550a";
255 reg = <0x0 0x21c0600 0x0 0x100>;
256 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
257 clock-frequency = <0>;
258 fifo-size = <15>;
259 status = "disabled";
260 };
261
262 uart2: serial@21d0500 {
263 compatible = "fsl,16550-FIFO64", "ns16550a";
264 reg = <0x0 0x21d0500 0x0 0x100>;
265 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
266 clock-frequency = <0>;
267 fifo-size = <15>;
268 status = "disabled";
269 };
270
271 uart3: serial@21d0600 {
272 compatible = "fsl,16550-FIFO64", "ns16550a";
273 reg = <0x0 0x21d0600 0x0 0x100>;
274 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
275 clock-frequency = <0>;
276 fifo-size = <15>;
277 status = "disabled";
278 };
279
280 lpuart0: serial@2950000 {
281 compatible = "fsl,ls1021a-lpuart";
282 reg = <0x0 0x2950000 0x0 0x1000>;
283 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&sysclk>;
285 clock-names = "ipg";
286 status = "disabled";
287 };
288
289 lpuart1: serial@2960000 {
290 compatible = "fsl,ls1021a-lpuart";
291 reg = <0x0 0x2960000 0x0 0x1000>;
292 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&platform_clk 1>;
294 clock-names = "ipg";
295 status = "disabled";
296 };
297
298 lpuart2: serial@2970000 {
299 compatible = "fsl,ls1021a-lpuart";
300 reg = <0x0 0x2970000 0x0 0x1000>;
301 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&platform_clk 1>;
303 clock-names = "ipg";
304 status = "disabled";
305 };
306
307 lpuart3: serial@2980000 {
308 compatible = "fsl,ls1021a-lpuart";
309 reg = <0x0 0x2980000 0x0 0x1000>;
310 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&platform_clk 1>;
312 clock-names = "ipg";
313 status = "disabled";
314 };
315
316 lpuart4: serial@2990000 {
317 compatible = "fsl,ls1021a-lpuart";
318 reg = <0x0 0x2990000 0x0 0x1000>;
319 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&platform_clk 1>;
321 clock-names = "ipg";
322 status = "disabled";
323 };
324
325 lpuart5: serial@29a0000 {
326 compatible = "fsl,ls1021a-lpuart";
327 reg = <0x0 0x29a0000 0x0 0x1000>;
328 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&platform_clk 1>;
330 clock-names = "ipg";
331 status = "disabled";
332 };
333
334 wdog0: watchdog@2ad0000 {
335 compatible = "fsl,imx21-wdt";
336 reg = <0x0 0x2ad0000 0x0 0x10000>;
337 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&platform_clk 1>;
339 clock-names = "wdog-en";
340 big-endian;
341 };
342
343 sai1: sai@2b50000 {
344 compatible = "fsl,vf610-sai";
345 reg = <0x0 0x2b50000 0x0 0x10000>;
346 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&platform_clk 1>;
348 clock-names = "sai";
349 dma-names = "tx", "rx";
350 dmas = <&edma0 1 47>,
351 <&edma0 1 46>;
352 big-endian;
353 status = "disabled";
354 };
355
356 sai2: sai@2b60000 {
357 compatible = "fsl,vf610-sai";
358 reg = <0x0 0x2b60000 0x0 0x10000>;
359 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&platform_clk 1>;
361 clock-names = "sai";
362 dma-names = "tx", "rx";
363 dmas = <&edma0 1 45>,
364 <&edma0 1 44>;
365 big-endian;
366 status = "disabled";
367 };
368
369 edma0: edma@2c00000 {
370 #dma-cells = <2>;
371 compatible = "fsl,vf610-edma";
372 reg = <0x0 0x2c00000 0x0 0x10000>,
373 <0x0 0x2c10000 0x0 0x10000>,
374 <0x0 0x2c20000 0x0 0x10000>;
375 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "edma-tx", "edma-err";
378 dma-channels = <32>;
379 big-endian;
380 clock-names = "dmamux0", "dmamux1";
381 clocks = <&platform_clk 1>,
382 <&platform_clk 1>;
383 };
384
385 mdio0: mdio@2d24000 {
386 compatible = "gianfar";
387 device_type = "mdio";
388 #address-cells = <1>;
389 #size-cells = <0>;
390 reg = <0x0 0x2d24000 0x0 0x4000>;
391 };
392
393 usb@8600000 {
394 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
395 reg = <0x0 0x8600000 0x0 0x1000>;
396 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
397 dr_mode = "host";
398 phy_type = "ulpi";
399 };
400
401 usb3@3100000 {
402 compatible = "snps,dwc3";
403 reg = <0x0 0x3100000 0x0 0x10000>;
404 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
405 dr_mode = "host";
406 };
407 };
408};
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711..03bcff87bd27 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
50/ { 50/ {
51 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
52 52
53 L2: l2-cache-controller@c4200000 {
54 compatible = "arm,pl310-cache";
55 reg = <0xc4200000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
53 gic: interrupt-controller@c4301000 { 60 gic: interrupt-controller@c4301000 {
54 compatible = "arm,cortex-a9-gic"; 61 compatible = "arm,cortex-a9-gic";
55 reg = <0xc4301000 0x1000>, 62 reg = <0xc4301000 0x1000>,
@@ -106,5 +113,35 @@
106 clocks = <&clk81>; 113 clocks = <&clk81>;
107 status = "disabled"; 114 status = "disabled";
108 }; 115 };
116
117 i2c_AO: i2c@c8100500 {
118 compatible = "amlogic,meson6-i2c";
119 reg = <0xc8100500 0x20>;
120 interrupts = <0 92 1>;
121 clocks = <&clk81>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 status = "disabled";
125 };
126
127 i2c_A: i2c@c1108500 {
128 compatible = "amlogic,meson6-i2c";
129 reg = <0xc1108500 0x20>;
130 interrupts = <0 21 1>;
131 clocks = <&clk81>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 status = "disabled";
135 };
136
137 i2c_B: i2c@c11087c0 {
138 compatible = "amlogic,meson6-i2c";
139 reg = <0xc11087c0 0x20>;
140 interrupts = <0 128 1>;
141 clocks = <&clk81>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disabled";
145 };
109 }; 146 };
110}; /* end of / */ 147}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541faf1ec..d7d351a68944 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -50,7 +50,7 @@
50 50
51/ { 51/ {
52 model = "Geniatech ATV1200"; 52 model = "Geniatech ATV1200";
53 compatible = "geniatech,atv1200"; 53 compatible = "geniatech,atv1200", "amlogic,meson6";
54 54
55 aliases { 55 aliases {
56 serial0 = &uart_AO; 56 serial0 = &uart_AO;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
60 cpu@200 { 60 cpu@200 {
61 device_type = "cpu"; 61 device_type = "cpu";
62 compatible = "arm,cortex-a9"; 62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
63 reg = <0x200>; 64 reg = <0x200>;
64 }; 65 };
65 66
66 cpu@201 { 67 cpu@201 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cortex-a9"; 69 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
69 reg = <0x201>; 71 reg = <0x201>;
70 }; 72 };
71 }; 73 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000000000000..1f442a7fe03b
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,92 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/include/ "meson.dtsi"
47
48/ {
49 model = "Amlogic Meson8 SoC";
50 compatible = "amlogic,meson8";
51
52 interrupt-parent = <&gic>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a9";
61 next-level-cache = <&L2>;
62 reg = <0x200>;
63 };
64
65 cpu@201 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a9";
68 next-level-cache = <&L2>;
69 reg = <0x201>;
70 };
71
72 cpu@202 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a9";
75 next-level-cache = <&L2>;
76 reg = <0x202>;
77 };
78
79 cpu@203 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a9";
82 next-level-cache = <&L2>;
83 reg = <0x203>;
84 };
85 };
86
87 clk81: clk@0 {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <141666666>;
91 };
92}; /* end of / */
diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts
new file mode 100644
index 000000000000..b57237e6394a
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592-evb.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Howard Chen <ibanezchen@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt6592.dtsi"
17
18/ {
19 model = "mt6592 evb";
20 compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
21
22 memory {
23 reg = <0x80000000 0x40000000>;
24 };
25};
26
diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi
new file mode 100644
index 000000000000..31e5a0979d78
--- /dev/null
+++ b/arch/arm/boot/dts/mt6592.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Howard Chen <ibanezchen@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton.dtsi"
18
19/ {
20 compatible = "mediatek,mt6592";
21 interrupt-parent = <&gic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x0>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0x1>;
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0x2>;
41 };
42 cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 reg = <0x3>;
46 };
47 cpu@4 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a7";
50 reg = <0x4>;
51 };
52 cpu@5 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0x5>;
56 };
57 cpu@6 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <0x6>;
61 };
62 cpu@7 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a7";
65 reg = <0x7>;
66 };
67 };
68
69 system_clk: dummy13m {
70 compatible = "fixed-clock";
71 clock-frequency = <13000000>;
72 #clock-cells = <0>;
73 };
74
75 rtc_clk: dummy32k {
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
78 #clock-cells = <0>;
79 };
80
81 timer: timer@10008000 {
82 compatible = "mediatek,mt6577-timer";
83 reg = <0x10008000 0x80>;
84 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&system_clk>, <&rtc_clk>;
86 clock-names = "system-clk", "rtc-clk";
87 };
88
89 gic: interrupt-controller@10211000 {
90 compatible = "arm,cortex-a7-gic";
91 interrupt-controller;
92 #interrupt-cells = <3>;
93 reg = <0x10211000 0x1000>,
94 <0x10212000 0x1000>;
95 };
96
97};
98
diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts
new file mode 100644
index 000000000000..13cba0e77e08
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127-moose.dts
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt8127.dtsi"
17
18/ {
19 model = "MediaTek MT8127 Moose Board";
20 compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
21
22 memory {
23 reg = <0 0x80000000 0 0x40000000>;
24 };
25};
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
new file mode 100644
index 000000000000..b24c0a2f3c44
--- /dev/null
+++ b/arch/arm/boot/dts/mt8127.dtsi
@@ -0,0 +1,94 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton64.dtsi"
18
19/ {
20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&gic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x0>;
31 };
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "arm,cortex-a7";
35 reg = <0x1>;
36 };
37 cpu@2 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a7";
40 reg = <0x2>;
41 };
42 cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 reg = <0x3>;
46 };
47
48 };
49
50 clocks {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 ranges;
55
56 system_clk: dummy13m {
57 compatible = "fixed-clock";
58 clock-frequency = <13000000>;
59 #clock-cells = <0>;
60 };
61
62 rtc_clk: dummy32k {
63 compatible = "fixed-clock";
64 clock-frequency = <32000>;
65 #clock-cells = <0>;
66 };
67 };
68
69 soc {
70 #address-cells = <2>;
71 #size-cells = <2>;
72 compatible = "simple-bus";
73 ranges;
74
75 timer: timer@10008000 {
76 compatible = "mediatek,mt8127-timer",
77 "mediatek,mt6577-timer";
78 reg = <0 0x10008000 0 0x80>;
79 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&system_clk>, <&rtc_clk>;
81 clock-names = "system-clk", "rtc-clk";
82 };
83
84 gic: interrupt-controller@10211000 {
85 compatible = "arm,cortex-a7-gic";
86 interrupt-controller;
87 #interrupt-cells = <3>;
88 reg = <0 0x10211000 0 0x1000>,
89 <0 0x10212000 0 0x1000>,
90 <0 0x10214000 0 0x2000>,
91 <0 0x10216000 0 0x2000>;
92 };
93 };
94};
diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts
new file mode 100644
index 000000000000..a5adf9742308
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135-evbp1.dts
@@ -0,0 +1,25 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15/dts-v1/;
16#include "mt8135.dtsi"
17
18/ {
19 model = "MediaTek MT8135 evaluation board";
20 compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135";
21
22 memory {
23 reg = <0 0x80000000 0 0x40000000>;
24 };
25};
diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
new file mode 100644
index 000000000000..7d56a986358e
--- /dev/null
+++ b/arch/arm/boot/dts/mt8135.dtsi
@@ -0,0 +1,116 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include "skeleton64.dtsi"
18
19/ {
20 compatible = "mediatek,mt8135";
21 interrupt-parent = <&gic>;
22
23 cpu-map {
24 cluster0 {
25 core0 {
26 cpu = <&cpu0>;
27 };
28 core1 {
29 cpu = <&cpu1>;
30 };
31 };
32
33 cluster1 {
34 core0 {
35 cpu = <&cpu2>;
36 };
37 core1 {
38 cpu = <&cpu3>;
39 };
40 };
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a7";
50 reg = <0x000>;
51 };
52
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a7";
56 reg = <0x001>;
57 };
58
59 cpu2: cpu@100 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x100>;
63 };
64
65 cpu3: cpu@101 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <0x101>;
69 };
70 };
71
72 clocks {
73 #address-cells = <2>;
74 #size-cells = <2>;
75 compatible = "simple-bus";
76 ranges;
77
78 system_clk: dummy13m {
79 compatible = "fixed-clock";
80 clock-frequency = <13000000>;
81 #clock-cells = <0>;
82 };
83
84 rtc_clk: dummy32k {
85 compatible = "fixed-clock";
86 clock-frequency = <32000>;
87 #clock-cells = <0>;
88 };
89 };
90
91 soc {
92 #address-cells = <2>;
93 #size-cells = <2>;
94 compatible = "simple-bus";
95 ranges;
96
97 timer: timer@10008000 {
98 compatible = "mediatek,mt8135-timer",
99 "mediatek,mt6577-timer";
100 reg = <0 0x10008000 0 0x80>;
101 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
102 clocks = <&system_clk>, <&rtc_clk>;
103 clock-names = "system-clk", "rtc-clk";
104 };
105
106 gic: interrupt-controller@10211000 {
107 compatible = "arm,cortex-a15-gic";
108 interrupt-controller;
109 #interrupt-cells = <3>;
110 reg = <0 0x10211000 0 0x1000>,
111 <0 0x10212000 0 0x1000>,
112 <0 0x10214000 0 0x2000>,
113 <0 0x10216000 0 0x2000>;
114 };
115 };
116};
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index 521c587acaee..445fafc73254 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -23,24 +23,29 @@
23 ethernet@gpmc { 23 ethernet@gpmc {
24 compatible = "smsc,lan9221", "smsc,lan9115"; 24 compatible = "smsc,lan9221", "smsc,lan9115";
25 bank-width = <2>; 25 bank-width = <2>;
26 gpmc,mux-add-data; 26 gpmc,device-width = <1>;
27 gpmc,cs-on-ns = <1>; 27 gpmc,cycle2cycle-samecsen = <1>;
28 gpmc,cs-rd-off-ns = <180>; 28 gpmc,cycle2cycle-diffcsen = <1>;
29 gpmc,cs-wr-off-ns = <180>; 29 gpmc,cs-on-ns = <5>;
30 gpmc,adv-rd-off-ns = <18>; 30 gpmc,cs-rd-off-ns = <150>;
31 gpmc,adv-wr-off-ns = <48>; 31 gpmc,cs-wr-off-ns = <150>;
32 gpmc,oe-on-ns = <54>; 32 gpmc,adv-on-ns = <0>;
33 gpmc,oe-off-ns = <168>; 33 gpmc,adv-rd-off-ns = <15>;
34 gpmc,we-on-ns = <54>; 34 gpmc,adv-wr-off-ns = <40>;
35 gpmc,we-off-ns = <168>; 35 gpmc,oe-on-ns = <45>;
36 gpmc,rd-cycle-ns = <186>; 36 gpmc,oe-off-ns = <140>;
37 gpmc,wr-cycle-ns = <186>; 37 gpmc,we-on-ns = <45>;
38 gpmc,access-ns = <144>; 38 gpmc,we-off-ns = <140>;
39 gpmc,page-burst-access-ns = <24>; 39 gpmc,rd-cycle-ns = <155>;
40 gpmc,bus-turnaround-ns = <90>; 40 gpmc,wr-cycle-ns = <155>;
41 gpmc,cycle2cycle-delay-ns = <90>; 41 gpmc,access-ns = <120>;
42 gpmc,cycle2cycle-samecsen; 42 gpmc,page-burst-access-ns = <20>;
43 gpmc,cycle2cycle-diffcsen; 43 gpmc,bus-turnaround-ns = <75>;
44 gpmc,cycle2cycle-delay-ns = <75>;
45 gpmc,wait-monitoring-ns = <0>;
46 gpmc,clk-activation-ns = <0>;
47 gpmc,wr-data-mux-bus-ns = <0>;
48 gpmc,wr-access-ns = <0>;
44 vddvario-supply = <&vddvario>; 49 vddvario-supply = <&vddvario>;
45 vdd33a-supply = <&vdd33a>; 50 vdd33a-supply = <&vdd33a>;
46 reg-io-width = <4>; 51 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi
index 68221fab978d..46ef3e443861 100644
--- a/arch/arm/boot/dts/omap-zoom-common.dtsi
+++ b/arch/arm/boot/dts/omap-zoom-common.dtsi
@@ -5,7 +5,7 @@
5#include "omap-gpmc-smsc911x.dtsi" 5#include "omap-gpmc-smsc911x.dtsi"
6 6
7&gpmc { 7&gpmc {
8 ranges = <3 0 0x10000000 0x00000400>, 8 ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */
9 <7 0 0x2c000000 0x01000000>; 9 <7 0 0x2c000000 0x01000000>;
10 10
11 /* 11 /*
@@ -15,7 +15,65 @@
15 */ 15 */
16 uart@3,0 { 16 uart@3,0 {
17 compatible = "ns16550a"; 17 compatible = "ns16550a";
18 reg = <3 0 0x100>; 18 reg = <3 0 8>; /* CS3, offset 0, IO size 8 */
19 bank-width = <2>;
20 reg-shift = <1>;
21 reg-io-width = <1>;
22 interrupt-parent = <&gpio4>;
23 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
24 clock-frequency = <1843200>;
25 current-speed = <115200>;
26 gpmc,mux-add-data = <0>;
27 gpmc,device-width = <1>;
28 gpmc,wait-pin = <1>;
29 gpmc,cycle2cycle-samecsen = <1>;
30 gpmc,cycle2cycle-diffcsen = <1>;
31 gpmc,cs-on-ns = <5>;
32 gpmc,cs-rd-off-ns = <155>;
33 gpmc,cs-wr-off-ns = <155>;
34 gpmc,adv-on-ns = <15>;
35 gpmc,adv-rd-off-ns = <40>;
36 gpmc,adv-wr-off-ns = <40>;
37 gpmc,oe-on-ns = <45>;
38 gpmc,oe-off-ns = <145>;
39 gpmc,we-on-ns = <45>;
40 gpmc,we-off-ns = <145>;
41 gpmc,rd-cycle-ns = <155>;
42 gpmc,wr-cycle-ns = <155>;
43 gpmc,access-ns = <145>;
44 gpmc,page-burst-access-ns = <20>;
45 gpmc,bus-turnaround-ns = <20>;
46 gpmc,cycle2cycle-delay-ns = <20>;
47 gpmc,wait-monitoring-ns = <0>;
48 gpmc,clk-activation-ns = <0>;
49 gpmc,wr-data-mux-bus-ns = <45>;
50 gpmc,wr-access-ns = <145>;
51 };
52 uart@3,1 {
53 compatible = "ns16550a";
54 reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */
55 bank-width = <2>;
56 reg-shift = <1>;
57 reg-io-width = <1>;
58 interrupt-parent = <&gpio4>;
59 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
60 clock-frequency = <1843200>;
61 current-speed = <115200>;
62 };
63 uart@3,2 {
64 compatible = "ns16550a";
65 reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */
66 bank-width = <2>;
67 reg-shift = <1>;
68 reg-io-width = <1>;
69 interrupt-parent = <&gpio4>;
70 interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */
71 clock-frequency = <1843200>;
72 current-speed = <115200>;
73 };
74 uart@3,3 {
75 compatible = "ns16550a";
76 reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */
19 bank-width = <2>; 77 bank-width = <2>;
20 reg-shift = <1>; 78 reg-shift = <1>;
21 reg-io-width = <1>; 79 reg-io-width = <1>;
diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
index 24c50db2a478..c9f1e93a95ae 100644
--- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
+++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi
@@ -40,14 +40,14 @@
40}; 40};
41 41
42&gpmc { 42&gpmc {
43 ranges = <0 0 0x04000000 0x10000000>; 43 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
44 44
45 /* gpio-irq for dma: 26 */ 45 /* gpio-irq for dma: 26 */
46 46
47 onenand@0,0 { 47 onenand@0,0 {
48 #address-cells = <1>; 48 #address-cells = <1>;
49 #size-cells = <1>; 49 #size-cells = <1>;
50 reg = <0 0 0x10000000>; 50 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
51 51
52 gpmc,sync-read; 52 gpmc,sync-read;
53 gpmc,burst-length = <16>; 53 gpmc,burst-length = <16>;
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index ae89aad01595..e2b2e93d7b61 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -157,6 +157,7 @@
157 interrupts = <26>, <34>; 157 interrupts = <26>, <34>;
158 interrupt-names = "dsp", "iva"; 158 interrupt-names = "dsp", "iva";
159 ti,hwmods = "mailbox"; 159 ti,hwmods = "mailbox";
160 #mbox-cells = <1>;
160 ti,mbox-num-users = <4>; 161 ti,mbox-num-users = <4>;
161 ti,mbox-num-fifos = <6>; 162 ti,mbox-num-fifos = <6>;
162 mbox_dsp: dsp { 163 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts
index 2c90d29b4cad..05eca2e4430f 100644
--- a/arch/arm/boot/dts/omap2430-sdp.dts
+++ b/arch/arm/boot/dts/omap2430-sdp.dts
@@ -43,7 +43,31 @@
43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ 43 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */
44 reg = <5 0x300 0xf>; 44 reg = <5 0x300 0xf>;
45 bank-width = <2>; 45 bank-width = <2>;
46 gpmc,mux-add-data; 46 gpmc,sync-clk-ps = <0>;
47 }; 47 gpmc,mux-add-data = <2>;
48 gpmc,device-width = <1>;
49 gpmc,cycle2cycle-samecsen = <1>;
50 gpmc,cycle2cycle-diffcsen = <1>;
51 gpmc,cs-on-ns = <7>;
52 gpmc,cs-rd-off-ns = <233>;
53 gpmc,cs-wr-off-ns = <233>;
54 gpmc,adv-on-ns = <22>;
55 gpmc,adv-rd-off-ns = <60>;
56 gpmc,adv-wr-off-ns = <60>;
57 gpmc,oe-on-ns = <67>;
58 gpmc,oe-off-ns = <210>;
59 gpmc,we-on-ns = <67>;
60 gpmc,we-off-ns = <210>;
61 gpmc,rd-cycle-ns = <233>;
62 gpmc,wr-cycle-ns = <233>;
63 gpmc,access-ns = <233>;
64 gpmc,page-burst-access-ns = <30>;
65 gpmc,bus-turnaround-ns = <30>;
66 gpmc,cycle2cycle-delay-ns = <30>;
67 gpmc,wait-monitoring-ns = <0>;
68 gpmc,clk-activation-ns = <0>;
69 gpmc,wr-data-mux-bus-ns = <0>;
70 gpmc,wr-access-ns = <0>;
71 };
48}; 72};
49 73
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index b56d71611026..0dc8de2782b1 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -247,6 +247,7 @@
247 reg = <0x48094000 0x200>; 247 reg = <0x48094000 0x200>;
248 interrupts = <26>; 248 interrupts = <26>;
249 ti,hwmods = "mailbox"; 249 ti,hwmods = "mailbox";
250 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>; 251 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <6>; 252 ti,mbox-num-fifos = <6>;
252 mbox_dsp: dsp { 253 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts
index d00502f4fd9b..0ab748cf7749 100644
--- a/arch/arm/boot/dts/omap3-cm-t3517.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3517.dts
@@ -134,3 +134,14 @@
134 bus-width = <4>; 134 bus-width = <4>;
135 cap-power-off-card; 135 cap-power-off-card;
136}; 136};
137
138&dss {
139 status = "ok";
140
141 pinctrl-names = "default";
142 pinctrl-0 = <
143 &dss_dpi_pins_common
144 &dss_dpi_pins_cm_t35x
145 >;
146};
147
diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts
index d1458496520e..8dd14fcf6825 100644
--- a/arch/arm/boot/dts/omap3-cm-t3530.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3530.dts
@@ -46,3 +46,14 @@
46 bus-width = <4>; 46 bus-width = <4>;
47 cap-power-off-card; 47 cap-power-off-card;
48}; 48};
49
50&dss {
51 status = "ok";
52
53 pinctrl-names = "default";
54 pinctrl-0 = <
55 &dss_dpi_pins_common
56 &dss_dpi_pins_cm_t35x
57 >;
58};
59
diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts
index b3f9a50b3bc8..46eadb21b5ef 100644
--- a/arch/arm/boot/dts/omap3-cm-t3730.dts
+++ b/arch/arm/boot/dts/omap3-cm-t3730.dts
@@ -31,6 +31,19 @@
31 }; 31 };
32}; 32};
33 33
34&omap3_pmx_wkup {
35 dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 {
36 pinctrl-single,pins = <
37 OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */
38 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */
39 OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */
40 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */
41 OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */
42 OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */
43 >;
44 };
45};
46
34&omap3_pmx_core { 47&omap3_pmx_core {
35 48
36 mmc2_pins: pinmux_mmc2_pins { 49 mmc2_pins: pinmux_mmc2_pins {
@@ -61,3 +74,14 @@
61 bus-width = <4>; 74 bus-width = <4>;
62 cap-power-off-card; 75 cap-power-off-card;
63}; 76};
77
78&dss {
79 status = "ok";
80
81 pinctrl-names = "default";
82 pinctrl-0 = <
83 &dss_dpi_pins_common
84 &dss_dpi_pins_cm_t3730
85 >;
86};
87
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index c671a2299ea8..6ea6d460db30 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -49,6 +49,24 @@
49 compatible = "usb-nop-xceiv"; 49 compatible = "usb-nop-xceiv";
50 vcc-supply = <&hsusb2_power>; 50 vcc-supply = <&hsusb2_power>;
51 }; 51 };
52
53 ads7846reg: ads7846-reg {
54 compatible = "regulator-fixed";
55 regulator-name = "ads7846-reg";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 };
59
60 tv0: connector@1 {
61 compatible = "svideo-connector";
62 label = "tv";
63
64 port {
65 tv_connector_in: endpoint {
66 remote-endpoint = <&venc_out>;
67 };
68 };
69 };
52}; 70};
53 71
54&omap3_pmx_core { 72&omap3_pmx_core {
@@ -76,6 +94,76 @@
76 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ 94 OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */
77 >; 95 >;
78 }; 96 };
97
98 dss_dpi_pins_common: pinmux_dss_dpi_pins_common {
99 pinctrl-single,pins = <
100 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
101 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
102 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
103 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
104
105 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
106 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
107 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
108 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
109 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
110 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
111 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
112 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
113 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
114 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
115 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
116 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
117 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
118 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
119 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
120 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
121 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
122 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
123 >;
124 };
125
126 dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x {
127 pinctrl-single,pins = <
128 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
129 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
130 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
131 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
132 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
133 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
134 >;
135 };
136
137 ads7846_pins: pinmux_ads7846_pins {
138 pinctrl-single,pins = <
139 OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */
140 >;
141 };
142
143 mcspi1_pins: pinmux_mcspi1_pins {
144 pinctrl-single,pins = <
145 OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */
146 OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */
147 OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */
148 OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */
149 >;
150 };
151
152 i2c1_pins: pinmux_i2c1_pins {
153 pinctrl-single,pins = <
154 OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
155 OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
156 >;
157 };
158
159 mcbsp2_pins: pinmux_mcbsp2_pins {
160 pinctrl-single,pins = <
161 OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */
162 OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */
163 OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */
164 OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */
165 >;
166 };
79}; 167};
80 168
81&uart3 { 169&uart3 {
@@ -94,12 +182,22 @@
94}; 182};
95 183
96&i2c1 { 184&i2c1 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&i2c1_pins>;
187
97 clock-frequency = <400000>; 188 clock-frequency = <400000>;
189
190 at24@50 {
191 compatible = "at24,24c02";
192 pagesize = <16>;
193 reg = <0x50>;
194 };
98}; 195};
99 196
100&i2c3 { 197&i2c3 {
101 clock-frequency = <400000>; 198 clock-frequency = <400000>;
102}; 199};
200
103&usbhshost { 201&usbhshost {
104 port1-mode = "ehci-phy"; 202 port1-mode = "ehci-phy";
105 port2-mode = "ehci-phy"; 203 port2-mode = "ehci-phy";
@@ -108,3 +206,56 @@
108&usbhsehci { 206&usbhsehci {
109 phys = <&hsusb1_phy &hsusb2_phy>; 207 phys = <&hsusb1_phy &hsusb2_phy>;
110}; 208};
209
210&mcspi1 {
211 pinctrl-names = "default";
212 pinctrl-0 = <&mcspi1_pins>;
213
214 /* touch controller */
215 ads7846@0 {
216 pinctrl-names = "default";
217 pinctrl-0 = <&ads7846_pins>;
218
219 compatible = "ti,ads7846";
220 vcc-supply = <&ads7846reg>;
221
222 reg = <0>; /* CS0 */
223 spi-max-frequency = <1500000>;
224
225 interrupt-parent = <&gpio2>;
226 interrupts = <25 0>; /* gpio_57 */
227 pendown-gpio = <&gpio2 25 0>;
228
229 ti,x-min = /bits/ 16 <0x0>;
230 ti,x-max = /bits/ 16 <0x0fff>;
231 ti,y-min = /bits/ 16 <0x0>;
232 ti,y-max = /bits/ 16 <0x0fff>;
233
234 ti,x-plate-ohms = /bits/ 16 <180>;
235 ti,pressure-max = /bits/ 16 <255>;
236
237 ti,debounce-max = /bits/ 16 <30>;
238 ti,debounce-tol = /bits/ 16 <10>;
239 ti,debounce-rep = /bits/ 16 <1>;
240
241 linux,wakeup;
242 };
243};
244
245&venc {
246 status = "ok";
247
248 port {
249 venc_out: endpoint {
250 remote-endpoint = <&tv_connector_in>;
251 ti,channels = <2>;
252 };
253 };
254};
255
256&mcbsp2 {
257 status = "ok";
258
259 pinctrl-names = "default";
260 pinctrl-0 = <&mcbsp2_pins>;
261};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index 3cbaf98c1372..9a4a3ab9af78 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -10,6 +10,14 @@
10 cpu0-supply = <&vcc>; 10 cpu0-supply = <&vcc>;
11 }; 11 };
12 }; 12 };
13
14 sound {
15 compatible = "ti,omap-twl4030";
16 ti,model = "cm-t35";
17
18 ti,mcbsp = <&mcbsp2>;
19 ti,codec = <&twl_audio>;
20 };
13}; 21};
14 22
15&omap3_pmx_core { 23&omap3_pmx_core {
@@ -59,6 +67,12 @@
59 reg = <0x48>; 67 reg = <0x48>;
60 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 68 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
61 interrupt-parent = <&intc>; 69 interrupt-parent = <&intc>;
70
71 twl_audio: audio {
72 compatible = "ti,twl4030-audio";
73 codec {
74 };
75 };
62 }; 76 };
63}; 77};
64 78
@@ -66,6 +80,10 @@
66#include "twl4030_omap3.dtsi" 80#include "twl4030_omap3.dtsi"
67#include <dt-bindings/input/input.h> 81#include <dt-bindings/input/input.h>
68 82
83&venc {
84 vdda-supply = <&vdac>;
85};
86
69&mmc1 { 87&mmc1 {
70 vmmc-supply = <&vmmc1>; 88 vmmc-supply = <&vmmc1>;
71}; 89};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index da402f0fdab4..169037e5ff53 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -106,10 +106,10 @@
106}; 106};
107 107
108&gpmc { 108&gpmc {
109 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 109 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
110 110
111 nand@0,0 { 111 nand@0,0 {
112 reg = <0 0 0>; /* CS0, offset 0 */ 112 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
113 nand-bus-width = <16>; 113 nand-bus-width = <16>;
114 114
115 gpmc,sync-clk-ps = <0>; 115 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index a8bd4349c7d2..16e8ce350dda 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -154,13 +154,14 @@
154}; 154};
155 155
156&gpmc { 156&gpmc {
157 ranges = <0 0 0x00000000 0x20000000>, 157 ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */
158 <5 0 0x2c000000 0x01000000>; 158 <5 0 0x2c000000 0x01000000>;
159 159
160 nand@0,0 { 160 nand@0,0 {
161 linux,mtd-name= "hynix,h8kds0un0mer-4em"; 161 linux,mtd-name= "hynix,h8kds0un0mer-4em";
162 reg = <0 0 0>; 162 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
163 nand-bus-width = <16>; 163 nand-bus-width = <16>;
164 gpmc,device-width = <2>;
164 ti,nand-ecc-opt = "bch8"; 165 ti,nand-ecc-opt = "bch8";
165 166
166 gpmc,sync-clk-ps = <0>; 167 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index fd34f913ace3..655d6e920a86 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -104,67 +104,67 @@
104 104
105 uart1_pins: pinmux_uart1_pins { 105 uart1_pins: pinmux_uart1_pins {
106 pinctrl-single,pins = < 106 pinctrl-single,pins = <
107 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ 107 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
108 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ 108 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
109 >; 109 >;
110 }; 110 };
111 111
112 uart2_pins: pinmux_uart2_pins { 112 uart2_pins: pinmux_uart2_pins {
113 pinctrl-single,pins = < 113 pinctrl-single,pins = <
114 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ 114 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
115 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ 115 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
116 >; 116 >;
117 }; 117 };
118 118
119 uart3_pins: pinmux_uart3_pins { 119 uart3_pins: pinmux_uart3_pins {
120 pinctrl-single,pins = < 120 pinctrl-single,pins = <
121 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 121 OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
122 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ 122 OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
123 >; 123 >;
124 }; 124 };
125 125
126 mmc1_pins: pinmux_mmc1_pins { 126 mmc1_pins: pinmux_mmc1_pins {
127 pinctrl-single,pins = < 127 pinctrl-single,pins = <
128 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 128 OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
129 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ 129 OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
130 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ 130 OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
131 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ 131 OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
132 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ 132 OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
133 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ 133 OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
134 >; 134 >;
135 }; 135 };
136 136
137 dss_dpi_pins: pinmux_dss_dpi_pins { 137 dss_dpi_pins: pinmux_dss_dpi_pins {
138 pinctrl-single,pins = < 138 pinctrl-single,pins = <
139 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 139 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
140 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 140 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
141 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 141 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
142 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 142 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
143 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ 143 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
144 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ 144 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
145 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ 145 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
146 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ 146 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
147 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ 147 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
148 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ 148 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
149 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ 149 OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
150 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ 150 OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
151 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ 151 OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
152 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ 152 OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
153 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ 153 OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
154 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ 154 OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
155 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ 155 OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
156 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ 156 OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
157 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ 157 OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
158 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ 158 OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
159 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ 159 OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
160 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ 160 OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
161 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ 161 OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
162 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ 162 OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
163 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ 163 OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
164 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ 164 OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
165 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ 165 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
166 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ 166 OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
167 >; 167 >;
168 }; 168 };
169}; 169};
170 170
@@ -397,10 +397,10 @@
397}; 397};
398 398
399&gpmc { 399&gpmc {
400 ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ 400 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
401 401
402 nand@0,0 { 402 nand@0,0 {
403 reg = <0 0 0>; /* CS0, offset 0 */ 403 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
404 nand-bus-width = <16>; 404 nand-bus-width = <16>;
405 ti,nand-ecc-opt = "bch8"; 405 ti,nand-ecc-opt = "bch8";
406 406
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index e2d163bf0619..8a63ad2286aa 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -31,18 +31,6 @@
31 regulator-always-on; 31 regulator-always-on;
32 }; 32 };
33 33
34 lbee1usjyc_vmmc: lbee1usjyc_vmmc {
35 pinctrl-names = "default";
36 pinctrl-0 = <&lbee1usjyc_pins>;
37 compatible = "regulator-fixed";
38 regulator-name = "regulator-lbee1usjyc";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */
42 startup-delay-us = <10000>;
43 enable-active-high;
44 vin-supply = <&vdd33>;
45 };
46}; 34};
47 35
48&omap3_pmx_core { 36&omap3_pmx_core {
@@ -53,13 +41,6 @@
53 >; 41 >;
54 }; 42 };
55 43
56 uart2_pins: pinmux_uart2_pins {
57 pinctrl-single,pins = <
58 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
59 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
60 >;
61 };
62
63 uart3_pins: pinmux_uart3_pins { 44 uart3_pins: pinmux_uart3_pins {
64 pinctrl-single,pins = < 45 pinctrl-single,pins = <
65 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ 46 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
@@ -67,15 +48,6 @@
67 >; 48 >;
68 }; 49 };
69 50
70 /* WiFi/BT combo */
71 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
72 pinctrl-single,pins = <
73 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */
74 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */
75 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */
76 >;
77 };
78
79 mcbsp2_pins: pinmux_mcbsp2_pins { 51 mcbsp2_pins: pinmux_mcbsp2_pins {
80 pinctrl-single,pins = < 52 pinctrl-single,pins = <
81 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ 53 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
@@ -120,13 +92,6 @@
120 >; 92 >;
121 }; 93 };
122 94
123 i2c2_pins: pinmux_i2c2_pins {
124 pinctrl-single,pins = <
125 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */
126 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */
127 >;
128 };
129
130 i2c3_pins: pinmux_i2c3_pins { 95 i2c3_pins: pinmux_i2c3_pins {
131 pinctrl-single,pins = < 96 pinctrl-single,pins = <
132 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ 97 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */
@@ -135,6 +100,55 @@
135 }; 100 };
136}; 101};
137 102
103&gpmc {
104 nand@0,0 {
105 linux,mtd-name= "micron,mt29c4g96maz";
106 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
107 nand-bus-width = <16>;
108 gpmc,device-width = <2>;
109 ti,nand-ecc-opt = "bch8";
110
111 gpmc,sync-clk-ps = <0>;
112 gpmc,cs-on-ns = <0>;
113 gpmc,cs-rd-off-ns = <44>;
114 gpmc,cs-wr-off-ns = <44>;
115 gpmc,adv-on-ns = <6>;
116 gpmc,adv-rd-off-ns = <34>;
117 gpmc,adv-wr-off-ns = <44>;
118 gpmc,we-off-ns = <40>;
119 gpmc,oe-off-ns = <54>;
120 gpmc,access-ns = <64>;
121 gpmc,rd-cycle-ns = <82>;
122 gpmc,wr-cycle-ns = <82>;
123 gpmc,wr-access-ns = <40>;
124 gpmc,wr-data-mux-bus-ns = <0>;
125
126 #address-cells = <1>;
127 #size-cells = <1>;
128
129 partition@0 {
130 label = "SPL";
131 reg = <0 0x100000>;
132 };
133 partition@80000 {
134 label = "U-Boot";
135 reg = <0x100000 0x180000>;
136 };
137 partition@1c0000 {
138 label = "Environment";
139 reg = <0x280000 0x100000>;
140 };
141 partition@280000 {
142 label = "Kernel";
143 reg = <0x380000 0x300000>;
144 };
145 partition@780000 {
146 label = "Filesystem";
147 reg = <0x680000 0x1f980000>;
148 };
149 };
150};
151
138&i2c1 { 152&i2c1 {
139 pinctrl-names = "default"; 153 pinctrl-names = "default";
140 pinctrl-0 = <&i2c1_pins>; 154 pinctrl-0 = <&i2c1_pins>;
@@ -156,12 +170,6 @@
156#include "twl4030.dtsi" 170#include "twl4030.dtsi"
157#include "twl4030_omap3.dtsi" 171#include "twl4030_omap3.dtsi"
158 172
159&i2c2 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&i2c2_pins>;
162 clock-frequency = <400000>;
163};
164
165&i2c3 { 173&i2c3 {
166 pinctrl-names = "default"; 174 pinctrl-names = "default";
167 pinctrl-0 = <&i2c3_pins>; 175 pinctrl-0 = <&i2c3_pins>;
@@ -181,14 +189,6 @@
181 bus-width = <4>; 189 bus-width = <4>;
182}; 190};
183 191
184&mmc2 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&mmc2_pins>;
187 vmmc-supply = <&lbee1usjyc_vmmc>;
188 bus-width = <4>;
189 non-removable;
190};
191
192&mmc3 { 192&mmc3 {
193 status = "disabled"; 193 status = "disabled";
194}; 194};
@@ -198,11 +198,6 @@
198 pinctrl-0 = <&uart1_pins>; 198 pinctrl-0 = <&uart1_pins>;
199}; 199};
200 200
201&uart2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&uart2_pins>;
204};
205
206&uart3 { 201&uart3 {
207 pinctrl-names = "default"; 202 pinctrl-names = "default";
208 pinctrl-0 = <&uart3_pins>; 203 pinctrl-0 = <&uart3_pins>;
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
new file mode 100644
index 000000000000..e458c2185e3c
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -0,0 +1,246 @@
1/*
2 * Common Device Tree Source for IGEPv2
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14
15/ {
16
17 leds {
18 pinctrl-names = "default";
19 pinctrl-0 = <&leds_pins>;
20 compatible = "gpio-leds";
21
22 boot {
23 label = "omap3:green:boot";
24 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
25 default-state = "on";
26 };
27
28 user0 {
29 label = "omap3:red:user0";
30 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
31 default-state = "off";
32 };
33
34 user1 {
35 label = "omap3:red:user1";
36 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
37 default-state = "off";
38 };
39
40 user2 {
41 label = "omap3:green:user1";
42 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
43 };
44 };
45
46 /* HS USB Port 1 Power */
47 hsusb1_power: hsusb1_power_reg {
48 compatible = "regulator-fixed";
49 regulator-name = "hsusb1_vbus";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
53 startup-delay-us = <70000>;
54 };
55
56 /* HS USB Host PHY on PORT 1 */
57 hsusb1_phy: hsusb1_phy {
58 compatible = "usb-nop-xceiv";
59 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
60 vcc-supply = <&hsusb1_power>;
61 };
62
63 tfp410: encoder@0 {
64 compatible = "ti,tfp410";
65 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
66
67 ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 port@0 {
72 reg = <0>;
73
74 tfp410_in: endpoint@0 {
75 remote-endpoint = <&dpi_out>;
76 };
77 };
78
79 port@1 {
80 reg = <1>;
81
82 tfp410_out: endpoint@0 {
83 remote-endpoint = <&dvi_connector_in>;
84 };
85 };
86 };
87 };
88
89 dvi0: connector@0 {
90 compatible = "dvi-connector";
91 label = "dvi";
92
93 digital;
94
95 ddc-i2c-bus = <&i2c3>;
96
97 port {
98 dvi_connector_in: endpoint {
99 remote-endpoint = <&tfp410_out>;
100 };
101 };
102 };
103};
104
105&omap3_pmx_core {
106 pinctrl-names = "default";
107 pinctrl-0 = <
108 &tfp410_pins
109 &dss_dpi_pins
110 >;
111
112 tfp410_pins: pinmux_tfp410_pins {
113 pinctrl-single,pins = <
114 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
115 >;
116 };
117
118 dss_dpi_pins: pinmux_dss_dpi_pins {
119 pinctrl-single,pins = <
120 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
121 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
122 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
123 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
124 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
125 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
126 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
127 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
128 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
129 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
130 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
131 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
132 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
133 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
134 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
135 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
136 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
137 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
138 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
139 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
140 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
141 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
142 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
143 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
144 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
145 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
146 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
147 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
148 >;
149 };
150
151 uart2_pins: pinmux_uart2_pins {
152 pinctrl-single,pins = <
153 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
154 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
155 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
156 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
157 >;
158 };
159};
160
161&omap3_pmx_core2 {
162 pinctrl-names = "default";
163 pinctrl-0 = <
164 &hsusbb1_pins
165 >;
166
167 hsusbb1_pins: pinmux_hsusbb1_pins {
168 pinctrl-single,pins = <
169 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
170 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
171 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
172 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
173 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
174 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
175 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
176 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
177 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
178 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
179 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
180 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
181 >;
182 };
183
184 leds_pins: pinmux_leds_pins {
185 pinctrl-single,pins = <
186 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
187 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
188 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
189 >;
190 };
191};
192
193&i2c3 {
194 clock-frequency = <100000>;
195
196 /*
197 * Display monitor features are burnt in the EEPROM
198 * as EDID data.
199 */
200 eeprom@50 {
201 compatible = "ti,eeprom";
202 reg = <0x50>;
203 };
204};
205
206&gpmc {
207 ranges = <0 0 0x00000000 0x20000000>,
208 <5 0 0x2c000000 0x01000000>;
209
210 ethernet@gpmc {
211 pinctrl-names = "default";
212 pinctrl-0 = <&smsc9221_pins>;
213 reg = <5 0 0xff>;
214 interrupt-parent = <&gpio6>;
215 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
216 };
217};
218
219&uart2 {
220 pinctrl-names = "default";
221 pinctrl-0 = <&uart2_pins>;
222};
223
224&usbhshost {
225 port1-mode = "ehci-phy";
226};
227
228&usbhsehci {
229 phys = <&hsusb1_phy>;
230};
231
232&vpll2 {
233 /* Needed for DSS */
234 regulator-name = "vdds_dsi";
235};
236
237&dss {
238 status = "ok";
239
240 port {
241 dpi_out: endpoint {
242 remote-endpoint = <&tfp410_in>;
243 data-lines = <24>;
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
new file mode 100644
index 000000000000..cc8bd0cd8cf8
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts
@@ -0,0 +1,45 @@
1/*
2 * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0020-common.dtsi"
13
14/ {
15 model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37};
38
39&mmc2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
42 vmmc-supply = <&lbep5clwmc_wlen>;
43 bus-width = <4>;
44 non-removable;
45};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index b22caaaf774b..fea7f7edb45d 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,272 +9,59 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0020-common.dtsi"
13#include "omap-gpmc-smsc9221.dtsi"
14 13
15/ { 14/ {
16 model = "IGEPv2 (TI OMAP AM/DM37x)"; 15 model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
17 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
18 17
19 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
20 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
21 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
22 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
23 22 regulator-min-microvolt = <3300000>;
24 boot { 23 regulator-max-microvolt = <3300000>;
25 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
26 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 25 startup-delay-us = <10000>;
27 default-state = "on"; 26 enable-active-high;
28 };
29
30 user0 {
31 label = "omap3:red:user0";
32 gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
33 default-state = "off";
34 };
35
36 user1 {
37 label = "omap3:red:user1";
38 gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
39 default-state = "off";
40 };
41
42 user2 {
43 label = "omap3:green:user1";
44 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
45 };
46 }; 27 };
47 28
48 /* HS USB Port 1 Power */ 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
49 hsusb1_power: hsusb1_power_reg { 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
50 compatible = "regulator-fixed"; 31 compatible = "regulator-fixed";
51 regulator-name = "hsusb1_vbus"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
52 regulator-min-microvolt = <3300000>; 33 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>;
54 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ 35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
55 startup-delay-us = <70000>; 36 enable-active-high;
56 };
57
58 /* HS USB Host PHY on PORT 1 */
59 hsusb1_phy: hsusb1_phy {
60 compatible = "usb-nop-xceiv";
61 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
62 vcc-supply = <&hsusb1_power>;
63 };
64
65 tfp410: encoder@0 {
66 compatible = "ti,tfp410";
67 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
68
69 ports {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 port@0 {
74 reg = <0>;
75
76 tfp410_in: endpoint@0 {
77 remote-endpoint = <&dpi_out>;
78 };
79 };
80
81 port@1 {
82 reg = <1>;
83
84 tfp410_out: endpoint@0 {
85 remote-endpoint = <&dvi_connector_in>;
86 };
87 };
88 };
89 };
90
91 dvi0: connector@0 {
92 compatible = "dvi-connector";
93 label = "dvi";
94
95 digital;
96
97 ddc-i2c-bus = <&i2c3>;
98
99 port {
100 dvi_connector_in: endpoint {
101 remote-endpoint = <&tfp410_out>;
102 };
103 };
104 }; 37 };
105}; 38};
106 39
107&omap3_pmx_core { 40&omap3_pmx_core {
108 pinctrl-names = "default"; 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
109 pinctrl-0 = <
110 &tfp410_pins
111 &dss_dpi_pins
112 >;
113
114 tfp410_pins: pinmux_tfp410_pins {
115 pinctrl-single,pins = < 42 pinctrl-single,pins = <
116 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
117 >; 46 >;
118 }; 47 };
119 48
120 dss_dpi_pins: pinmux_dss_dpi_pins { 49 uart2_pins: pinmux_uart2_pins {
121 pinctrl-single,pins = < 50 pinctrl-single,pins = <
122 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ 51 OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */
123 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ 52 OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/
124 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ 53 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
125 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ 54 OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
126 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
127 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
128 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
129 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
130 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
131 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
132 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */
133 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */
134 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */
135 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */
136 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */
137 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */
138 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */
139 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */
140 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */
141 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */
142 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */
143 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */
144 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */
145 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */
146 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */
147 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */
148 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */
149 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */
150 >; 55 >;
151 }; 56 };
152}; 57};
153 58
154&omap3_pmx_core2 { 59/* On board Wifi module */
60&mmc2 {
155 pinctrl-names = "default"; 61 pinctrl-names = "default";
156 pinctrl-0 = < 62 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
157 &hsusbb1_pins 63 vmmc-supply = <&lbee1usjyc_pdn>;
158 >; 64 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
159 65 bus-width = <4>;
160 hsusbb1_pins: pinmux_hsusbb1_pins { 66 non-removable;
161 pinctrl-single,pins = <
162 OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
163 OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
164 OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
165 OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
166 OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
167 OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
168 OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
169 OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
170 OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
171 OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
172 OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
173 OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
174 >;
175 };
176
177 leds_pins: pinmux_leds_pins {
178 pinctrl-single,pins = <
179 OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
180 OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
181 OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
182 >;
183 };
184};
185
186&i2c3 {
187 clock-frequency = <100000>;
188
189 /*
190 * Display monitor features are burnt in the EEPROM
191 * as EDID data.
192 */
193 eeprom@50 {
194 compatible = "ti,eeprom";
195 reg = <0x50>;
196 };
197};
198
199&gpmc {
200 ranges = <0 0 0x00000000 0x20000000>,
201 <5 0 0x2c000000 0x01000000>;
202
203 nand@0,0 {
204 linux,mtd-name= "micron,mt29c4g96maz";
205 reg = <0 0 0>;
206 nand-bus-width = <16>;
207 ti,nand-ecc-opt = "bch8";
208
209 gpmc,sync-clk-ps = <0>;
210 gpmc,cs-on-ns = <0>;
211 gpmc,cs-rd-off-ns = <44>;
212 gpmc,cs-wr-off-ns = <44>;
213 gpmc,adv-on-ns = <6>;
214 gpmc,adv-rd-off-ns = <34>;
215 gpmc,adv-wr-off-ns = <44>;
216 gpmc,we-off-ns = <40>;
217 gpmc,oe-off-ns = <54>;
218 gpmc,access-ns = <64>;
219 gpmc,rd-cycle-ns = <82>;
220 gpmc,wr-cycle-ns = <82>;
221 gpmc,wr-access-ns = <40>;
222 gpmc,wr-data-mux-bus-ns = <0>;
223
224 #address-cells = <1>;
225 #size-cells = <1>;
226
227 partition@0 {
228 label = "SPL";
229 reg = <0 0x100000>;
230 };
231 partition@80000 {
232 label = "U-Boot";
233 reg = <0x100000 0x180000>;
234 };
235 partition@1c0000 {
236 label = "Environment";
237 reg = <0x280000 0x100000>;
238 };
239 partition@280000 {
240 label = "Kernel";
241 reg = <0x380000 0x300000>;
242 };
243 partition@780000 {
244 label = "Filesystem";
245 reg = <0x680000 0x1f980000>;
246 };
247 };
248
249 ethernet@gpmc {
250 pinctrl-names = "default";
251 pinctrl-0 = <&smsc9221_pins>;
252 reg = <5 0 0xff>;
253 interrupt-parent = <&gpio6>;
254 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
255 };
256};
257
258&usbhshost {
259 port1-mode = "ehci-phy";
260};
261
262&usbhsehci {
263 phys = <&hsusb1_phy>;
264};
265
266&vpll2 {
267 /* Needed for DSS */
268 regulator-name = "vdds_dsi";
269};
270
271&dss {
272 status = "ok";
273
274 port {
275 dpi_out: endpoint {
276 remote-endpoint = <&tfp410_in>;
277 data-lines = <24>;
278 };
279 };
280}; 67};
diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
new file mode 100644
index 000000000000..0cb1527c39d4
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi
@@ -0,0 +1,60 @@
1/*
2 * Common Device Tree Source for IGEP COM MODULE
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep.dtsi"
13
14/ {
15 leds: gpio_leds {
16 compatible = "gpio-leds";
17
18 user0 {
19 label = "omap3:red:user0";
20 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
21 default-state = "off";
22 };
23
24 user1 {
25 label = "omap3:green:user1";
26 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
27 default-state = "off";
28 };
29
30 user2 {
31 label = "omap3:red:user1";
32 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */
33 default-state = "off";
34 };
35 };
36};
37
38&omap3_pmx_core {
39 uart2_pins: pinmux_uart2_pins {
40 pinctrl-single,pins = <
41 OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */
42 OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */
43 OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */
44 OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */
45 >;
46 };
47};
48
49&omap3_pmx_core2 {
50 leds_core2_pins: pinmux_leds_core2_pins {
51 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
53 >;
54 };
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
60};
diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
new file mode 100644
index 000000000000..9326b282c94a
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts
@@ -0,0 +1,67 @@
1/*
2 * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
3 *
4 * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include "omap3-igep0030-common.dtsi"
13
14/ {
15 model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3";
17
18 /* Regulator to trigger the WL_EN signal of the Wifi module */
19 lbep5clwmc_wlen: regulator-lbep5clwmc-wlen {
20 compatible = "regulator-fixed";
21 regulator-name = "regulator-lbep5clwmc-wlen";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */
25 enable-active-high;
26 };
27};
28
29&omap3_pmx_core {
30 lbep5clwmc_pins: pinmux_lbep5clwmc_pins {
31 pinctrl-single,pins = <
32 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */
33 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */
34 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */
35 >;
36 };
37
38 leds_pins: pinmux_leds_pins {
39 pinctrl-single,pins = <
40 OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */
41 >;
42 };
43
44};
45
46&i2c2 {
47 status = "disabled";
48};
49
50&leds {
51 pinctrl-names = "default";
52 pinctrl-0 = <&leds_pins &leds_core2_pins>;
53
54 boot {
55 label = "omap3:green:boot";
56 gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
57 default-state = "on";
58 };
59};
60
61&mmc2 {
62 pinctrl-names = "default";
63 pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>;
64 vmmc-supply = <&lbep5clwmc_wlen>;
65 bus-width = <4>;
66 non-removable;
67};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 2793749eb1ba..8150f47ccdf5 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) 2 * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)
3 * 3 *
4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> 4 * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> 5 * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
@@ -9,97 +9,62 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11 11
12#include "omap3-igep.dtsi" 12#include "omap3-igep0030-common.dtsi"
13 13
14/ { 14/ {
15 model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; 15 model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)";
16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3";
17 17
18 leds { 18 /* Regulator to trigger the WIFI_PDN signal of the Wifi module */
19 pinctrl-names = "default"; 19 lbee1usjyc_pdn: lbee1usjyc_pdn {
20 pinctrl-0 = <&leds_pins>; 20 compatible = "regulator-fixed";
21 compatible = "gpio-leds"; 21 regulator-name = "regulator-lbee1usjyc-pdn";
22 22 regulator-min-microvolt = <3300000>;
23 boot { 23 regulator-max-microvolt = <3300000>;
24 label = "omap3:green:boot"; 24 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */
25 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; 25 startup-delay-us = <10000>;
26 default-state = "on"; 26 enable-active-high;
27 }; 27 };
28
29 user0 {
30 label = "omap3:red:user0";
31 gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
32 default-state = "off";
33 };
34
35 user1 {
36 label = "omap3:green:user1";
37 gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
38 default-state = "off";
39 };
40 28
41 user2 { 29 /* Regulator to trigger the RESET_N_W signal of the Wifi module */
42 label = "omap3:red:user1"; 30 lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w {
43 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 31 compatible = "regulator-fixed";
44 default-state = "off"; 32 regulator-name = "regulator-lbee1usjyc-reset-n-w";
45 }; 33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */
36 enable-active-high;
46 }; 37 };
47}; 38};
48 39
49&omap3_pmx_core2 { 40&omap3_pmx_core {
50 leds_pins: pinmux_leds_pins { 41 lbee1usjyc_pins: pinmux_lbee1usjyc_pins {
51 pinctrl-single,pins = < 42 pinctrl-single,pins = <
52 OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ 43 OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */
44 OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */
45 OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */
53 >; 46 >;
54 }; 47 };
55}; 48};
56 49
57&gpmc { 50&leds {
58 ranges = <0 0 0x00000000 0x20000000>; 51 pinctrl-names = "default";
59 52 pinctrl-0 = <&leds_core2_pins>;
60 nand@0,0 {
61 linux,mtd-name= "micron,mt29c4g96maz";
62 reg = <0 0 0>;
63 nand-bus-width = <16>;
64 ti,nand-ecc-opt = "bch8";
65 53
66 gpmc,sync-clk-ps = <0>; 54 boot {
67 gpmc,cs-on-ns = <0>; 55 label = "omap3:green:boot";
68 gpmc,cs-rd-off-ns = <44>; 56 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */
69 gpmc,cs-wr-off-ns = <44>; 57 default-state = "on";
70 gpmc,adv-on-ns = <6>;
71 gpmc,adv-rd-off-ns = <34>;
72 gpmc,adv-wr-off-ns = <44>;
73 gpmc,we-off-ns = <40>;
74 gpmc,oe-off-ns = <54>;
75 gpmc,access-ns = <64>;
76 gpmc,rd-cycle-ns = <82>;
77 gpmc,wr-cycle-ns = <82>;
78 gpmc,wr-access-ns = <40>;
79 gpmc,wr-data-mux-bus-ns = <0>;
80
81 #address-cells = <1>;
82 #size-cells = <1>;
83
84 partition@0 {
85 label = "SPL";
86 reg = <0 0x100000>;
87 };
88 partition@80000 {
89 label = "U-Boot";
90 reg = <0x100000 0x180000>;
91 };
92 partition@1c0000 {
93 label = "Environment";
94 reg = <0x280000 0x100000>;
95 };
96 partition@280000 {
97 label = "Kernel";
98 reg = <0x380000 0x300000>;
99 };
100 partition@780000 {
101 label = "Filesystem";
102 reg = <0x680000 0x1f980000>;
103 };
104 }; 58 };
105}; 59};
60
61/* On board Wifi module */
62&mmc2 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>;
65 vmmc-supply = <&lbee1usjyc_pdn>;
66 vmmc_aux-supply = <&lbee1usjyc_reset_n_w>;
67 bus-width = <4>;
68 non-removable;
69};
70
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 77fee3fb7515..b699bc48f242 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -102,8 +102,9 @@
102 102
103 nand@0,0 { 103 nand@0,0 {
104 linux,mtd-name= "micron,nand"; 104 linux,mtd-name= "micron,nand";
105 reg = <0 0 0>; 105 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
106 nand-bus-width = <16>; 106 nand-bus-width = <16>;
107 gpmc,device-width = <2>;
107 ti,nand-ecc-opt = "bch8"; 108 ti,nand-ecc-opt = "bch8";
108 109
109 gpmc,sync-clk-ps = <0>; 110 gpmc,sync-clk-ps = <0>;
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index d97308896f0c..e81fb651d5d0 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -363,7 +363,7 @@
363 <7 0 0x15000000 0x01000000>; 363 <7 0 0x15000000 0x01000000>;
364 364
365 nand@0,0 { 365 nand@0,0 {
366 reg = <0 0 0x1000000>; 366 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
367 nand-bus-width = <16>; 367 nand-bus-width = <16>;
368 ti,nand-ecc-opt = "bch8"; 368 ti,nand-ecc-opt = "bch8";
369 /* no elm on omap3 */ 369 /* no elm on omap3 */
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index bc82a12d4c2c..53f3ca064140 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -115,6 +115,12 @@
115 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ 115 eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
116 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; 116 speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
117 }; 117 };
118
119 battery: n900-battery {
120 compatible = "nokia,n900-battery";
121 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
122 io-channel-names = "temp", "bsi", "vbat";
123 };
118}; 124};
119 125
120&omap3_pmx_core { 126&omap3_pmx_core {
@@ -142,6 +148,33 @@
142 >; 148 >;
143 }; 149 };
144 150
151 gpmc_pins: pinmux_gpmc_pins {
152 pinctrl-single,pins = <
153
154 /* address lines */
155 OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */
156 OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */
157 OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */
158
159 /* data lines, gpmc_d0..d7 not muxable according to TRM */
160 OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */
161 OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */
162 OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */
163 OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */
164 OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */
165 OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */
166 OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */
167 OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */
168
169 /*
170 * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable
171 * according to TRM. OneNAND seems to require PIN_INPUT on clock.
172 */
173 OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */
174 OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */
175 >;
176 };
177
145 i2c1_pins: pinmux_i2c1_pins { 178 i2c1_pins: pinmux_i2c1_pins {
146 pinctrl-single,pins = < 179 pinctrl-single,pins = <
147 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ 180 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
@@ -540,6 +573,16 @@
540 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ 573 power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */
541 }; 574 };
542 575
576 si4713: si4713@63 {
577 compatible = "silabs,si4713";
578 reg = <0x63>;
579
580 interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */
581 reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */
582 vio-supply = <&vio>;
583 vdd-supply = <&vaux1>;
584 };
585
543 bq24150a: bq24150a@6b { 586 bq24150a: bq24150a@6b {
544 compatible = "ti,bq24150a"; 587 compatible = "ti,bq24150a";
545 reg = <0x6b>; 588 reg = <0x6b>;
@@ -585,16 +628,16 @@
585}; 628};
586 629
587&gpmc { 630&gpmc {
588 ranges = <0 0 0x04000000 0x10000000>; /* 256MB */
589 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ 631 ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
590 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ 632 <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
633 pinctrl-names = "default";
634 pinctrl-0 = <&gpmc_pins>;
591 635
592 /* gpio-irq for dma: 65 */ 636 /* sys_ndmareq1 could be used by the driver, not as gpio65 though */
593
594 onenand@0,0 { 637 onenand@0,0 {
595 #address-cells = <1>; 638 #address-cells = <1>;
596 #size-cells = <1>; 639 #size-cells = <1>;
597 reg = <0 0 0x10000000>; 640 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
598 641
599 gpmc,sync-read; 642 gpmc,sync-read;
600 gpmc,sync-write; 643 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 70addcba37c5..1e49dfe7e212 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -115,12 +115,12 @@
115}; 115};
116 116
117&gpmc { 117&gpmc {
118 ranges = <0 0 0x04000000 0x20000000>; 118 ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */
119 119
120 onenand@0,0 { 120 onenand@0,0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 reg = <0 0 0x20000000>; 123 reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
124 124
125 gpmc,sync-read; 125 gpmc,sync-read;
126 gpmc,sync-write; 126 gpmc,sync-write;
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index d59e3de1441e..827f614261f6 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,6 +2,59 @@
2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 2 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
3 */ 3 */
4 4
5/ {
6 tfp410: encoder@0 {
7 compatible = "ti,tfp410";
8
9 powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */
10
11 pinctrl-names = "default";
12 pinctrl-0 = <&tfp410_pins>;
13
14 ports {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 port@0 {
19 reg = <0>;
20
21 tfp410_in: endpoint@0 {
22 remote-endpoint = <&dpi_out>;
23 };
24 };
25
26 port@1 {
27 reg = <1>;
28
29 tfp410_out: endpoint@0 {
30 remote-endpoint = <&dvi_connector_in>;
31 };
32 };
33 };
34 };
35
36 dvi0: connector@0 {
37 compatible = "dvi-connector";
38 label = "dvi";
39
40 port {
41 dvi_connector_in: endpoint {
42 remote-endpoint = <&tfp410_out>;
43 };
44 };
45 };
46
47 audio_amp: audio_amp {
48 compatible = "regulator-fixed";
49 regulator-name = "audio_amp";
50 pinctrl-names = "default";
51 pinctrl-0 = <&sb_t35_audio_amp>;
52 gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */
53 enable-active-low;
54 regulator-always-on;
55 };
56};
57
5&omap3_pmx_core { 58&omap3_pmx_core {
6 smsc2_pins: pinmux_smsc2_pins { 59 smsc2_pins: pinmux_smsc2_pins {
7 pinctrl-single,pins = < 60 pinctrl-single,pins = <
@@ -9,6 +62,38 @@
9 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ 62 OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */
10 >; 63 >;
11 }; 64 };
65
66 tfp410_pins: pinmux_tfp410_pins {
67 pinctrl-single,pins = <
68 OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */
69 >;
70 };
71
72 i2c3_pins: pinmux_i2c3_pins {
73 pinctrl-single,pins = <
74 OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
75 OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
76 >;
77 };
78
79 sb_t35_audio_amp: pinmux_sb_t35_audio_amp {
80 pinctrl-single,pins = <
81 OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */
82 >;
83 };
84};
85
86&i2c3 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c3_pins>;
89
90 clock-frequency = <400000>;
91
92 at24@50 {
93 compatible = "at24,24c02";
94 pagesize = <16>;
95 reg = <0x50>;
96 };
12}; 97};
13 98
14&gpmc { 99&gpmc {
@@ -22,24 +107,29 @@
22 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 107 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
23 reg = <4 0 0xff>; 108 reg = <4 0 0xff>;
24 bank-width = <2>; 109 bank-width = <2>;
25 gpmc,mux-add-data; 110 gpmc,device-width = <1>;
26 gpmc,cs-on-ns = <1>; 111 gpmc,cycle2cycle-samecsen = <1>;
27 gpmc,cs-rd-off-ns = <180>; 112 gpmc,cycle2cycle-diffcsen = <1>;
28 gpmc,cs-wr-off-ns = <180>; 113 gpmc,cs-on-ns = <5>;
29 gpmc,adv-rd-off-ns = <18>; 114 gpmc,cs-rd-off-ns = <150>;
30 gpmc,adv-wr-off-ns = <48>; 115 gpmc,cs-wr-off-ns = <150>;
31 gpmc,oe-on-ns = <54>; 116 gpmc,adv-on-ns = <0>;
32 gpmc,oe-off-ns = <168>; 117 gpmc,adv-rd-off-ns = <15>;
33 gpmc,we-on-ns = <54>; 118 gpmc,adv-wr-off-ns = <40>;
34 gpmc,we-off-ns = <168>; 119 gpmc,oe-on-ns = <45>;
35 gpmc,rd-cycle-ns = <186>; 120 gpmc,oe-off-ns = <140>;
36 gpmc,wr-cycle-ns = <186>; 121 gpmc,we-on-ns = <45>;
37 gpmc,access-ns = <144>; 122 gpmc,we-off-ns = <140>;
38 gpmc,page-burst-access-ns = <24>; 123 gpmc,rd-cycle-ns = <155>;
39 gpmc,bus-turnaround-ns = <90>; 124 gpmc,wr-cycle-ns = <155>;
40 gpmc,cycle2cycle-delay-ns = <90>; 125 gpmc,access-ns = <120>;
41 gpmc,cycle2cycle-samecsen; 126 gpmc,page-burst-access-ns = <20>;
42 gpmc,cycle2cycle-diffcsen; 127 gpmc,bus-turnaround-ns = <75>;
128 gpmc,cycle2cycle-delay-ns = <75>;
129 gpmc,wait-monitoring-ns = <0>;
130 gpmc,clk-activation-ns = <0>;
131 gpmc,wr-data-mux-bus-ns = <0>;
132 gpmc,wr-access-ns = <0>;
43 vddvario-supply = <&vddvario>; 133 vddvario-supply = <&vddvario>;
44 vdd33a-supply = <&vdd33a>; 134 vdd33a-supply = <&vdd33a>;
45 reg-io-width = <4>; 135 reg-io-width = <4>;
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 42189b65d393..17986536c61f 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -9,6 +9,11 @@
9 model = "CompuLab SBC-T3517 with CM-T3517"; 9 model = "CompuLab SBC-T3517 with CM-T3517";
10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
11 11
12 aliases {
13 display0 = &dvi0;
14 display1 = &tv0;
15 };
16
12 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ 17 /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
13 vddvario: regulator-vddvario-sb-t35 { 18 vddvario: regulator-vddvario-sb-t35 {
14 compatible = "regulator-fixed"; 19 compatible = "regulator-fixed";
@@ -54,3 +59,13 @@
54 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ 59 wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */
55 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ 60 cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */
56}; 61};
62
63&dss {
64 port {
65 dpi_out: endpoint {
66 remote-endpoint = <&tfp410_in>;
67 data-lines = <24>;
68 };
69 };
70};
71
diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts
index bbbeea6b1988..c994f0f7e38a 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3530.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts
@@ -8,6 +8,11 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3530 with CM-T3530"; 9 model = "CompuLab SBC-T3530 with CM-T3530";
10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 display1 = &tv0;
15 };
11}; 16};
12 17
13&omap3_pmx_core { 18&omap3_pmx_core {
@@ -34,3 +39,13 @@
34&mmc1 { 39&mmc1 {
35 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; 40 cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>;
36}; 41};
42
43&dss {
44 port {
45 dpi_out: endpoint {
46 remote-endpoint = <&tfp410_in>;
47 data-lines = <24>;
48 };
49 };
50};
51
diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts
index 08e4a7086f22..5bdddf29341d 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3730.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts
@@ -8,6 +8,11 @@
8/ { 8/ {
9 model = "CompuLab SBC-T3730 with CM-T3730"; 9 model = "CompuLab SBC-T3730 with CM-T3730";
10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; 10 compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3";
11
12 aliases {
13 display0 = &dvi0;
14 display1 = &tv0;
15 };
11}; 16};
12 17
13&omap3_pmx_core { 18&omap3_pmx_core {
@@ -25,3 +30,13 @@
25 ranges = <5 0 0x2c000000 0x01000000>, 30 ranges = <5 0 0x2c000000 0x01000000>,
26 <4 0 0x2d000000 0x01000000>; 31 <4 0 0x2d000000 0x01000000>;
27}; 32};
33
34&dss {
35 port {
36 dpi_out: endpoint {
37 remote-endpoint = <&tfp410_in>;
38 data-lines = <24>;
39 };
40 };
41};
42
diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi
index b30f387d3a83..e89820a6776e 100644
--- a/arch/arm/boot/dts/omap3-tao3530.dtsi
+++ b/arch/arm/boot/dts/omap3-tao3530.dtsi
@@ -270,7 +270,7 @@
270 ranges = <0 0 0x00000000 0x01000000>; 270 ranges = <0 0 0x00000000 0x01000000>;
271 271
272 nand@0,0 { 272 nand@0,0 {
273 reg = <0 0 0>; /* CS0, offset 0 */ 273 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
274 nand-bus-width = <16>; 274 nand-bus-width = <16>;
275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ 275 gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */
276 ti,nand-ecc-opt = "sw"; 276 ti,nand-ecc-opt = "sw";
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index e602e75ce5b7..01b71111bd55 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -332,6 +332,7 @@
332 ti,hwmods = "mailbox"; 332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>; 333 reg = <0x48094000 0x200>;
334 interrupts = <26>; 334 interrupts = <26>;
335 #mbox-cells = <1>;
335 ti,mbox-num-users = <2>; 336 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>; 337 ti,mbox-num-fifos = <2>;
337 mbox_dsp: dsp { 338 mbox_dsp: dsp {
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 9bad94efe1c8..16b0cdfbee9c 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -51,8 +51,8 @@
51 51
52&gpmc { 52&gpmc {
53 ranges = <0 0 0x10000000 0x08000000>, 53 ranges = <0 0 0x10000000 0x08000000>,
54 <1 0 0x28000000 0x08000000>, 54 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
55 <2 0 0x20000000 0x10000000>; 55 <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */
56 56
57 nor@0,0 { 57 nor@0,0 {
58 compatible = "cfi-flash"; 58 compatible = "cfi-flash";
@@ -106,7 +106,7 @@
106 linux,mtd-name= "micron,mt29f1g08abb"; 106 linux,mtd-name= "micron,mt29f1g08abb";
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <1>; 108 #size-cells = <1>;
109 reg = <1 0 0x08000000>; 109 reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
110 ti,nand-ecc-opt = "sw"; 110 ti,nand-ecc-opt = "sw";
111 nand-bus-width = <8>; 111 nand-bus-width = <8>;
112 gpmc,cs-on-ns = <0>; 112 gpmc,cs-on-ns = <0>;
@@ -150,7 +150,7 @@
150 linux,mtd-name= "samsung,kfm2g16q2m-deb8"; 150 linux,mtd-name= "samsung,kfm2g16q2m-deb8";
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 reg = <2 0 0x10000000>; 153 reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */
154 154
155 gpmc,device-width = <2>; 155 gpmc,device-width = <2>;
156 gpmc,mux-add-data = <2>; 156 gpmc,mux-add-data = <2>;
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 6dc84d9f9b4c..1a78f013f37a 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -177,6 +177,7 @@
177 177
178&hdmi { 178&hdmi {
179 status = "ok"; 179 status = "ok";
180 vdda-supply = <&vdac>;
180 181
181 pinctrl-names = "default"; 182 pinctrl-names = "default";
182 pinctrl-0 = <&dss_hdmi_pins>; 183 pinctrl-0 = <&dss_hdmi_pins>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 84045a5c3ce8..074147cebae4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -661,6 +661,7 @@
661 reg = <0x4a0f4000 0x200>; 661 reg = <0x4a0f4000 0x200>;
662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
663 ti,hwmods = "mailbox"; 663 ti,hwmods = "mailbox";
664 #mbox-cells = <1>;
664 ti,mbox-num-users = <3>; 665 ti,mbox-num-users = <3>;
665 ti,mbox-num-fifos = <8>; 666 ti,mbox-num-fifos = <8>;
666 mbox_ipu: mbox_ipu { 667 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 256b7f69e45b..b321fdf42c9f 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -651,6 +651,7 @@
651 reg = <0x4a0f4000 0x200>; 651 reg = <0x4a0f4000 0x200>;
652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 652 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
653 ti,hwmods = "mailbox"; 653 ti,hwmods = "mailbox";
654 #mbox-cells = <1>;
654 ti,mbox-num-users = <3>; 655 ti,mbox-num-users = <3>;
655 ti,mbox-num-fifos = <8>; 656 ti,mbox-num-fifos = <8>;
656 mbox_ipu: mbox_ipu { 657 mbox_ipu: mbox_ipu {
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 963b7e54ab15..1ca1a9aa953f 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -41,6 +41,11 @@
41 }; 41 };
42 }; 42 };
43 43
44 arm-pmu {
45 compatible = "arm,cortex-a9-pmu";
46 interrupts = <29>;
47 };
48
44 axi { 49 axi {
45 compatible = "simple-bus"; 50 compatible = "simple-bus";
46 #address-cells = <1>; 51 #address-cells = <1>;
@@ -132,6 +137,7 @@
132 reg = <0x90020000 0x10000>; 137 reg = <0x90020000 0x10000>;
133 interrupts = <31>; 138 interrupts = <31>;
134 clocks = <&clks 35>; 139 clocks = <&clks 35>;
140 resets = <&rstc 6>;
135 }; 141 };
136 }; 142 };
137 143
@@ -173,6 +179,7 @@
173 compatible = "sirf,prima2-dspif"; 179 compatible = "sirf,prima2-dspif";
174 reg = <0xa8000000 0x10000>; 180 reg = <0xa8000000 0x10000>;
175 interrupts = <9>; 181 interrupts = <9>;
182 resets = <&rstc 1>;
176 }; 183 };
177 184
178 gps@a8010000 { 185 gps@a8010000 {
@@ -180,6 +187,7 @@
180 reg = <0xa8010000 0x10000>; 187 reg = <0xa8010000 0x10000>;
181 interrupts = <7>; 188 interrupts = <7>;
182 clocks = <&clks 9>; 189 clocks = <&clks 9>;
190 resets = <&rstc 2>;
183 }; 191 };
184 192
185 dsp@a9000000 { 193 dsp@a9000000 {
@@ -187,6 +195,7 @@
187 reg = <0xa9000000 0x1000000>; 195 reg = <0xa9000000 0x1000000>;
188 interrupts = <8>; 196 interrupts = <8>;
189 clocks = <&clks 8>; 197 clocks = <&clks 8>;
198 resets = <&rstc 0>;
190 }; 199 };
191 }; 200 };
192 201
@@ -524,12 +533,36 @@
524 sirf,function = "sdmmc5"; 533 sirf,function = "sdmmc5";
525 }; 534 };
526 }; 535 };
536 i2s_mclk_pins_a: i2s_mclk@0 {
537 i2s_mclk {
538 sirf,pins = "i2smclkgrp";
539 sirf,function = "i2s_mclk";
540 };
541 };
542 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
543 i2s_ext_clk_input {
544 sirf,pins = "i2s_ext_clk_inputgrp";
545 sirf,function = "i2s_ext_clk_input";
546 };
547 };
527 i2s_pins_a: i2s@0 { 548 i2s_pins_a: i2s@0 {
528 i2s { 549 i2s {
529 sirf,pins = "i2sgrp"; 550 sirf,pins = "i2sgrp";
530 sirf,function = "i2s"; 551 sirf,function = "i2s";
531 }; 552 };
532 }; 553 };
554 i2s_no_din_pins_a: i2s_no_din@0 {
555 i2s_no_din {
556 sirf,pins = "i2s_no_dingrp";
557 sirf,function = "i2s_no_din";
558 };
559 };
560 i2s_6chn_pins_a: i2s_6chn@0 {
561 i2s_6chn {
562 sirf,pins = "i2s_6chngrp";
563 sirf,function = "i2s_6chn";
564 };
565 };
533 ac97_pins_a: ac97@0 { 566 ac97_pins_a: ac97@0 {
534 ac97 { 567 ac97 {
535 sirf,pins = "ac97grp"; 568 sirf,pins = "ac97grp";
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 2bcf69124a6a..84e05f713c54 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -94,6 +94,10 @@
94 voltage-tolerance = <1>; /* 1% */ 94 voltage-tolerance = <1>; /* 1% */
95}; 95};
96 96
97&cmt1 {
98 status = "okay";
99};
100
97&pfc { 101&pfc {
98 scifa0_pins: serial0 { 102 scifa0_pins: serial0 {
99 renesas,groups = "scifa0_data"; 103 renesas,groups = "scifa0_data";
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index c17afef92e8d..5ac57babc3b9 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -106,9 +106,20 @@
106 i2c5: i2c@e60b0000 { 106 i2c5: i2c@e60b0000 {
107 #address-cells = <1>; 107 #address-cells = <1>;
108 #size-cells = <0>; 108 #size-cells = <0>;
109 compatible = "renesas,rmobile-iic"; 109 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
110 reg = <0 0xe60b0000 0 0x428>; 110 reg = <0 0xe60b0000 0 0x428>;
111 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; 111 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
112
113 status = "disabled";
114 };
115
116 cmt1: timer@e6130000 {
117 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
118 reg = <0 0xe6130000 0 0x1004>;
119 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
120
121 renesas,channels-mask = <0xff>;
122
112 status = "disabled"; 123 status = "disabled";
113 }; 124 };
114 125
@@ -194,7 +205,7 @@
194 i2c0: i2c@e6500000 { 205 i2c0: i2c@e6500000 {
195 #address-cells = <1>; 206 #address-cells = <1>;
196 #size-cells = <0>; 207 #size-cells = <0>;
197 compatible = "renesas,rmobile-iic"; 208 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
198 reg = <0 0xe6500000 0 0x428>; 209 reg = <0 0xe6500000 0 0x428>;
199 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 210 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
200 status = "disabled"; 211 status = "disabled";
@@ -203,7 +214,7 @@
203 i2c1: i2c@e6510000 { 214 i2c1: i2c@e6510000 {
204 #address-cells = <1>; 215 #address-cells = <1>;
205 #size-cells = <0>; 216 #size-cells = <0>;
206 compatible = "renesas,rmobile-iic"; 217 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
207 reg = <0 0xe6510000 0 0x428>; 218 reg = <0 0xe6510000 0 0x428>;
208 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 219 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
209 status = "disabled"; 220 status = "disabled";
@@ -212,7 +223,7 @@
212 i2c2: i2c@e6520000 { 223 i2c2: i2c@e6520000 {
213 #address-cells = <1>; 224 #address-cells = <1>;
214 #size-cells = <0>; 225 #size-cells = <0>;
215 compatible = "renesas,rmobile-iic"; 226 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
216 reg = <0 0xe6520000 0 0x428>; 227 reg = <0 0xe6520000 0 0x428>;
217 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 228 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
218 status = "disabled"; 229 status = "disabled";
@@ -221,7 +232,7 @@
221 i2c3: i2c@e6530000 { 232 i2c3: i2c@e6530000 {
222 #address-cells = <1>; 233 #address-cells = <1>;
223 #size-cells = <0>; 234 #size-cells = <0>;
224 compatible = "renesas,rmobile-iic"; 235 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
225 reg = <0 0xe6530000 0 0x428>; 236 reg = <0 0xe6530000 0 0x428>;
226 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; 237 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
227 status = "disabled"; 238 status = "disabled";
@@ -230,7 +241,7 @@
230 i2c4: i2c@e6540000 { 241 i2c4: i2c@e6540000 {
231 #address-cells = <1>; 242 #address-cells = <1>;
232 #size-cells = <0>; 243 #size-cells = <0>;
233 compatible = "renesas,rmobile-iic"; 244 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
234 reg = <0 0xe6540000 0 0x428>; 245 reg = <0 0xe6540000 0 0x428>;
235 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; 246 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
236 status = "disabled"; 247 status = "disabled";
@@ -239,7 +250,7 @@
239 i2c6: i2c@e6550000 { 250 i2c6: i2c@e6550000 {
240 #address-cells = <1>; 251 #address-cells = <1>;
241 #size-cells = <0>; 252 #size-cells = <0>;
242 compatible = "renesas,rmobile-iic"; 253 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
243 reg = <0 0xe6550000 0 0x428>; 254 reg = <0 0xe6550000 0 0x428>;
244 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 255 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
245 status = "disabled"; 256 status = "disabled";
@@ -248,7 +259,7 @@
248 i2c7: i2c@e6560000 { 259 i2c7: i2c@e6560000 {
249 #address-cells = <1>; 260 #address-cells = <1>;
250 #size-cells = <0>; 261 #size-cells = <0>;
251 compatible = "renesas,rmobile-iic"; 262 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
252 reg = <0 0xe6560000 0 0x428>; 263 reg = <0 0xe6560000 0 0x428>;
253 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; 264 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
254 status = "disabled"; 265 status = "disabled";
@@ -257,20 +268,20 @@
257 i2c8: i2c@e6570000 { 268 i2c8: i2c@e6570000 {
258 #address-cells = <1>; 269 #address-cells = <1>;
259 #size-cells = <0>; 270 #size-cells = <0>;
260 compatible = "renesas,rmobile-iic"; 271 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
261 reg = <0 0xe6570000 0 0x428>; 272 reg = <0 0xe6570000 0 0x428>;
262 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 273 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
263 status = "disabled"; 274 status = "disabled";
264 }; 275 };
265 276
266 scifb2: serial@e6c20000 { 277 scifb0: serial@e6c20000 {
267 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 278 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
268 reg = <0 0xe6c20000 0 0x100>; 279 reg = <0 0xe6c20000 0 0x100>;
269 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
270 status = "disabled"; 281 status = "disabled";
271 }; 282 };
272 283
273 scifb3: serial@e6c30000 { 284 scifb1: serial@e6c30000 {
274 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 285 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
275 reg = <0 0xe6c30000 0 0x100>; 286 reg = <0 0xe6c30000 0 0x100>;
276 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 287 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
@@ -291,14 +302,14 @@
291 status = "disabled"; 302 status = "disabled";
292 }; 303 };
293 304
294 scifb4: serial@e6ce0000 { 305 scifb2: serial@e6ce0000 {
295 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 306 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
296 reg = <0 0xe6ce0000 0 0x100>; 307 reg = <0 0xe6ce0000 0 0x100>;
297 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 308 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
298 status = "disabled"; 309 status = "disabled";
299 }; 310 };
300 311
301 scifb5: serial@e6cf0000 { 312 scifb3: serial@e6cf0000 {
302 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 313 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
303 reg = <0 0xe6cf0000 0 0x100>; 314 reg = <0 0xe6cf0000 0 0x100>;
304 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 2703428557fc..d4af4d86c6b0 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -78,7 +78,7 @@
78 regulator-boot-on; 78 regulator-boot-on;
79 }; 79 };
80 80
81 gpio-keys { 81 keyboard {
82 compatible = "gpio-keys"; 82 compatible = "gpio-keys";
83 83
84 power-key { 84 power-key {
@@ -299,3 +299,7 @@
299 299
300 status = "okay"; 300 status = "okay";
301}; 301};
302
303&tmu0 {
304 status = "okay";
305};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index eed697a6bd6b..a8a674bafa67 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -71,6 +71,7 @@
71 0 149 IRQ_TYPE_LEVEL_HIGH 71 0 149 IRQ_TYPE_LEVEL_HIGH
72 0 149 IRQ_TYPE_LEVEL_HIGH 72 0 149 IRQ_TYPE_LEVEL_HIGH
73 0 149 IRQ_TYPE_LEVEL_HIGH>; 73 0 149 IRQ_TYPE_LEVEL_HIGH>;
74 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
74 }; 75 };
75 76
76 /* irqpin1: IRQ8 - IRQ15 */ 77 /* irqpin1: IRQ8 - IRQ15 */
@@ -91,6 +92,7 @@
91 0 149 IRQ_TYPE_LEVEL_HIGH 92 0 149 IRQ_TYPE_LEVEL_HIGH
92 0 149 IRQ_TYPE_LEVEL_HIGH 93 0 149 IRQ_TYPE_LEVEL_HIGH
93 0 149 IRQ_TYPE_LEVEL_HIGH>; 94 0 149 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
94 }; 96 };
95 97
96 /* irqpin2: IRQ16 - IRQ23 */ 98 /* irqpin2: IRQ16 - IRQ23 */
@@ -111,6 +113,7 @@
111 0 149 IRQ_TYPE_LEVEL_HIGH 113 0 149 IRQ_TYPE_LEVEL_HIGH
112 0 149 IRQ_TYPE_LEVEL_HIGH 114 0 149 IRQ_TYPE_LEVEL_HIGH
113 0 149 IRQ_TYPE_LEVEL_HIGH>; 115 0 149 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
114 }; 117 };
115 118
116 /* irqpin3: IRQ24 - IRQ31 */ 119 /* irqpin3: IRQ24 - IRQ31 */
@@ -131,6 +134,7 @@
131 0 149 IRQ_TYPE_LEVEL_HIGH 134 0 149 IRQ_TYPE_LEVEL_HIGH
132 0 149 IRQ_TYPE_LEVEL_HIGH 135 0 149 IRQ_TYPE_LEVEL_HIGH
133 0 149 IRQ_TYPE_LEVEL_HIGH>; 136 0 149 IRQ_TYPE_LEVEL_HIGH>;
137 clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
134 }; 138 };
135 139
136 ether: ethernet@e9a00000 { 140 ether: ethernet@e9a00000 {
@@ -193,7 +197,7 @@
193 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 197 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
194 reg = <0xe6c60000 0x100>; 198 reg = <0xe6c60000 0x100>;
195 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; 199 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 200 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
197 clock-names = "sci_ick"; 201 clock-names = "sci_ick";
198 status = "disabled"; 202 status = "disabled";
199 }; 203 };
@@ -331,6 +335,34 @@
331 status = "disabled"; 335 status = "disabled";
332 }; 336 };
333 337
338 tmu0: timer@fff80000 {
339 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
340 reg = <0xfff80000 0x2c>;
341 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
342 <0 199 IRQ_TYPE_LEVEL_HIGH>,
343 <0 200 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
345 clock-names = "fck";
346
347 #renesas,channels = <3>;
348
349 status = "disabled";
350 };
351
352 tmu1: timer@fff90000 {
353 compatible = "renesas,tmu-r8a7740", "renesas,tmu";
354 reg = <0xfff90000 0x2c>;
355 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>,
356 <0 171 IRQ_TYPE_LEVEL_HIGH>,
357 <0 172 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
359 clock-names = "fck";
360
361 #renesas,channels = <3>;
362
363 status = "disabled";
364 };
365
334 clocks { 366 clocks {
335 #address-cells = <1>; 367 #address-cells = <1>;
336 #size-cells = <1>; 368 #size-cells = <1>;
@@ -448,8 +480,8 @@
448 mstp2_clks: mstp2_clks@e6150138 { 480 mstp2_clks: mstp2_clks@e6150138 {
449 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 481 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
450 reg = <0xe6150138 4>, <0xe6150040 4>; 482 reg = <0xe6150138 4>, <0xe6150040 4>;
451 clocks = <&sub_clk>, <&sub_clk>, 483 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
452 <&cpg_clocks R8A7740_CLK_HP>, 484 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
453 <&cpg_clocks R8A7740_CLK_HP>, 485 <&cpg_clocks R8A7740_CLK_HP>,
454 <&cpg_clocks R8A7740_CLK_HP>, 486 <&cpg_clocks R8A7740_CLK_HP>,
455 <&cpg_clocks R8A7740_CLK_HP>, 487 <&cpg_clocks R8A7740_CLK_HP>,
@@ -458,7 +490,8 @@
458 <&sub_clk>; 490 <&sub_clk>;
459 #clock-cells = <1>; 491 #clock-cells = <1>;
460 renesas,clock-indices = < 492 renesas,clock-indices = <
461 R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7 493 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
494 R8A7740_CLK_SCIFA7
462 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 495 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
463 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC 496 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
464 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB 497 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
@@ -467,7 +500,8 @@
467 R8A7740_CLK_SCIFA4 500 R8A7740_CLK_SCIFA4
468 >; 501 >;
469 clock-output-names = 502 clock-output-names =
470 "scifa6", "scifa7", "dmac1", "dmac2", "dmac3", 503 "scifa6", "intca",
504 "scifa7", "dmac1", "dmac2", "dmac3",
471 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", 505 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
472 "scifa2", "scifa3", "scifa4"; 506 "scifa2", "scifa3", "scifa4";
473 }; 507 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index fba294905ff4..04c0c37bb784 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -74,6 +74,10 @@
74 status = "okay"; 74 status = "okay";
75}; 75};
76 76
77&tmu0 {
78 status = "okay";
79};
80
77&pfc { 81&pfc {
78 scif0_pins: serial0 { 82 scif0_pins: serial0 {
79 renesas,groups = "scif0_data_a", "scif0_ctrl"; 83 renesas,groups = "scif0_data_a", "scif0_ctrl";
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 315ec62cb96b..ef8533910029 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -162,6 +162,42 @@
162 status = "disabled"; 162 status = "disabled";
163 }; 163 };
164 164
165 tmu0: timer@ffd80000 {
166 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
167 reg = <0xffd80000 0x30>;
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>;
171
172 #renesas,channels = <3>;
173
174 status = "disabled";
175 };
176
177 tmu1: timer@ffd81000 {
178 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
179 reg = <0xffd81000 0x30>;
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>;
183
184 #renesas,channels = <3>;
185
186 status = "disabled";
187 };
188
189 tmu2: timer@ffd82000 {
190 compatible = "renesas,tmu-r8a7778", "renesas,tmu";
191 reg = <0xffd82000 0x30>;
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>;
195
196 #renesas,channels = <3>;
197
198 status = "disabled";
199 };
200
165 scif0: serial@ffe40000 { 201 scif0: serial@ffe40000 {
166 compatible = "renesas,scif-r8a7778", "renesas,scif"; 202 compatible = "renesas,scif-r8a7778", "renesas,scif";
167 reg = <0xffe40000 0x100>; 203 reg = <0xffe40000 0x100>;
@@ -215,8 +251,6 @@
215 compatible = "renesas,sdhi-r8a7778"; 251 compatible = "renesas,sdhi-r8a7778";
216 reg = <0xffe4c000 0x100>; 252 reg = <0xffe4c000 0x100>;
217 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
218 cap-sd-highspeed;
219 cap-sdio-irq;
220 status = "disabled"; 254 status = "disabled";
221 }; 255 };
222 256
@@ -224,8 +258,6 @@
224 compatible = "renesas,sdhi-r8a7778"; 258 compatible = "renesas,sdhi-r8a7778";
225 reg = <0xffe4d000 0x100>; 259 reg = <0xffe4d000 0x100>;
226 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
227 cap-sd-highspeed;
228 cap-sdio-irq;
229 status = "disabled"; 261 status = "disabled";
230 }; 262 };
231 263
@@ -233,8 +265,6 @@
233 compatible = "renesas,sdhi-r8a7778"; 265 compatible = "renesas,sdhi-r8a7778";
234 reg = <0xffe4f000 0x100>; 266 reg = <0xffe4f000 0x100>;
235 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
236 cap-sd-highspeed;
237 cap-sdio-irq;
238 status = "disabled"; 268 status = "disabled";
239 }; 269 };
240 270
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index fda814ed191d..ede9a29e4bc6 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -303,7 +303,7 @@
303 }; 303 };
304 304
305 sata: sata@fc600000 { 305 sata: sata@fc600000 {
306 compatible = "renesas,rcar-sata"; 306 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
307 reg = <0xfc600000 0x2000>; 307 reg = <0xfc600000 0x2000>;
308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 308 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 309 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
@@ -314,8 +314,6 @@
314 reg = <0xffe4c000 0x100>; 314 reg = <0xffe4c000 0x100>;
315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 316 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
317 cap-sd-highspeed;
318 cap-sdio-irq;
319 status = "disabled"; 317 status = "disabled";
320 }; 318 };
321 319
@@ -324,8 +322,6 @@
324 reg = <0xffe4d000 0x100>; 322 reg = <0xffe4d000 0x100>;
325 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 323 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 324 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
327 cap-sd-highspeed;
328 cap-sdio-irq;
329 status = "disabled"; 325 status = "disabled";
330 }; 326 };
331 327
@@ -334,8 +330,6 @@
334 reg = <0xffe4e000 0x100>; 330 reg = <0xffe4e000 0x100>;
335 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 331 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 332 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
337 cap-sd-highspeed;
338 cap-sdio-irq;
339 status = "disabled"; 333 status = "disabled";
340 }; 334 };
341 335
@@ -344,8 +338,6 @@
344 reg = <0xffe4f000 0x100>; 338 reg = <0xffe4f000 0x100>;
345 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 340 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
347 cap-sd-highspeed;
348 cap-sdio-irq;
349 status = "disabled"; 341 status = "disabled";
350 }; 342 };
351 343
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index acab2e153382..636d53bb87a2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -9,6 +9,34 @@
9 * kind, whether express or implied. 9 * kind, whether express or implied.
10 */ 10 */
11 11
12/*
13 * SSI-AK4643
14 *
15 * SW1: 1: AK4643
16 * 2: CN22
17 * 3: ADV7511
18 *
19 * This command is required when Playback/Capture
20 *
21 * amixer set "LINEOUT Mixer DACL" on
22 * amixer set "DVC Out" 100%
23 * amixer set "DVC In" 100%
24 *
25 * You can use Mute
26 *
27 * amixer set "DVC Out Mute" on
28 * amixer set "DVC In Mute" on
29 *
30 * You can use Volume Ramp
31 *
32 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
33 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
34 * amixer set "DVC Out Ramp" on
35 * aplay xxx.wav &
36 * amixer set "DVC Out" 80% // Volume Down
37 * amixer set "DVC Out" 100% // Volume Up
38 */
39
12/dts-v1/; 40/dts-v1/;
13#include "r8a7790.dtsi" 41#include "r8a7790.dtsi"
14#include <dt-bindings/gpio/gpio.h> 42#include <dt-bindings/gpio/gpio.h>
@@ -19,8 +47,8 @@
19 compatible = "renesas,lager", "renesas,r8a7790"; 47 compatible = "renesas,lager", "renesas,r8a7790";
20 48
21 aliases { 49 aliases {
22 serial6 = &scif0; 50 serial6 = &scifa0;
23 serial7 = &scif1; 51 serial7 = &scifa1;
24 }; 52 };
25 53
26 chosen { 54 chosen {
@@ -43,7 +71,7 @@
43 #size-cells = <1>; 71 #size-cells = <1>;
44 }; 72 };
45 73
46 gpio_keys { 74 keyboard {
47 compatible = "gpio-keys"; 75 compatible = "gpio-keys";
48 76
49 button@1 { 77 button@1 {
@@ -146,6 +174,23 @@
146 1800000 0>; 174 1800000 0>;
147 }; 175 };
148 176
177 sound {
178 compatible = "simple-audio-card";
179
180 simple-audio-card,format = "left_j";
181 simple-audio-card,bitclock-master = <&sndcodec>;
182 simple-audio-card,frame-master = <&sndcodec>;
183
184 sndcpu: simple-audio-card,cpu {
185 sound-dai = <&rcar_sound>;
186 };
187
188 sndcodec: simple-audio-card,codec {
189 sound-dai = <&ak4643>;
190 system-clock-frequency = <11289600>;
191 };
192 };
193
149 vga-encoder { 194 vga-encoder {
150 compatible = "adi,adv7123"; 195 compatible = "adi,adv7123";
151 196
@@ -207,9 +252,9 @@
207 renesas,function = "du"; 252 renesas,function = "du";
208 }; 253 };
209 254
210 scif0_pins: serial0 { 255 scifa0_pins: serial0 {
211 renesas,groups = "scif0_data"; 256 renesas,groups = "scifa0_data";
212 renesas,function = "scif0"; 257 renesas,function = "scifa0";
213 }; 258 };
214 259
215 ether_pins: ether { 260 ether_pins: ether {
@@ -222,9 +267,9 @@
222 renesas,function = "intc"; 267 renesas,function = "intc";
223 }; 268 };
224 269
225 scif1_pins: serial1 { 270 scifa1_pins: serial1 {
226 renesas,groups = "scif1_data"; 271 renesas,groups = "scifa1_data";
227 renesas,function = "scif1"; 272 renesas,function = "scifa1";
228 }; 273 };
229 274
230 sdhi0_pins: sd0 { 275 sdhi0_pins: sd0 {
@@ -268,6 +313,11 @@
268 renesas,function = "iic3"; 313 renesas,function = "iic3";
269 }; 314 };
270 315
316 hsusb_pins: hsusb {
317 renesas,groups = "usb0_ovc_vbus";
318 renesas,function = "usb0";
319 };
320
271 usb0_pins: usb0 { 321 usb0_pins: usb0 {
272 renesas,groups = "usb0"; 322 renesas,groups = "usb0";
273 renesas,function = "usb0"; 323 renesas,function = "usb0";
@@ -287,6 +337,16 @@
287 renesas,groups = "vin1_data8", "vin1_clk"; 337 renesas,groups = "vin1_data8", "vin1_clk";
288 renesas,function = "vin1"; 338 renesas,function = "vin1";
289 }; 339 };
340
341 sound_pins: sound {
342 renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
343 renesas,function = "ssi";
344 };
345
346 sound_clk_pins: sound_clk {
347 renesas,groups = "audio_clk_a";
348 renesas,function = "audio_clk";
349 };
290}; 350};
291 351
292&ether { 352&ether {
@@ -356,15 +416,15 @@
356 }; 416 };
357}; 417};
358 418
359&scif0 { 419&scifa0 {
360 pinctrl-0 = <&scif0_pins>; 420 pinctrl-0 = <&scifa0_pins>;
361 pinctrl-names = "default"; 421 pinctrl-names = "default";
362 422
363 status = "okay"; 423 status = "okay";
364}; 424};
365 425
366&scif1 { 426&scifa1 {
367 pinctrl-0 = <&scif1_pins>; 427 pinctrl-0 = <&scifa1_pins>;
368 pinctrl-names = "default"; 428 pinctrl-names = "default";
369 429
370 status = "okay"; 430 status = "okay";
@@ -424,6 +484,14 @@
424 pinctrl-0 = <&iic2_pins>; 484 pinctrl-0 = <&iic2_pins>;
425 pinctrl-names = "default"; 485 pinctrl-names = "default";
426 486
487 clock-frequency = <100000>;
488
489 ak4643: sound-codec@12 {
490 compatible = "asahi-kasei,ak4643";
491 #sound-dai-cells = <0>;
492 reg = <0x12>;
493 };
494
427 composite-in@20 { 495 composite-in@20 {
428 compatible = "adi,adv7180"; 496 compatible = "adi,adv7180";
429 reg = <0x20>; 497 reg = <0x20>;
@@ -466,12 +534,29 @@
466 pinctrl-names = "default"; 534 pinctrl-names = "default";
467}; 535};
468 536
537&xhci {
538 status = "okay";
539 pinctrl-0 = <&usb2_pins>;
540 pinctrl-names = "default";
541};
542
469&pci2 { 543&pci2 {
470 status = "okay"; 544 status = "okay";
471 pinctrl-0 = <&usb2_pins>; 545 pinctrl-0 = <&usb2_pins>;
472 pinctrl-names = "default"; 546 pinctrl-names = "default";
473}; 547};
474 548
549&hsusb {
550 status = "okay";
551 pinctrl-0 = <&hsusb_pins>;
552 pinctrl-names = "default";
553 renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
554};
555
556&usbphy {
557 status = "okay";
558};
559
475/* composite video input */ 560/* composite video input */
476&vin1 { 561&vin1 {
477 pinctrl-0 = <&vin1_pins>; 562 pinctrl-0 = <&vin1_pins>;
@@ -489,3 +574,23 @@
489 }; 574 };
490 }; 575 };
491}; 576};
577
578&rcar_sound {
579 pinctrl-0 = <&sound_pins &sound_clk_pins>;
580 pinctrl-names = "default";
581
582 #sound-dai-cells = <0>;
583
584 status = "okay";
585
586 rcar_sound,dai {
587 dai0 {
588 playback = <&ssi0 &src2 &dvc0>;
589 capture = <&ssi1 &src3 &dvc1>;
590 };
591 };
592};
593
594&ssi1 {
595 shared-pin;
596};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0c20c90d8c06..af7e255f629e 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -312,6 +312,70 @@
312 #dma-cells = <1>; 312 #dma-cells = <1>;
313 dma-channels = <15>; 313 dma-channels = <15>;
314 }; 314 };
315
316 audma0: dma-controller@ec700000 {
317 compatible = "renesas,rcar-dmac";
318 reg = <0 0xec700000 0 0x10000>;
319 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
320 0 320 IRQ_TYPE_LEVEL_HIGH
321 0 321 IRQ_TYPE_LEVEL_HIGH
322 0 322 IRQ_TYPE_LEVEL_HIGH
323 0 323 IRQ_TYPE_LEVEL_HIGH
324 0 324 IRQ_TYPE_LEVEL_HIGH
325 0 325 IRQ_TYPE_LEVEL_HIGH
326 0 326 IRQ_TYPE_LEVEL_HIGH
327 0 327 IRQ_TYPE_LEVEL_HIGH
328 0 328 IRQ_TYPE_LEVEL_HIGH
329 0 329 IRQ_TYPE_LEVEL_HIGH
330 0 330 IRQ_TYPE_LEVEL_HIGH
331 0 331 IRQ_TYPE_LEVEL_HIGH
332 0 332 IRQ_TYPE_LEVEL_HIGH>;
333 interrupt-names = "error",
334 "ch0", "ch1", "ch2", "ch3",
335 "ch4", "ch5", "ch6", "ch7",
336 "ch8", "ch9", "ch10", "ch11",
337 "ch12";
338 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
339 clock-names = "fck";
340 #dma-cells = <1>;
341 dma-channels = <13>;
342 };
343
344 audma1: dma-controller@ec720000 {
345 compatible = "renesas,rcar-dmac";
346 reg = <0 0xec720000 0 0x10000>;
347 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
348 0 333 IRQ_TYPE_LEVEL_HIGH
349 0 334 IRQ_TYPE_LEVEL_HIGH
350 0 335 IRQ_TYPE_LEVEL_HIGH
351 0 336 IRQ_TYPE_LEVEL_HIGH
352 0 337 IRQ_TYPE_LEVEL_HIGH
353 0 338 IRQ_TYPE_LEVEL_HIGH
354 0 339 IRQ_TYPE_LEVEL_HIGH
355 0 340 IRQ_TYPE_LEVEL_HIGH
356 0 341 IRQ_TYPE_LEVEL_HIGH
357 0 342 IRQ_TYPE_LEVEL_HIGH
358 0 343 IRQ_TYPE_LEVEL_HIGH
359 0 344 IRQ_TYPE_LEVEL_HIGH
360 0 345 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "error",
362 "ch0", "ch1", "ch2", "ch3",
363 "ch4", "ch5", "ch6", "ch7",
364 "ch8", "ch9", "ch10", "ch11",
365 "ch12";
366 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
367 clock-names = "fck";
368 #dma-cells = <1>;
369 dma-channels = <13>;
370 };
371
372 audmapp: dma-controller@ec740000 {
373 compatible = "renesas,rcar-audmapp";
374 #dma-cells = <1>;
375
376 reg = <0 0xec740000 0 0x200>;
377 };
378
315 i2c0: i2c@e6508000 { 379 i2c0: i2c@e6508000 {
316 #address-cells = <1>; 380 #address-cells = <1>;
317 #size-cells = <0>; 381 #size-cells = <0>;
@@ -359,6 +423,8 @@
359 reg = <0 0xe6500000 0 0x425>; 423 reg = <0 0xe6500000 0 0x425>;
360 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 424 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7790_CLK_IIC0>; 425 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
426 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
427 dma-names = "tx", "rx";
362 status = "disabled"; 428 status = "disabled";
363 }; 429 };
364 430
@@ -369,6 +435,8 @@
369 reg = <0 0xe6510000 0 0x425>; 435 reg = <0 0xe6510000 0 0x425>;
370 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 436 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7790_CLK_IIC1>; 437 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
438 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
439 dma-names = "tx", "rx";
372 status = "disabled"; 440 status = "disabled";
373 }; 441 };
374 442
@@ -379,6 +447,8 @@
379 reg = <0 0xe6520000 0 0x425>; 447 reg = <0 0xe6520000 0 0x425>;
380 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; 448 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp3_clks R8A7790_CLK_IIC2>; 449 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
450 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
451 dma-names = "tx", "rx";
382 status = "disabled"; 452 status = "disabled";
383 }; 453 };
384 454
@@ -389,14 +459,18 @@
389 reg = <0 0xe60b0000 0 0x425>; 459 reg = <0 0xe60b0000 0 0x425>;
390 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 460 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; 461 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
462 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
463 dma-names = "tx", "rx";
392 status = "disabled"; 464 status = "disabled";
393 }; 465 };
394 466
395 mmcif0: mmcif@ee200000 { 467 mmcif0: mmc@ee200000 {
396 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; 468 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
397 reg = <0 0xee200000 0 0x80>; 469 reg = <0 0xee200000 0 0x80>;
398 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 470 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; 471 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
472 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
473 dma-names = "tx", "rx";
400 reg-io-width = <4>; 474 reg-io-width = <4>;
401 status = "disabled"; 475 status = "disabled";
402 }; 476 };
@@ -406,6 +480,8 @@
406 reg = <0 0xee220000 0 0x80>; 480 reg = <0 0xee220000 0 0x80>;
407 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; 481 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; 482 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
483 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
484 dma-names = "tx", "rx";
409 reg-io-width = <4>; 485 reg-io-width = <4>;
410 status = "disabled"; 486 status = "disabled";
411 }; 487 };
@@ -420,7 +496,6 @@
420 reg = <0 0xee100000 0 0x200>; 496 reg = <0 0xee100000 0 0x200>;
421 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 497 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; 498 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
423 cap-sd-highspeed;
424 status = "disabled"; 499 status = "disabled";
425 }; 500 };
426 501
@@ -429,7 +504,6 @@
429 reg = <0 0xee120000 0 0x200>; 504 reg = <0 0xee120000 0 0x200>;
430 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; 505 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; 506 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
432 cap-sd-highspeed;
433 status = "disabled"; 507 status = "disabled";
434 }; 508 };
435 509
@@ -438,7 +512,6 @@
438 reg = <0 0xee140000 0 0x100>; 512 reg = <0 0xee140000 0 0x100>;
439 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 513 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; 514 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
441 cap-sd-highspeed;
442 status = "disabled"; 515 status = "disabled";
443 }; 516 };
444 517
@@ -447,7 +520,6 @@
447 reg = <0 0xee160000 0 0x100>; 520 reg = <0 0xee160000 0 0x100>;
448 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 521 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; 522 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
450 cap-sd-highspeed;
451 status = "disabled"; 523 status = "disabled";
452 }; 524 };
453 525
@@ -568,6 +640,36 @@
568 status = "disabled"; 640 status = "disabled";
569 }; 641 };
570 642
643 hsusb: usb@e6590000 {
644 compatible = "renesas,usbhs-r8a7790";
645 reg = <0 0xe6590000 0 0x100>;
646 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
648 renesas,buswait = <4>;
649 phys = <&usb0 1>;
650 phy-names = "usb";
651 status = "disabled";
652 };
653
654 usbphy: usb-phy@e6590100 {
655 compatible = "renesas,usb-phy-r8a7790";
656 reg = <0 0xe6590100 0 0x100>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
660 clock-names = "usbhs";
661 status = "disabled";
662
663 usb0: usb-channel@0 {
664 reg = <0>;
665 #phy-cells = <1>;
666 };
667 usb2: usb-channel@2 {
668 reg = <2>;
669 #phy-cells = <1>;
670 };
671 };
672
571 vin0: video@e6ef0000 { 673 vin0: video@e6ef0000 {
572 compatible = "renesas,vin-r8a7790"; 674 compatible = "renesas,vin-r8a7790";
573 clocks = <&mstp8_clks R8A7790_CLK_VIN0>; 675 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
@@ -958,18 +1060,25 @@
958 mstp1_clks: mstp1_clks@e6150134 { 1060 mstp1_clks: mstp1_clks@e6150134 {
959 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1061 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
960 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1062 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
961 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1063 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
962 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 1064 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
963 <&zs_clk>; 1065 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1066 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
964 #clock-cells = <1>; 1067 #clock-cells = <1>;
965 renesas,clock-indices = < 1068 renesas,clock-indices = <
966 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 1069 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
967 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 1070 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
968 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 1071 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1072 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1073 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1074 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1075 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
969 >; 1076 >;
970 clock-output-names = 1077 clock-output-names =
971 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 1078 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
972 "vsp1-du0", "vsp1-rt", "vsp1-sy"; 1079 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1080 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
1081 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
973 }; 1082 };
974 mstp2_clks: mstp2_clks@e6150138 { 1083 mstp2_clks: mstp2_clks@e6150138 {
975 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1084 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -994,25 +1103,29 @@
994 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1103 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
995 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, 1104 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
996 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, 1105 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
997 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; 1106 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1107 <&hp_clk>, <&hp_clk>;
998 #clock-cells = <1>; 1108 #clock-cells = <1>;
999 renesas,clock-indices = < 1109 renesas,clock-indices = <
1000 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 1110 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1001 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 1111 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
1002 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 1112 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
1113 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
1003 >; 1114 >;
1004 clock-output-names = 1115 clock-output-names =
1005 "iic2", "tpu0", "mmcif1", "sdhi3", 1116 "iic2", "tpu0", "mmcif1", "sdhi3",
1006 "sdhi2", "sdhi1", "sdhi0", "mmcif0", 1117 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
1007 "iic0", "pciec", "iic1", "ssusb", "cmt1"; 1118 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1119 "usbdmac0", "usbdmac1";
1008 }; 1120 };
1009 mstp5_clks: mstp5_clks@e6150144 { 1121 mstp5_clks: mstp5_clks@e6150144 {
1010 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1011 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1012 clocks = <&extal_clk>, <&p_clk>; 1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1013 #clock-cells = <1>; 1125 #clock-cells = <1>;
1014 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; 1126 renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1015 clock-output-names = "thermal", "pwm"; 1127 R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1128 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1016 }; 1129 };
1017 mstp7_clks: mstp7_clks@e615014c { 1130 mstp7_clks: mstp7_clks@e615014c {
1018 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1131 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1160,6 +1273,16 @@
1160 status = "disabled"; 1273 status = "disabled";
1161 }; 1274 };
1162 1275
1276 xhci: usb@ee000000 {
1277 compatible = "renesas,xhci-r8a7790";
1278 reg = <0 0xee000000 0 0xc00>;
1279 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1281 phys = <&usb2 1>;
1282 phy-names = "usb";
1283 status = "disabled";
1284 };
1285
1163 pci0: pci@ee090000 { 1286 pci0: pci@ee090000 {
1164 compatible = "renesas,pci-r8a7790"; 1287 compatible = "renesas,pci-r8a7790";
1165 device_type = "pci"; 1288 device_type = "pci";
@@ -1178,6 +1301,20 @@
1178 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1301 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1179 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1302 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1180 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1303 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1304
1305 usb@0,1 {
1306 reg = <0x800 0 0 0 0>;
1307 device_type = "pci";
1308 phys = <&usb0 0>;
1309 phy-names = "usb";
1310 };
1311
1312 usb@0,2 {
1313 reg = <0x1000 0 0 0 0>;
1314 device_type = "pci";
1315 phys = <&usb0 0>;
1316 phy-names = "usb";
1317 };
1181 }; 1318 };
1182 1319
1183 pci1: pci@ee0b0000 { 1320 pci1: pci@ee0b0000 {
@@ -1218,6 +1355,20 @@
1218 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1355 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1219 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1356 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1220 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1357 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1358
1359 usb@0,1 {
1360 reg = <0x800 0 0 0 0>;
1361 device_type = "pci";
1362 phys = <&usb2 0>;
1363 phy-names = "usb";
1364 };
1365
1366 usb@0,2 {
1367 reg = <0x1000 0 0 0 0>;
1368 device_type = "pci";
1369 phys = <&usb2 0>;
1370 phy-names = "usb";
1371 };
1221 }; 1372 };
1222 1373
1223 pciec: pcie@fe000000 { 1374 pciec: pcie@fe000000 {
@@ -1245,7 +1396,7 @@
1245 status = "disabled"; 1396 status = "disabled";
1246 }; 1397 };
1247 1398
1248 rcar_sound: rcar_sound@0xec500000 { 1399 rcar_sound: rcar_sound@ec500000 {
1249 #sound-dai-cells = <1>; 1400 #sound-dai-cells = <1>;
1250 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1401 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1251 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1402 reg = <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index 0868899882e3..740e38678032 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -272,6 +272,17 @@
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273}; 273};
274 274
275&hsusb {
276 status = "okay";
277 pinctrl-0 = <&usb0_pins>;
278 pinctrl-names = "default";
279 renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
280};
281
282&usbphy {
283 status = "okay";
284};
285
275&pcie_bus_clk { 286&pcie_bus_clk {
276 status = "okay"; 287 status = "okay";
277}; 288};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 924183817b02..990af167c551 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -10,6 +10,34 @@
10 * kind, whether express or implied. 10 * kind, whether express or implied.
11 */ 11 */
12 12
13/*
14 * SSI-AK4643
15 *
16 * SW1: 1: AK4643
17 * 2: CN22
18 * 3: ADV7511
19 *
20 * This command is required when Playback/Capture
21 *
22 * amixer set "LINEOUT Mixer DACL" on
23 * amixer set "DVC Out" 100%
24 * amixer set "DVC In" 100%
25 *
26 * You can use Mute
27 *
28 * amixer set "DVC Out Mute" on
29 * amixer set "DVC In Mute" on
30 *
31 * You can use Volume Ramp
32 *
33 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
34 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
35 * amixer set "DVC Out Ramp" on
36 * aplay xxx.wav &
37 * amixer set "DVC Out" 80% // Volume Down
38 * amixer set "DVC Out" 100% // Volume Up
39 */
40
13/dts-v1/; 41/dts-v1/;
14#include "r8a7791.dtsi" 42#include "r8a7791.dtsi"
15#include <dt-bindings/gpio/gpio.h> 43#include <dt-bindings/gpio/gpio.h>
@@ -44,7 +72,7 @@
44 #size-cells = <1>; 72 #size-cells = <1>;
45 }; 73 };
46 74
47 gpio-keys { 75 keyboard {
48 compatible = "gpio-keys"; 76 compatible = "gpio-keys";
49 77
50 key-1 { 78 key-1 {
@@ -130,12 +158,15 @@
130 compatible = "gpio-leds"; 158 compatible = "gpio-leds";
131 led6 { 159 led6 {
132 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; 160 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
161 label = "LED6";
133 }; 162 };
134 led7 { 163 led7 {
135 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 164 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
165 label = "LED7";
136 }; 166 };
137 led8 { 167 led8 {
138 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; 168 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
169 label = "LED8";
139 }; 170 };
140 }; 171 };
141 172
@@ -210,6 +241,23 @@
210 states = <3300000 1 241 states = <3300000 1
211 1800000 0>; 242 1800000 0>;
212 }; 243 };
244
245 sound {
246 compatible = "simple-audio-card";
247
248 simple-audio-card,format = "left_j";
249 simple-audio-card,bitclock-master = <&sndcodec>;
250 simple-audio-card,frame-master = <&sndcodec>;
251
252 sndcpu: simple-audio-card,cpu {
253 sound-dai = <&rcar_sound>;
254 };
255
256 sndcodec: simple-audio-card,codec {
257 sound-dai = <&ak4643>;
258 system-clock-frequency = <11289600>;
259 };
260 };
213}; 261};
214 262
215&du { 263&du {
@@ -300,6 +348,16 @@
300 renesas,groups = "vin1_data8", "vin1_clk"; 348 renesas,groups = "vin1_data8", "vin1_clk";
301 renesas,function = "vin1"; 349 renesas,function = "vin1";
302 }; 350 };
351
352 sound_pins: sound {
353 renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
354 renesas,function = "ssi";
355 };
356
357 sound_clk_pins: sound_clk {
358 renesas,groups = "audio_clk_a";
359 renesas,function = "audio_clk";
360 };
303}; 361};
304 362
305&ether { 363&ether {
@@ -425,7 +483,13 @@
425 pinctrl-names = "default"; 483 pinctrl-names = "default";
426 484
427 status = "okay"; 485 status = "okay";
428 clock-frequency = <400000>; 486 clock-frequency = <100000>;
487
488 ak4643: sound-codec@12 {
489 compatible = "asahi-kasei,ak4643";
490 #sound-dai-cells = <0>;
491 reg = <0x12>;
492 };
429 493
430 composite-in@20 { 494 composite-in@20 {
431 compatible = "adi,adv7180"; 495 compatible = "adi,adv7180";
@@ -474,6 +538,17 @@
474 pinctrl-names = "default"; 538 pinctrl-names = "default";
475}; 539};
476 540
541&hsusb {
542 status = "okay";
543 pinctrl-0 = <&usb0_pins>;
544 pinctrl-names = "default";
545 renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>;
546};
547
548&usbphy {
549 status = "okay";
550};
551
477&pcie_bus_clk { 552&pcie_bus_clk {
478 status = "okay"; 553 status = "okay";
479}; 554};
@@ -502,3 +577,23 @@
502 }; 577 };
503 }; 578 };
504}; 579};
580
581&rcar_sound {
582 pinctrl-0 = <&sound_pins &sound_clk_pins>;
583 pinctrl-names = "default";
584
585 #sound-dai-cells = <0>;
586
587 status = "okay";
588
589 rcar_sound,dai {
590 dai0 {
591 playback = <&ssi0 &src2 &dvc0>;
592 capture = <&ssi1 &src3 &dvc1>;
593 };
594 };
595};
596
597&ssi1 {
598 shared-pin;
599};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e4a7170f368b..77c0beeb8d7c 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for the r8a7791 SoC 2 * Device Tree Source for the r8a7791 SoC
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc. 6 * Copyright (C) 2014 Cogent Embedded Inc.
7 * 7 *
@@ -301,6 +301,69 @@
301 dma-channels = <15>; 301 dma-channels = <15>;
302 }; 302 };
303 303
304 audma0: dma-controller@ec700000 {
305 compatible = "renesas,rcar-dmac";
306 reg = <0 0xec700000 0 0x10000>;
307 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
308 0 320 IRQ_TYPE_LEVEL_HIGH
309 0 321 IRQ_TYPE_LEVEL_HIGH
310 0 322 IRQ_TYPE_LEVEL_HIGH
311 0 323 IRQ_TYPE_LEVEL_HIGH
312 0 324 IRQ_TYPE_LEVEL_HIGH
313 0 325 IRQ_TYPE_LEVEL_HIGH
314 0 326 IRQ_TYPE_LEVEL_HIGH
315 0 327 IRQ_TYPE_LEVEL_HIGH
316 0 328 IRQ_TYPE_LEVEL_HIGH
317 0 329 IRQ_TYPE_LEVEL_HIGH
318 0 330 IRQ_TYPE_LEVEL_HIGH
319 0 331 IRQ_TYPE_LEVEL_HIGH
320 0 332 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12";
326 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
327 clock-names = "fck";
328 #dma-cells = <1>;
329 dma-channels = <13>;
330 };
331
332 audma1: dma-controller@ec720000 {
333 compatible = "renesas,rcar-dmac";
334 reg = <0 0xec720000 0 0x10000>;
335 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
336 0 333 IRQ_TYPE_LEVEL_HIGH
337 0 334 IRQ_TYPE_LEVEL_HIGH
338 0 335 IRQ_TYPE_LEVEL_HIGH
339 0 336 IRQ_TYPE_LEVEL_HIGH
340 0 337 IRQ_TYPE_LEVEL_HIGH
341 0 338 IRQ_TYPE_LEVEL_HIGH
342 0 339 IRQ_TYPE_LEVEL_HIGH
343 0 340 IRQ_TYPE_LEVEL_HIGH
344 0 341 IRQ_TYPE_LEVEL_HIGH
345 0 342 IRQ_TYPE_LEVEL_HIGH
346 0 343 IRQ_TYPE_LEVEL_HIGH
347 0 344 IRQ_TYPE_LEVEL_HIGH
348 0 345 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12";
354 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
355 clock-names = "fck";
356 #dma-cells = <1>;
357 dma-channels = <13>;
358 };
359
360 audmapp: dma-controller@ec740000 {
361 compatible = "renesas,rcar-audmapp";
362 #dma-cells = <1>;
363
364 reg = <0 0xec740000 0 0x200>;
365 };
366
304 /* The memory map in the User's Manual maps the cores to bus numbers */ 367 /* The memory map in the User's Manual maps the cores to bus numbers */
305 i2c0: i2c@e6508000 { 368 i2c0: i2c@e6508000 {
306 #address-cells = <1>; 369 #address-cells = <1>;
@@ -371,6 +434,8 @@
371 reg = <0 0xe60b0000 0 0x425>; 434 reg = <0 0xe60b0000 0 0x425>;
372 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 435 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; 436 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
437 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
438 dma-names = "tx", "rx";
374 status = "disabled"; 439 status = "disabled";
375 }; 440 };
376 441
@@ -381,6 +446,8 @@
381 reg = <0 0xe6500000 0 0x425>; 446 reg = <0 0xe6500000 0 0x425>;
382 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 447 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp3_clks R8A7791_CLK_IIC0>; 448 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
449 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
450 dma-names = "tx", "rx";
384 status = "disabled"; 451 status = "disabled";
385 }; 452 };
386 453
@@ -391,6 +458,8 @@
391 reg = <0 0xe6510000 0 0x425>; 458 reg = <0 0xe6510000 0 0x425>;
392 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 459 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&mstp3_clks R8A7791_CLK_IIC1>; 460 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
461 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
462 dma-names = "tx", "rx";
394 status = "disabled"; 463 status = "disabled";
395 }; 464 };
396 465
@@ -400,6 +469,17 @@
400 #gpio-range-cells = <3>; 469 #gpio-range-cells = <3>;
401 }; 470 };
402 471
472 mmcif0: mmc@ee200000 {
473 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
474 reg = <0 0xee200000 0 0x80>;
475 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
477 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
478 dma-names = "tx", "rx";
479 reg-io-width = <4>;
480 status = "disabled";
481 };
482
403 sdhi0: sd@ee100000 { 483 sdhi0: sd@ee100000 {
404 compatible = "renesas,sdhi-r8a7791"; 484 compatible = "renesas,sdhi-r8a7791";
405 reg = <0 0xee100000 0 0x200>; 485 reg = <0 0xee100000 0 0x200>;
@@ -613,6 +693,36 @@
613 status = "disabled"; 693 status = "disabled";
614 }; 694 };
615 695
696 hsusb: usb@e6590000 {
697 compatible = "renesas,usbhs-r8a7791";
698 reg = <0 0xe6590000 0 0x100>;
699 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
701 renesas,buswait = <4>;
702 phys = <&usb0 1>;
703 phy-names = "usb";
704 status = "disabled";
705 };
706
707 usbphy: usb-phy@e6590100 {
708 compatible = "renesas,usb-phy-r8a7791";
709 reg = <0 0xe6590100 0 0x100>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
713 clock-names = "usbhs";
714 status = "disabled";
715
716 usb0: usb-channel@0 {
717 reg = <0>;
718 #phy-cells = <1>;
719 };
720 usb2: usb-channel@2 {
721 reg = <2>;
722 #phy-cells = <1>;
723 };
724 };
725
616 vin0: video@e6ef0000 { 726 vin0: video@e6ef0000 {
617 compatible = "renesas,vin-r8a7791"; 727 compatible = "renesas,vin-r8a7791";
618 clocks = <&mstp8_clks R8A7791_CLK_VIN0>; 728 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
@@ -958,17 +1068,23 @@
958 mstp1_clks: mstp1_clks@e6150134 { 1068 mstp1_clks: mstp1_clks@e6150134 {
959 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1069 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
960 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1070 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
961 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 1071 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
962 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 1072 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1073 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1074 <&zs_clk>;
963 #clock-cells = <1>; 1075 #clock-cells = <1>;
964 renesas,clock-indices = < 1076 renesas,clock-indices = <
965 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 1077 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
966 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 1078 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
967 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S 1079 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1080 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1081 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1082 R8A7791_CLK_VSP1_S
968 >; 1083 >;
969 clock-output-names = 1084 clock-output-names =
970 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 1085 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
971 "vsp1-du0", "vsp1-sy"; 1086 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1087 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
972 }; 1088 };
973 mstp2_clks: mstp2_clks@e6150138 { 1089 mstp2_clks: mstp2_clks@e6150138 {
974 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1090 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -992,24 +1108,28 @@
992 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1108 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
993 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1109 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
994 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1110 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
995 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; 1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>;
996 #clock-cells = <1>; 1113 #clock-cells = <1>;
997 renesas,clock-indices = < 1114 renesas,clock-indices = <
998 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1115 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
999 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1116 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1000 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1117 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1118 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
1001 >; 1119 >;
1002 clock-output-names = 1120 clock-output-names =
1003 "tpu0", "sdhi2", "sdhi1", "sdhi0", 1121 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1004 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; 1122 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1123 "usbdmac0", "usbdmac1";
1005 }; 1124 };
1006 mstp5_clks: mstp5_clks@e6150144 { 1125 mstp5_clks: mstp5_clks@e6150144 {
1007 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1126 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1008 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1009 clocks = <&extal_clk>, <&p_clk>; 1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1010 #clock-cells = <1>; 1129 #clock-cells = <1>;
1011 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; 1130 renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1012 clock-output-names = "thermal", "pwm"; 1131 R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
1132 clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1013 }; 1133 };
1014 mstp7_clks: mstp7_clks@e615014c { 1134 mstp7_clks: mstp7_clks@e615014c {
1015 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1135 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1157,6 +1277,16 @@
1157 status = "disabled"; 1277 status = "disabled";
1158 }; 1278 };
1159 1279
1280 xhci: usb@ee000000 {
1281 compatible = "renesas,xhci-r8a7791";
1282 reg = <0 0xee000000 0 0xc00>;
1283 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1284 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1285 phys = <&usb2 1>;
1286 phy-names = "usb";
1287 status = "disabled";
1288 };
1289
1160 pci0: pci@ee090000 { 1290 pci0: pci@ee090000 {
1161 compatible = "renesas,pci-r8a7791"; 1291 compatible = "renesas,pci-r8a7791";
1162 device_type = "pci"; 1292 device_type = "pci";
@@ -1175,6 +1305,20 @@
1175 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1305 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1176 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1306 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1177 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1307 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1308
1309 usb@0,1 {
1310 reg = <0x800 0 0 0 0>;
1311 device_type = "pci";
1312 phys = <&usb0 0>;
1313 phy-names = "usb";
1314 };
1315
1316 usb@0,2 {
1317 reg = <0x1000 0 0 0 0>;
1318 device_type = "pci";
1319 phys = <&usb0 0>;
1320 phy-names = "usb";
1321 };
1178 }; 1322 };
1179 1323
1180 pci1: pci@ee0d0000 { 1324 pci1: pci@ee0d0000 {
@@ -1195,6 +1339,20 @@
1195 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1339 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1196 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1340 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1197 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1341 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1342
1343 usb@0,1 {
1344 reg = <0x800 0 0 0 0>;
1345 device_type = "pci";
1346 phys = <&usb2 0>;
1347 phy-names = "usb";
1348 };
1349
1350 usb@0,2 {
1351 reg = <0x1000 0 0 0 0>;
1352 device_type = "pci";
1353 phys = <&usb2 0>;
1354 phy-names = "usb";
1355 };
1198 }; 1356 };
1199 1357
1200 pciec: pcie@fe000000 { 1358 pciec: pcie@fe000000 {
@@ -1222,7 +1380,7 @@
1222 status = "disabled"; 1380 status = "disabled";
1223 }; 1381 };
1224 1382
1225 rcar_sound: rcar_sound@0xec500000 { 1383 rcar_sound: rcar_sound@ec500000 {
1226 #sound-dai-cells = <1>; 1384 #sound-dai-cells = <1>;
1227 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; 1385 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1228 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1386 reg = <0 0xec500000 0 0x1000>, /* SCU */
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8aec51268b7d..f2cf7576bf3f 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -20,7 +20,7 @@
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; 23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 stdout-path = &scif2; 24 stdout-path = &scif2;
25 }; 25 };
26 26
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index d4e8bce1e0b7..19c9de3f2a5a 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -82,6 +82,14 @@
82 status = "disabled"; 82 status = "disabled";
83 }; 83 };
84 84
85 timer {
86 compatible = "arm,armv7-timer";
87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
88 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
89 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
91 };
92
85 irqc0: interrupt-controller@e61c0000 { 93 irqc0: interrupt-controller@e61c0000 {
86 compatible = "renesas,irqc-r8a7794", "renesas,irqc"; 94 compatible = "renesas,irqc-r8a7794", "renesas,irqc";
87 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
@@ -453,16 +461,19 @@
453 mstp1_clks: mstp1_clks@e6150134 { 461 mstp1_clks: mstp1_clks@e6150134 {
454 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 462 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
455 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 463 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
456 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 464 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
457 <&cp_clk>, 465 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
458 <&zs_clk>, <&zs_clk>, <&zs_clk>; 466 <&zs_clk>, <&zs_clk>;
459 #clock-cells = <1>; 467 #clock-cells = <1>;
460 renesas,clock-indices = < 468 renesas,clock-indices = <
461 R8A7794_CLK_TMU1 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 469 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
462 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0 470 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
471 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
472 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
463 >; 473 >;
464 clock-output-names = 474 clock-output-names =
465 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0"; 475 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
476 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
466 }; 477 };
467 mstp2_clks: mstp2_clks@e6150138 { 478 mstp2_clks: mstp2_clks@e6150138 {
468 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 479 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -509,13 +520,13 @@
509 mstp8_clks: mstp8_clks@e6150990 { 520 mstp8_clks: mstp8_clks@e6150990 {
510 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
511 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 522 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
512 clocks = <&p_clk>; 523 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>;
513 #clock-cells = <1>; 524 #clock-cells = <1>;
514 renesas,clock-indices = < 525 renesas,clock-indices = <
515 R8A7794_CLK_ETHER 526 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER
516 >; 527 >;
517 clock-output-names = 528 clock-output-names =
518 "ether"; 529 "vin1", "vin0", "ether";
519 }; 530 };
520 mstp11_clks: mstp11_clks@e615099c { 531 mstp11_clks: mstp11_clks@e615099c {
521 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 532 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index d5344510c676..baf21ac6ce7f 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -60,6 +60,10 @@
60 }; 60 };
61}; 61};
62 62
63&cpu0 {
64 cpu0-supply = <&vdd_arm>;
65};
66
63&i2c1 { 67&i2c1 {
64 status = "okay"; 68 status = "okay";
65 clock-frequency = <400000>; 69 clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts
new file mode 100644
index 000000000000..0a7304beb417
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-marsboard.dts
@@ -0,0 +1,206 @@
1/*
2 * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3066a.dtsi"
45
46/ {
47 model = "MarsBoard RK3066";
48 compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
49
50 memory {
51 reg = <0x60000000 0x40000000>;
52 };
53
54 vcc_sd0: sdmmc-regulator {
55 compatible = "regulator-fixed";
56 regulator-name = "sdmmc-supply";
57 regulator-min-microvolt = <3000000>;
58 regulator-max-microvolt = <3000000>;
59 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
60 startup-delay-us = <100000>;
61 vin-supply = <&vcc_io>;
62 };
63
64 vsys: vsys-regulator {
65 compatible = "regulator-fixed";
66 regulator-name = "vsys";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 regulator-boot-on;
70 };
71};
72
73&i2c1 {
74 status = "okay";
75 clock-frequency = <400000>;
76
77 tps: tps@2d {
78 reg = <0x2d>;
79
80 interrupt-parent = <&gpio6>;
81 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
82
83 vcc1-supply = <&vsys>;
84 vcc2-supply = <&vsys>;
85 vcc3-supply = <&vsys>;
86 vcc4-supply = <&vsys>;
87 vcc5-supply = <&vcc_io>;
88 vcc6-supply = <&vcc_io>;
89 vcc7-supply = <&vsys>;
90 vccio-supply = <&vsys>;
91
92 regulators {
93 vcc_rtc: regulator@0 {
94 regulator-name = "vcc_rtc";
95 regulator-always-on;
96 };
97
98 vcc_io: regulator@1 {
99 regulator-name = "vcc_io";
100 regulator-always-on;
101 };
102
103 vdd_arm: regulator@2 {
104 regulator-name = "vdd_arm";
105 regulator-min-microvolt = <600000>;
106 regulator-max-microvolt = <1500000>;
107 regulator-boot-on;
108 regulator-always-on;
109 };
110
111 vcc_ddr: regulator@3 {
112 regulator-name = "vcc_ddr";
113 regulator-min-microvolt = <600000>;
114 regulator-max-microvolt = <1500000>;
115 regulator-boot-on;
116 regulator-always-on;
117 };
118
119 vcc18_cif: regulator@5 {
120 regulator-name = "vcc18_cif";
121 regulator-always-on;
122 };
123
124 vdd_11: regulator@6 {
125 regulator-name = "vdd_11";
126 regulator-always-on;
127 };
128
129 vcc_25: regulator@7 {
130 regulator-name = "vcc_25";
131 regulator-always-on;
132 };
133
134 vcc_18: regulator@8 {
135 regulator-name = "vcc_18";
136 regulator-always-on;
137 };
138
139 vcc25_hdmi: regulator@9 {
140 regulator-name = "vcc25_hdmi";
141 regulator-always-on;
142 };
143
144 vcca_33: regulator@10 {
145 regulator-name = "vcca_33";
146 regulator-always-on;
147 };
148
149 vcc_rmii: regulator@11 {
150 regulator-name = "vcc_rmii";
151 };
152
153 vcc28_cif: regulator@12 {
154 regulator-name = "vcc28_cif";
155 regulator-always-on;
156 };
157 };
158 };
159};
160
161/* must be included after &tps gets defined */
162#include "tps65910.dtsi"
163
164&emac {
165 status = "okay";
166
167 phy = <&phy0>;
168 phy-supply = <&vcc_rmii>;
169
170 pinctrl-names = "default";
171 pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
172
173 phy0: ethernet-phy@0 {
174 reg = <0>;
175 interrupt-parent = <&gpio1>;
176 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
177 };
178};
179
180&pinctrl {
181 lan8720a {
182 phy_int: phy-int {
183 rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>;
184 };
185 };
186};
187
188&uart0 {
189 status = "okay";
190};
191
192&uart1 {
193 status = "okay";
194};
195
196&uart2 {
197 status = "okay";
198};
199
200&uart3 {
201 status = "okay";
202};
203
204&wdt {
205 status = "okay";
206};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index ad9c2db59670..41ffd4951ef3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -26,11 +26,21 @@
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp"; 27 enable-method = "rockchip,rk3066-smp";
28 28
29 cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 reg = <0x0>; 33 reg = <0x0>;
34 operating-points = <
35 /* kHz uV */
36 1008000 1075000
37 816000 1025000
38 600000 1025000
39 504000 1000000
40 312000 975000
41 >;
42 clock-latency = <40000>;
43 clocks = <&cru ARMCLK>;
34 }; 44 };
35 cpu@1 { 45 cpu@1 {
36 device_type = "cpu"; 46 device_type = "cpu";
@@ -53,6 +63,51 @@
53 }; 63 };
54 }; 64 };
55 65
66 i2s0: i2s@10118000 {
67 compatible = "rockchip,rk3066-i2s";
68 reg = <0x10118000 0x2000>;
69 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
70 #address-cells = <1>;
71 #size-cells = <0>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&i2s0_bus>;
74 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
75 dma-names = "tx", "rx";
76 clock-names = "i2s_hclk", "i2s_clk";
77 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
78 status = "disabled";
79 };
80
81 i2s1: i2s@1011a000 {
82 compatible = "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s1_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
93 status = "disabled";
94 };
95
96 i2s2: i2s@1011c000 {
97 compatible = "rockchip,rk3066-i2s";
98 reg = <0x1011c000 0x2000>;
99 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
100 #address-cells = <1>;
101 #size-cells = <0>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2s2_bus>;
104 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
105 dma-names = "tx", "rx";
106 clock-names = "i2s_hclk", "i2s_clk";
107 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
108 status = "disabled";
109 };
110
56 cru: clock-controller@20000000 { 111 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru"; 112 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>; 113 reg = <0x20000000 0x1000>;
@@ -179,6 +234,24 @@
179 bias-disable; 234 bias-disable;
180 }; 235 };
181 236
237 emac {
238 emac_xfer: emac-xfer {
239 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
240 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
241 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
242 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
243 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
244 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
245 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
246 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
247 };
248
249 emac_mdio: emac-mdio {
250 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
251 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
252 };
253 };
254
182 emmc { 255 emmc {
183 emmc_clk: emmc-clk { 256 emmc_clk: emmc-clk {
184 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>; 257 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
@@ -405,6 +478,42 @@
405 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; 478 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
406 }; 479 };
407 }; 480 };
481
482 i2s0 {
483 i2s0_bus: i2s0-bus {
484 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
485 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
486 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
487 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
488 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
489 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
490 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
491 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
492 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
493 };
494 };
495
496 i2s1 {
497 i2s1_bus: i2s1-bus {
498 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
499 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
500 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
501 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
502 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
503 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
504 };
505 };
506
507 i2s2 {
508 i2s2_bus: i2s2-bus {
509 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
510 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
511 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
512 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
513 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
514 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
515 };
516 };
408 }; 517 };
409}; 518};
410 519
@@ -496,3 +605,7 @@
496&wdt { 605&wdt {
497 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; 606 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
498}; 607};
608
609&emac {
610 compatible = "rockchip,rk3066-emac";
611};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 15910c9ddbc7..9a09579b8309 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -43,16 +43,19 @@
43 compatible = "gpio-leds"; 43 compatible = "gpio-leds";
44 44
45 green { 45 green {
46 label = "rock:green:user1";
46 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 47 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
47 default-state = "off"; 48 default-state = "off";
48 }; 49 };
49 50
50 yellow { 51 blue {
52 label = "rock:blue:user2";
51 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 53 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
52 default-state = "off"; 54 default-state = "off";
53 }; 55 };
54 56
55 sleep { 57 sleep {
58 label = "rock:red:power";
56 gpios = <&gpio0 15 0>; 59 gpios = <&gpio0 15 0>;
57 default-state = "off"; 60 default-state = "off";
58 }; 61 };
@@ -118,6 +121,10 @@
118 }; 121 };
119}; 122};
120 123
124&cpu0 {
125 cpu0-supply = <&vdd_arm>;
126};
127
121&i2c1 { 128&i2c1 {
122 status = "okay"; 129 status = "okay";
123 clock-frequency = <400000>; 130 clock-frequency = <400000>;
@@ -159,7 +166,7 @@
159 vdd_arm: REG3 { 166 vdd_arm: REG3 {
160 regulator-name = "VDD_ARM"; 167 regulator-name = "VDD_ARM";
161 regulator-min-microvolt = <875000>; 168 regulator-min-microvolt = <875000>;
162 regulator-max-microvolt = <1300000>; 169 regulator-max-microvolt = <1350000>;
163 regulator-always-on; 170 regulator-always-on;
164 }; 171 };
165 172
@@ -239,6 +246,18 @@
239 disable-wp; 246 disable-wp;
240}; 247};
241 248
249&pwm1 {
250 status = "okay";
251};
252
253&pwm2 {
254 status = "okay";
255};
256
257&pwm3 {
258 status = "okay";
259};
260
242&pinctrl { 261&pinctrl {
243 pcfg_output_low: pcfg-output-low { 262 pcfg_output_low: pcfg-output-low {
244 output-low; 263 output-low;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ddaada788b45..1d4d79c6688d 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -26,11 +26,24 @@
26 #size-cells = <0>; 26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp"; 27 enable-method = "rockchip,rk3066-smp";
28 28
29 cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>; 32 next-level-cache = <&L2>;
33 reg = <0x0>; 33 reg = <0x0>;
34 operating-points = <
35 /* kHz uV */
36 1608000 1350000
37 1416000 1250000
38 1200000 1150000
39 1008000 1075000
40 816000 975000
41 600000 950000
42 504000 925000
43 312000 875000
44 >;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
34 }; 47 };
35 cpu@1 { 48 cpu@1 {
36 device_type = "cpu"; 49 device_type = "cpu";
@@ -65,6 +78,21 @@
65 }; 78 };
66 }; 79 };
67 80
81 i2s0: i2s@1011a000 {
82 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
83 reg = <0x1011a000 0x2000>;
84 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2s0_bus>;
89 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
90 dma-names = "tx", "rx";
91 clock-names = "i2s_hclk", "i2s_clk";
92 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
93 status = "disabled";
94 };
95
68 cru: clock-controller@20000000 { 96 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru"; 97 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>; 98 reg = <0x20000000 0x1000>;
@@ -83,7 +111,7 @@
83 #size-cells = <1>; 111 #size-cells = <1>;
84 ranges; 112 ranges;
85 113
86 gpio0: gpio0@0x2000a000 { 114 gpio0: gpio0@2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0"; 115 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>; 116 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 117 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
@@ -96,7 +124,7 @@
96 #interrupt-cells = <2>; 124 #interrupt-cells = <2>;
97 }; 125 };
98 126
99 gpio1: gpio1@0x2003c000 { 127 gpio1: gpio1@2003c000 {
100 compatible = "rockchip,gpio-bank"; 128 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>; 129 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -395,6 +423,17 @@
395 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; 423 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
396 }; 424 };
397 }; 425 };
426
427 i2s0 {
428 i2s0_bus: i2s0-bus {
429 rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
430 <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
431 <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
432 <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
433 <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
434 <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
435 };
436 };
398 }; 437 };
399}; 438};
400 439
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
index ff522f8e3df4..d8c775e6d5fe 100644
--- a/arch/arm/boot/dts/rk3288-evb-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -17,6 +17,10 @@
17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; 17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
18}; 18};
19 19
20&cpu0 {
21 cpu0-supply = <&vdd_cpu>;
22};
23
20&i2c0 { 24&i2c0 {
21 clock-frequency = <400000>; 25 clock-frequency = <400000>;
22 status = "okay"; 26 status = "okay";
@@ -44,7 +48,7 @@
44 regulator-always-on; 48 regulator-always-on;
45 regulator-boot-on; 49 regulator-boot-on;
46 regulator-min-microvolt = <750000>; 50 regulator-min-microvolt = <750000>;
47 regulator-max-microvolt = <1300000>; 51 regulator-max-microvolt = <1350000>;
48 regulator-name = "vdd_arm"; 52 regulator-name = "vdd_arm";
49 }; 53 };
50 54
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
index cb83cea52fa1..3e067dd65d0c 100644
--- a/arch/arm/boot/dts/rk3288-evb.dtsi
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -148,6 +148,12 @@
148 status = "okay"; 148 status = "okay";
149}; 149};
150 150
151&tsadc {
152 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
153 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
154 status = "okay";
155};
156
151&pinctrl { 157&pinctrl {
152 backlight { 158 backlight {
153 bl_en: bl-en { 159 bl_en: bl-en {
diff --git a/arch/arm/boot/dts/rk3288-thermal.dtsi b/arch/arm/boot/dts/rk3288-thermal.dtsi
new file mode 100644
index 000000000000..2695200c0af7
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-thermal.dtsi
@@ -0,0 +1,74 @@
1/*
2 * Device Tree Source for RK3288 SoC thermal
3 *
4 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/thermal/thermal.h>
12
13reserve_thermal: reserve_thermal {
14 polling-delay-passive = <1000>; /* milliseconds */
15 polling-delay = <5000>; /* milliseconds */
16
17 thermal-sensors = <&tsadc 0>;
18};
19
20cpu_thermal: cpu_thermal {
21 polling-delay-passive = <1000>; /* milliseconds */
22 polling-delay = <5000>; /* milliseconds */
23
24 thermal-sensors = <&tsadc 1>;
25
26 trips {
27 cpu_alert0: cpu_alert0 {
28 temperature = <70000>; /* millicelsius */
29 hysteresis = <2000>; /* millicelsius */
30 type = "passive";
31 };
32 cpu_crit: cpu_crit {
33 temperature = <90000>; /* millicelsius */
34 hysteresis = <2000>; /* millicelsius */
35 type = "critical";
36 };
37 };
38
39 cooling-maps {
40 map0 {
41 trip = <&cpu_alert0>;
42 cooling-device =
43 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
44 };
45 };
46};
47
48gpu_thermal: gpu_thermal {
49 polling-delay-passive = <1000>; /* milliseconds */
50 polling-delay = <5000>; /* milliseconds */
51
52 thermal-sensors = <&tsadc 2>;
53
54 trips {
55 gpu_alert0: gpu_alert0 {
56 temperature = <70000>; /* millicelsius */
57 hysteresis = <2000>; /* millicelsius */
58 type = "passive";
59 };
60 gpu_crit: gpu_crit {
61 temperature = <90000>; /* millicelsius */
62 hysteresis = <2000>; /* millicelsius */
63 type = "critical";
64 };
65 };
66
67 cooling-maps {
68 map0 {
69 trip = <&gpu_alert0>;
70 cooling-device =
71 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
72 };
73 };
74};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..fd19f00784bd 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
15#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h> 16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h> 17#include <dt-bindings/clock/rk3288-cru.h>
18#include <dt-bindings/thermal/thermal.h>
18#include "skeleton.dtsi" 19#include "skeleton.dtsi"
19 20
20/ { 21/ {
@@ -46,26 +47,50 @@
46 cpus { 47 cpus {
47 #address-cells = <1>; 48 #address-cells = <1>;
48 #size-cells = <0>; 49 #size-cells = <0>;
50 enable-method = "rockchip,rk3066-smp";
51 rockchip,pmu = <&pmu>;
49 52
50 cpu@500 { 53 cpu0: cpu@500 {
51 device_type = "cpu"; 54 device_type = "cpu";
52 compatible = "arm,cortex-a12"; 55 compatible = "arm,cortex-a12";
53 reg = <0x500>; 56 reg = <0x500>;
57 resets = <&cru SRST_CORE0>;
58 operating-points = <
59 /* KHz uV */
60 1608000 1350000
61 1512000 1300000
62 1416000 1200000
63 1200000 1100000
64 1008000 1050000
65 816000 1000000
66 696000 950000
67 600000 900000
68 408000 900000
69 312000 900000
70 216000 900000
71 126000 900000
72 >;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
54 }; 76 };
55 cpu@501 { 77 cpu@501 {
56 device_type = "cpu"; 78 device_type = "cpu";
57 compatible = "arm,cortex-a12"; 79 compatible = "arm,cortex-a12";
58 reg = <0x501>; 80 reg = <0x501>;
81 resets = <&cru SRST_CORE1>;
59 }; 82 };
60 cpu@502 { 83 cpu@502 {
61 device_type = "cpu"; 84 device_type = "cpu";
62 compatible = "arm,cortex-a12"; 85 compatible = "arm,cortex-a12";
63 reg = <0x502>; 86 reg = <0x502>;
87 resets = <&cru SRST_CORE2>;
64 }; 88 };
65 cpu@503 { 89 cpu@503 {
66 device_type = "cpu"; 90 device_type = "cpu";
67 compatible = "arm,cortex-a12"; 91 compatible = "arm,cortex-a12";
68 reg = <0x503>; 92 reg = <0x503>;
93 resets = <&cru SRST_CORE3>;
69 }; 94 };
70 }; 95 };
71 96
@@ -116,6 +141,7 @@
116 141
117 timer { 142 timer {
118 compatible = "arm,armv7-timer"; 143 compatible = "arm,armv7-timer";
144 arm,cpu-registers-not-fw-configured;
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -177,6 +203,8 @@
177 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
178 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 204 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
179 clock-names = "spiclk", "apb_pclk"; 205 clock-names = "spiclk", "apb_pclk";
206 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
207 dma-names = "tx", "rx";
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default"; 209 pinctrl-names = "default";
182 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 210 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +218,8 @@
190 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 218 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
191 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 219 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
192 clock-names = "spiclk", "apb_pclk"; 220 clock-names = "spiclk", "apb_pclk";
221 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
222 dma-names = "tx", "rx";
193 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 223 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default"; 224 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 225 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +233,8 @@
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 233 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 234 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
205 clock-names = "spiclk", "apb_pclk"; 235 clock-names = "spiclk", "apb_pclk";
236 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
237 dma-names = "tx", "rx";
206 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default"; 239 pinctrl-names = "default";
208 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 240 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -329,6 +361,25 @@
329 status = "disabled"; 361 status = "disabled";
330 }; 362 };
331 363
364 thermal-zones {
365 #include "rk3288-thermal.dtsi"
366 };
367
368 tsadc: tsadc@ff280000 {
369 compatible = "rockchip,rk3288-tsadc";
370 reg = <0xff280000 0x100>;
371 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
373 clock-names = "tsadc", "apb_pclk";
374 resets = <&cru SRST_TSADC>;
375 reset-names = "tsadc-apb";
376 pinctrl-names = "default";
377 pinctrl-0 = <&otp_out>;
378 #thermal-sensor-cells = <1>;
379 rockchip,hw-tshut-temp = <95000>;
380 status = "disabled";
381 };
382
332 usb_host0_ehci: usb@ff500000 { 383 usb_host0_ehci: usb@ff500000 {
333 compatible = "generic-ehci"; 384 compatible = "generic-ehci";
334 reg = <0xff500000 0x100>; 385 reg = <0xff500000 0x100>;
@@ -439,6 +490,18 @@
439 status = "disabled"; 490 status = "disabled";
440 }; 491 };
441 492
493 bus_intmem@ff700000 {
494 compatible = "mmio-sram";
495 reg = <0xff700000 0x18000>;
496 #address-cells = <1>;
497 #size-cells = <1>;
498 ranges = <0 0xff700000 0x18000>;
499 smp-sram@0 {
500 compatible = "rockchip,rk3066-smp-sram";
501 reg = <0x00 0x10>;
502 };
503 };
504
442 pmu: power-management@ff730000 { 505 pmu: power-management@ff730000 {
443 compatible = "rockchip,rk3288-pmu", "syscon"; 506 compatible = "rockchip,rk3288-pmu", "syscon";
444 reg = <0xff730000 0x100>; 507 reg = <0xff730000 0x100>;
@@ -455,6 +518,16 @@
455 rockchip,grf = <&grf>; 518 rockchip,grf = <&grf>;
456 #clock-cells = <1>; 519 #clock-cells = <1>;
457 #reset-cells = <1>; 520 #reset-cells = <1>;
521 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
522 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
523 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
524 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
525 <&cru PCLK_PERI>;
526 assigned-clock-rates = <594000000>, <400000000>,
527 <500000000>, <300000000>,
528 <150000000>, <75000000>,
529 <300000000>, <150000000>,
530 <75000000>;
458 }; 531 };
459 532
460 grf: syscon@ff770000 { 533 grf: syscon@ff770000 {
@@ -484,6 +557,24 @@
484 status = "disabled"; 557 status = "disabled";
485 }; 558 };
486 559
560 vopb_mmu: iommu@ff930300 {
561 compatible = "rockchip,iommu";
562 reg = <0xff930300 0x100>;
563 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-names = "vopb_mmu";
565 #iommu-cells = <0>;
566 status = "disabled";
567 };
568
569 vopl_mmu: iommu@ff940300 {
570 compatible = "rockchip,iommu";
571 reg = <0xff940300 0x100>;
572 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "vopl_mmu";
574 #iommu-cells = <0>;
575 status = "disabled";
576 };
577
487 gic: interrupt-controller@ffc01000 { 578 gic: interrupt-controller@ffc01000 {
488 compatible = "arm,gic-400"; 579 compatible = "arm,gic-400";
489 interrupt-controller; 580 interrupt-controller;
@@ -948,6 +1039,12 @@
948 }; 1039 };
949 }; 1040 };
950 1041
1042 tsadc {
1043 otp_out: otp-out {
1044 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1045 };
1046 };
1047
951 pwm0 { 1048 pwm0 {
952 pwm0_pin: pwm0-pin { 1049 pwm0_pin: pwm0-pin {
953 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; 1050 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 499468d42ada..c54a9715dcfa 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -29,6 +29,10 @@
29 mshc0 = &emmc; 29 mshc0 = &emmc;
30 mshc1 = &mmc0; 30 mshc1 = &mmc0;
31 mshc2 = &mmc1; 31 mshc2 = &mmc1;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
32 spi0 = &spi0; 36 spi0 = &spi0;
33 spi1 = &spi1; 37 spi1 = &spi1;
34 }; 38 };
@@ -173,10 +177,9 @@
173 compatible = "rockchip,rk2928-dw-mshc"; 177 compatible = "rockchip,rk2928-dw-mshc";
174 reg = <0x10214000 0x1000>; 178 reg = <0x10214000 0x1000>;
175 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 179 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
176
177 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 180 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
178 clock-names = "biu", "ciu"; 181 clock-names = "biu", "ciu";
179 182 fifo-depth = <256>;
180 status = "disabled"; 183 status = "disabled";
181 }; 184 };
182 185
@@ -184,10 +187,9 @@
184 compatible = "rockchip,rk2928-dw-mshc"; 187 compatible = "rockchip,rk2928-dw-mshc";
185 reg = <0x10218000 0x1000>; 188 reg = <0x10218000 0x1000>;
186 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 189 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
187
188 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 190 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
189 clock-names = "biu", "ciu"; 191 clock-names = "biu", "ciu";
190 192 fifo-depth = <256>;
191 status = "disabled"; 193 status = "disabled";
192 }; 194 };
193 195
@@ -195,10 +197,9 @@
195 compatible = "rockchip,rk2928-dw-mshc"; 197 compatible = "rockchip,rk2928-dw-mshc";
196 reg = <0x1021c000 0x1000>; 198 reg = <0x1021c000 0x1000>;
197 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 199 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
198
199 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 200 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
200 clock-names = "biu", "ciu"; 201 clock-names = "biu", "ciu";
201 202 fifo-depth = <256>;
202 status = "disabled"; 203 status = "disabled";
203 }; 204 };
204 205
@@ -367,6 +368,8 @@
367 reg = <0x20070000 0x1000>; 368 reg = <0x20070000 0x1000>;
368 #address-cells = <1>; 369 #address-cells = <1>;
369 #size-cells = <0>; 370 #size-cells = <0>;
371 dmas = <&dmac2 10>, <&dmac2 11>;
372 dma-names = "tx", "rx";
370 status = "disabled"; 373 status = "disabled";
371 }; 374 };
372 375
@@ -378,6 +381,8 @@
378 reg = <0x20074000 0x1000>; 381 reg = <0x20074000 0x1000>;
379 #address-cells = <1>; 382 #address-cells = <1>;
380 #size-cells = <0>; 383 #size-cells = <0>;
384 dmas = <&dmac2 12>, <&dmac2 13>;
385 dma-names = "tx", "rx";
381 status = "disabled"; 386 status = "disabled";
382 }; 387 };
383}; 388};
diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts
index 57e00f9bce99..a25debb50401 100644
--- a/arch/arm/boot/dts/s3c6410-mini6410.dts
+++ b/arch/arm/boot/dts/s3c6410-mini6410.dts
@@ -198,10 +198,6 @@
198 status = "okay"; 198 status = "okay";
199}; 199};
200 200
201&pwm {
202 status = "okay";
203};
204
205&pinctrl0 { 201&pinctrl0 {
206 gpio_leds: gpio-leds { 202 gpio_leds: gpio-leds {
207 samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; 203 samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7";
diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi
index ff5bdaac987a..0ccb414cd268 100644
--- a/arch/arm/boot/dts/s3c64xx.dtsi
+++ b/arch/arm/boot/dts/s3c64xx.dtsi
@@ -172,7 +172,6 @@
172 clocks = <&clocks PCLK_PWM>; 172 clocks = <&clocks PCLK_PWM>;
173 samsung,pwm-outputs = <0>, <1>; 173 samsung,pwm-outputs = <0>, <1>;
174 #pwm-cells = <3>; 174 #pwm-cells = <3>;
175 status = "disabled";
176 }; 175 };
177 176
178 pinctrl0: pinctrl@7f008000 { 177 pinctrl0: pinctrl@7f008000 {
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 0dac0e66ccad..939be1299ca6 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -101,19 +101,23 @@
101 compatible = "gpio-leds"; 101 compatible = "gpio-leds";
102 led1 { 102 led1 {
103 gpios = <&pfc 20 GPIO_ACTIVE_LOW>; 103 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
104 label = "LED1";
104 }; 105 };
105 led2 { 106 led2 {
106 gpios = <&pfc 21 GPIO_ACTIVE_LOW>; 107 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
108 label = "LED2";
107 }; 109 };
108 led3 { 110 led3 {
109 gpios = <&pfc 22 GPIO_ACTIVE_LOW>; 111 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
112 label = "LED3";
110 }; 113 };
111 led4 { 114 led4 {
112 gpios = <&pfc 23 GPIO_ACTIVE_LOW>; 115 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
116 label = "LED4";
113 }; 117 };
114 }; 118 };
115 119
116 gpio-keys { 120 keyboard {
117 compatible = "gpio-keys"; 121 compatible = "gpio-keys";
118 122
119 back-key { 123 back-key {
@@ -251,7 +255,7 @@
251 }; 255 };
252 }; 256 };
253 257
254 ak4648: ak4648@0x12 { 258 ak4648: ak4648@12 {
255 #sound-dai-cells = <0>; 259 #sound-dai-cells = <0>;
256 compatible = "asahi-kasei,ak4648"; 260 compatible = "asahi-kasei,ak4648";
257 reg = <0x12>; 261 reg = <0x12>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 030a5920312f..d8def5a529da 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -138,7 +138,7 @@
138 i2c0: i2c@e6820000 { 138 i2c0: i2c@e6820000 {
139 #address-cells = <1>; 139 #address-cells = <1>;
140 #size-cells = <0>; 140 #size-cells = <0>;
141 compatible = "renesas,rmobile-iic"; 141 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
142 reg = <0xe6820000 0x425>; 142 reg = <0xe6820000 0x425>;
143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 143 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
144 0 168 IRQ_TYPE_LEVEL_HIGH 144 0 168 IRQ_TYPE_LEVEL_HIGH
@@ -150,7 +150,7 @@
150 i2c1: i2c@e6822000 { 150 i2c1: i2c@e6822000 {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <0>; 152 #size-cells = <0>;
153 compatible = "renesas,rmobile-iic"; 153 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
154 reg = <0xe6822000 0x425>; 154 reg = <0xe6822000 0x425>;
155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 155 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
156 0 52 IRQ_TYPE_LEVEL_HIGH 156 0 52 IRQ_TYPE_LEVEL_HIGH
@@ -162,7 +162,7 @@
162 i2c2: i2c@e6824000 { 162 i2c2: i2c@e6824000 {
163 #address-cells = <1>; 163 #address-cells = <1>;
164 #size-cells = <0>; 164 #size-cells = <0>;
165 compatible = "renesas,rmobile-iic"; 165 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
166 reg = <0xe6824000 0x425>; 166 reg = <0xe6824000 0x425>;
167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 167 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
168 0 172 IRQ_TYPE_LEVEL_HIGH 168 0 172 IRQ_TYPE_LEVEL_HIGH
@@ -174,7 +174,7 @@
174 i2c3: i2c@e6826000 { 174 i2c3: i2c@e6826000 {
175 #address-cells = <1>; 175 #address-cells = <1>;
176 #size-cells = <0>; 176 #size-cells = <0>;
177 compatible = "renesas,rmobile-iic"; 177 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
178 reg = <0xe6826000 0x425>; 178 reg = <0xe6826000 0x425>;
179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 179 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
180 0 184 IRQ_TYPE_LEVEL_HIGH 180 0 184 IRQ_TYPE_LEVEL_HIGH
@@ -186,7 +186,7 @@
186 i2c4: i2c@e6828000 { 186 i2c4: i2c@e6828000 {
187 #address-cells = <1>; 187 #address-cells = <1>;
188 #size-cells = <0>; 188 #size-cells = <0>;
189 compatible = "renesas,rmobile-iic"; 189 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
190 reg = <0xe6828000 0x425>; 190 reg = <0xe6828000 0x425>;
191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 191 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
192 0 188 IRQ_TYPE_LEVEL_HIGH 192 0 188 IRQ_TYPE_LEVEL_HIGH
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 4472fd92685c..252c3d1bda50 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -639,6 +639,33 @@
639 clock-names = "biu", "ciu"; 639 clock-names = "biu", "ciu";
640 }; 640 };
641 641
642 ocram: sram@ffff0000 {
643 compatible = "mmio-sram";
644 reg = <0xffff0000 0x10000>;
645 };
646
647 spi0: spi@fff00000 {
648 compatible = "snps,dw-apb-ssi";
649 #address-cells = <1>;
650 #size-cells = <0>;
651 reg = <0xfff00000 0x1000>;
652 interrupts = <0 154 4>;
653 num-cs = <4>;
654 clocks = <&spi_m_clk>;
655 status = "disabled";
656 };
657
658 spi1: spi@fff01000 {
659 compatible = "snps,dw-apb-ssi";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 reg = <0xfff01000 0x1000>;
663 interrupts = <0 156 4>;
664 num-cs = <4>;
665 clocks = <&spi_m_clk>;
666 status = "disabled";
667 };
668
642 /* Local timer */ 669 /* Local timer */
643 timer@fffec600 { 670 timer@fffec600 {
644 compatible = "arm,cortex-a9-twd-timer"; 671 compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
new file mode 100644
index 000000000000..8a05c47fd57f
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -0,0 +1,374 @@
1/*
2 * Copyright Altera Corporation (C) 2014. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include "skeleton.dtsi"
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19
20/ {
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 aliases {
25 ethernet0 = &gmac0;
26 ethernet1 = &gmac1;
27 ethernet2 = &gmac2;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 timer0 = &timer0;
31 timer1 = &timer1;
32 timer2 = &timer2;
33 timer3 = &timer3;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0>;
44 next-level-cache = <&L2>;
45 };
46 cpu@1 {
47 compatible = "arm,cortex-a9";
48 device_type = "cpu";
49 reg = <1>;
50 next-level-cache = <&L2>;
51 };
52 };
53
54 intc: intc@ffffd000 {
55 compatible = "arm,cortex-a9-gic";
56 #interrupt-cells = <3>;
57 interrupt-controller;
58 reg = <0xffffd000 0x1000>,
59 <0xffffc100 0x100>;
60 };
61
62 soc {
63 #address-cells = <1>;
64 #size-cells = <1>;
65 compatible = "simple-bus";
66 device_type = "soc";
67 interrupt-parent = <&intc>;
68 ranges;
69
70 amba {
71 compatible = "arm,amba-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 ranges;
75
76 pdma: pdma@ffda1000 {
77 compatible = "arm,pl330", "arm,primecell";
78 reg = <0xffda1000 0x1000>;
79 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
80 <0 84 IRQ_TYPE_LEVEL_HIGH>,
81 <0 85 IRQ_TYPE_LEVEL_HIGH>,
82 <0 86 IRQ_TYPE_LEVEL_HIGH>,
83 <0 87 IRQ_TYPE_LEVEL_HIGH>,
84 <0 88 IRQ_TYPE_LEVEL_HIGH>,
85 <0 89 IRQ_TYPE_LEVEL_HIGH>,
86 <0 90 IRQ_TYPE_LEVEL_HIGH>;
87 #dma-cells = <1>;
88 #dma-channels = <8>;
89 #dma-requests = <32>;
90 };
91 };
92
93 clkmgr@ffd04000 {
94 compatible = "altr,clk-mgr";
95 reg = <0xffd04000 0x1000>;
96
97 clocks {
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 osc1: osc1 {
102 #clock-cells = <0>;
103 compatible = "fixed-clock";
104 };
105
106 main_pll: main_pll {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 #clock-cells = <0>;
110 compatible = "altr,socfpga-pll-clock";
111 clocks = <&osc1>;
112 };
113
114 periph_pll: periph_pll {
115 #address-cells = <1>;
116 #size-cells = <0>;
117 #clock-cells = <0>;
118 compatible = "altr,socfpga-pll-clock";
119 clocks = <&osc1>;
120 };
121 };
122 };
123
124 gmac0: ethernet@ff800000 {
125 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
126 reg = <0xff800000 0x2000>;
127 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
128 interrupt-names = "macirq";
129 /* Filled in by bootloader */
130 mac-address = [00 00 00 00 00 00];
131 status = "disabled";
132 };
133
134 gmac1: ethernet@ff802000 {
135 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
136 reg = <0xff802000 0x2000>;
137 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
138 interrupt-names = "macirq";
139 /* Filled in by bootloader */
140 mac-address = [00 00 00 00 00 00];
141 status = "disabled";
142 };
143
144 gmac2: ethernet@ff804000 {
145 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
146 reg = <0xff804000 0x2000>;
147 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
148 interrupt-names = "macirq";
149 /* Filled in by bootloader */
150 mac-address = [00 00 00 00 00 00];
151 status = "disabled";
152 };
153
154 gpio0: gpio@ffc02900 {
155 #address-cells = <1>;
156 #size-cells = <0>;
157 compatible = "snps,dw-apb-gpio";
158 reg = <0xffc02900 0x100>;
159 status = "disabled";
160
161 porta: gpio-controller@0 {
162 compatible = "snps,dw-apb-gpio-port";
163 gpio-controller;
164 #gpio-cells = <2>;
165 snps,nr-gpios = <29>;
166 reg = <0>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
169 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
170 };
171 };
172
173 gpio1: gpio@ffc02a00 {
174 #address-cells = <1>;
175 #size-cells = <0>;
176 compatible = "snps,dw-apb-gpio";
177 reg = <0xffc02a00 0x100>;
178 status = "disabled";
179
180 portb: gpio-controller@0 {
181 compatible = "snps,dw-apb-gpio-port";
182 gpio-controller;
183 #gpio-cells = <2>;
184 snps,nr-gpios = <29>;
185 reg = <0>;
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
189 };
190 };
191
192 gpio2: gpio@ffc02b00 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "snps,dw-apb-gpio";
196 reg = <0xffc02b00 0x100>;
197 status = "disabled";
198
199 portc: gpio-controller@0 {
200 compatible = "snps,dw-apb-gpio-port";
201 gpio-controller;
202 #gpio-cells = <2>;
203 snps,nr-gpios = <27>;
204 reg = <0>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
207 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
208 };
209 };
210
211 i2c0: i2c@ffc02200 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "snps,designware-i2c";
215 reg = <0xffc02200 0x100>;
216 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
217 status = "disabled";
218 };
219
220 i2c1: i2c@ffc02300 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "snps,designware-i2c";
224 reg = <0xffc02300 0x100>;
225 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
226 status = "disabled";
227 };
228
229 i2c2: i2c@ffc02400 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "snps,designware-i2c";
233 reg = <0xffc02400 0x100>;
234 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
235 status = "disabled";
236 };
237
238 i2c3: i2c@ffc02500 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 compatible = "snps,designware-i2c";
242 reg = <0xffc02500 0x100>;
243 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
244 status = "disabled";
245 };
246
247 i2c4: i2c@ffc02600 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "snps,designware-i2c";
251 reg = <0xffc02600 0x100>;
252 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
253 status = "disabled";
254 };
255
256 L2: l2-cache@fffff000 {
257 compatible = "arm,pl310-cache";
258 reg = <0xfffff000 0x1000>;
259 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
260 cache-unified;
261 cache-level = <2>;
262 };
263
264 mmc: dwmmc0@ff808000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "altr,socfpga-dw-mshc";
268 reg = <0xff808000 0x1000>;
269 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
270 fifo-depth = <0x400>;
271 };
272
273 ocram: sram@ffe00000 {
274 compatible = "mmio-sram";
275 reg = <0xffe00000 0x40000>;
276 };
277
278 rst: rstmgr@ffd05000 {
279 #reset-cells = <1>;
280 compatible = "altr,rst-mgr";
281 reg = <0xffd05000 0x100>;
282 };
283
284 sysmgr: sysmgr@ffd06000 {
285 compatible = "altr,sys-mgr", "syscon";
286 reg = <0xffd06000 0x300>;
287 };
288
289 /* Local timer */
290 timer@ffffc600 {
291 compatible = "arm,cortex-a9-twd-timer";
292 reg = <0xffffc600 0x100>;
293 interrupts = <1 13 0xf04>;
294 };
295
296 timer0: timer0@ffc02700 {
297 compatible = "snps,dw-apb-timer";
298 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
299 reg = <0xffc02700 0x100>;
300 };
301
302 timer1: timer1@ffc02800 {
303 compatible = "snps,dw-apb-timer";
304 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
305 reg = <0xffc02800 0x100>;
306 };
307
308 timer2: timer2@ffd00000 {
309 compatible = "snps,dw-apb-timer";
310 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0xffd00000 0x100>;
312 };
313
314 timer3: timer3@ffd00100 {
315 compatible = "snps,dw-apb-timer";
316 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
317 reg = <0xffd01000 0x100>;
318 };
319
320 uart0: serial0@ffc02000 {
321 compatible = "snps,dw-apb-uart";
322 reg = <0xffc02000 0x100>;
323 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
324 reg-shift = <2>;
325 reg-io-width = <4>;
326 };
327
328 uart1: serial1@ffc02100 {
329 compatible = "snps,dw-apb-uart";
330 reg = <0xffc02100 0x100>;
331 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
332 reg-shift = <2>;
333 reg-io-width = <4>;
334 };
335
336 usbphy0: usbphy@0 {
337 #phy-cells = <0>;
338 compatible = "usb-nop-xceiv";
339 status = "okay";
340 };
341
342 usb0: usb@ffb00000 {
343 compatible = "snps,dwc2";
344 reg = <0xffb00000 0xffff>;
345 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
346 phys = <&usbphy0>;
347 phy-names = "usb2-phy";
348 status = "disabled";
349 };
350
351 usb1: usb@ffb40000 {
352 compatible = "snps,dwc2";
353 reg = <0xffb40000 0xffff>;
354 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
355 phys = <&usbphy0>;
356 phy-names = "usb2-phy";
357 status = "disabled";
358 };
359
360 watchdog0: watchdog@ffd00200 {
361 compatible = "snps,dw-wdt";
362 reg = <0xffd00200 0x100>;
363 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
364 status = "disabled";
365 };
366
367 watchdog1: watchdog@ffd00300 {
368 compatible = "snps,dw-wdt";
369 reg = <0xffd00300 0x100>;
370 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
371 status = "disabled";
372 };
373 };
374};
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
new file mode 100755
index 000000000000..3015ce8d3057
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2014 Altera Corporation <www.altera.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/dts-v1/;
19#include "socfpga_arria10.dtsi"
20
21/ {
22 model = "Altera SOCFPGA Arria 10";
23 compatible = "altr,socfpga-arria10", "altr,socfpga";
24
25 chosen {
26 bootargs = "console=ttyS0,115200 rootwait";
27 };
28
29 memory {
30 name = "memory";
31 device_type = "memory";
32 reg = <0x0 0x40000000>; /* 1GB */
33 };
34
35 soc {
36 clkmgr@ffd04000 {
37 clocks {
38 osc1 {
39 clock-frequency = <25000000>;
40 };
41 };
42 };
43
44 serial0@ffc02000 {
45 status = "okay";
46 };
47 };
48};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 28c05e7a31c9..06db951e06f8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -49,3 +49,7 @@
49 }; 49 };
50 }; 50 };
51}; 51};
52
53&watchdog0 {
54 status = "okay";
55};
diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
new file mode 100644
index 000000000000..a8c00ee7522a
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts
@@ -0,0 +1,151 @@
1/*
2 * Device Tree for the ST-Ericsson Nomadik S8815 board
3 * Produced by Calao Systems
4 */
5
6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/gpio/gpio.h>
9#include "ste-nomadik-stn8815.dtsi"
10
11/ {
12 model = "Nomadik STN8815NHK";
13 compatible = "st,nomadik-nhk-15";
14
15 chosen {
16 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
17 };
18
19 aliases {
20 stmpe-i2c0 = &stmpe0;
21 stmpe-i2c1 = &stmpe1;
22 };
23
24 pinctrl {
25 stmpe2401_1 {
26 stmpe2401_1_nhk_mode: stmpe2401_1_nhk {
27 nhk_cfg1 {
28 ste,pins = "GPIO76_B20"; // IRQ line
29 ste,input = <0>;
30 };
31 nhk_cfg2 {
32 ste,pins = "GPIO77_B8"; // reset line
33 ste,output = <1>;
34 };
35 };
36 };
37 stmpe2401_2 {
38 stmpe2401_2_nhk_mode: stmpe2401_2_nhk {
39 nhk_cfg1 {
40 ste,pins = "GPIO78_A8"; // IRQ line
41 ste,input = <0>;
42 };
43 nhk_cfg2 {
44 ste,pins = "GPIO79_C9"; // reset line
45 ste,output = <1>;
46 };
47 };
48 };
49 };
50
51 src@101e0000 {
52 /* These chrystal outputs are not used on this board */
53 disable-sxtalo;
54 disable-mxtalo;
55 };
56
57 /* This is where the interrupt is routed on the NHK-15 debug board */
58 external-bus@34000000 {
59 compatible = "simple-bus";
60 reg = <0x34000000 0x1000000>;
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges = <0 0x34000000 0x1000000>;
64 ethernet@300 {
65 compatible = "smsc,lan91c111";
66 reg = <0x300 0x0fd00>;
67 reg-io-width = <2>;
68 reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>;
69 interrupt-parent = <&stmpe_gpio44>;
70 interrupts = <11 IRQ_TYPE_EDGE_RISING>;
71 };
72 };
73
74 i2c0 {
75 stmpe0: stmpe2401@43 {
76 compatible = "st,stmpe2401";
77 reg = <0x43>;
78 reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77
79 interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76
80 interrupt-parent = <&gpio2>;
81 interrupt-controller;
82 wakeup-source;
83 pinctrl-names = "default";
84 pinctrl-0 = <&stmpe2401_1_nhk_mode>;
85 stmpe_gpio43: stmpe_gpio {
86 compatible = "st,stmpe-gpio";
87 gpio-controller;
88 #gpio-cells = <2>;
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 /* Some pins in alternate functions */
92 st,norequest-mask = <0xf0f002>;
93 };
94 stmpe_keypad {
95 compatible = "st,stmpe-keypad";
96 debounce-interval = <64>;
97 st,scan-count = <8>;
98 st,no-autorepeat;
99 keypad,num-rows = <8>;
100 keypad,num-columns = <8>;
101 linux,keymap = <0x00020072 // Vol down
102 0x00030073 // Vol up
103 0x0100009e // Back
104 0x010100e3 // TV out
105 0x01020098 // Lock
106 0x0103013b // Start
107 0x020000a3 // Next
108 0x020100a4 // Play
109 0x020200a5 // Prev
110 0x02030160 // OK
111 0x03000069 // Left
112 0x0301006a // Right
113 0x03020067 // Up
114 0x0303006c>; // Down
115 };
116 };
117 stmpe1: stmpe2401@44 {
118 compatible = "st,stmpe2401";
119 reg = <0x44>;
120 reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79
121 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78
122 interrupt-parent = <&gpio2>;
123 interrupt-controller;
124 wakeup-source;
125 pinctrl-names = "default";
126 pinctrl-0 = <&stmpe2401_2_nhk_mode>;
127 stmpe_gpio44: stmpe_gpio {
128 compatible = "st,stmpe-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134 };
135 };
136
137 amba {
138 mmcsd: sdi@101f6000 {
139 cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>;
140 wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>;
141 };
142 };
143
144 /* Custom board node with GPIO pins to active etc */
145 usb-s8815 {
146 /* This will turn off SATA so that MMC/SD can thrive */
147 mmcsd-gpio {
148 gpios = <&stmpe_gpio44 2 0x1>;
149 };
150 };
151};
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 90d8b6c7a205..e411ff7769fe 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -4,6 +4,7 @@
4 */ 4 */
5 5
6/dts-v1/; 6/dts-v1/;
7#include <dt-bindings/interrupt-controller/irq.h>
7#include "ste-nomadik-stn8815.dtsi" 8#include "ste-nomadik-stn8815.dtsi"
8 9
9/ { 10/ {
@@ -14,14 +15,6 @@
14 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; 15 bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
15 }; 16 };
16 17
17 /* This is where the interrupt is routed on the S8815 board */
18 external-bus@34000000 {
19 ethernet@300 {
20 interrupt-parent = <&gpio3>;
21 interrupts = <8 0x1>;
22 };
23 };
24
25 src@101e0000 { 18 src@101e0000 {
26 /* These chrystal drivers are not used on this board */ 19 /* These chrystal drivers are not used on this board */
27 disable-sxtalo; 20 disable-sxtalo;
@@ -47,6 +40,14 @@
47 }; 40 };
48 }; 41 };
49 }; 42 };
43 gpioi2c {
44 gpioi2c_default_mode: gpioi2c_default {
45 gpioi2c_default_cfg {
46 ste,pins = "GPIO73_C21", "GPIO74_C20";
47 ste,input = <0>;
48 };
49 };
50 };
50 user-led { 51 user-led {
51 user_led_default_mode: user_led_default { 52 user_led_default_mode: user_led_default {
52 user_led_default_cfg { 53 user_led_default_cfg {
@@ -65,6 +66,45 @@
65 }; 66 };
66 }; 67 };
67 68
69 /* Ethernet */
70 external-bus@34000000 {
71 compatible = "simple-bus";
72 reg = <0x34000000 0x1000000>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0 0x34000000 0x1000000>;
76 ethernet@300 {
77 compatible = "smsc,lan91c111";
78 reg = <0x300 0x0fd00>;
79 interrupt-parent = <&gpio3>;
80 interrupts = <8 IRQ_TYPE_EDGE_RISING>;
81 };
82 };
83
84 /* GPIO I2C connected to the USB portions of the STw4811 only */
85 gpio-i2c {
86 compatible = "i2c-gpio";
87 gpios = <&gpio2 10 0>, /* sda */
88 <&gpio2 9 0>; /* scl */
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&gpioi2c_default_mode>;
93
94 stw4811@2d {
95 compatible = "st,stw4811-usb";
96 reg = <0x2d>;
97 };
98 };
99
100
101 /* Configure card detect for the uSD slot */
102 amba {
103 mmcsd: sdi@101f6000 {
104 cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
105 };
106 };
107
68 /* Custom board node with GPIO pins to active etc */ 108 /* Custom board node with GPIO pins to active etc */
69 usb-s8815 { 109 usb-s8815 {
70 /* This will bias the MMC/SD card detect line */ 110 /* This will bias the MMC/SD card detect line */
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index dbcf521b017f..f435ff20aefe 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -117,7 +117,7 @@
117 mmcsd_default_mux: mmcsd_mux { 117 mmcsd_default_mux: mmcsd_mux {
118 mmcsd_default_mux { 118 mmcsd_default_mux {
119 ste,function = "mmcsd"; 119 ste,function = "mmcsd";
120 ste,pins = "mmcsd_a_1"; 120 ste,pins = "mmcsd_a_1", "mmcsd_b_1";
121 }; 121 };
122 }; 122 };
123 mmcsd_default_mode: mmcsd_default { 123 mmcsd_default_mode: mmcsd_default {
@@ -127,9 +127,9 @@
127 ste,output = <0>; 127 ste,output = <0>;
128 }; 128 };
129 mmcsd_default_cfg2 { 129 mmcsd_default_cfg2 {
130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ 130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */
131 ste,pins = "GPIO10_C11", "GPIO15_A12", 131 ste,pins = "GPIO10_C11", "GPIO15_A12",
132 "GPIO16_C13"; 132 "GPIO16_C13", "GPIO23_D15";
133 ste,output = <1>; 133 ste,output = <1>;
134 }; 134 };
135 mmcsd_default_cfg3 { 135 mmcsd_default_cfg3 {
@@ -169,21 +169,11 @@
169 }; 169 };
170 }; 170 };
171 }; 171 };
172 i2c2 {
173 i2c2_default_mode: i2c2_default {
174 i2c2_default_cfg {
175 ste,pins = "GPIO73_C21", "GPIO74_C20";
176 ste,input = <0>;
177 };
178 };
179 };
180 }; 172 };
181 173
182 src: src@101e0000 { 174 src: src@101e0000 {
183 compatible = "stericsson,nomadik-src"; 175 compatible = "stericsson,nomadik-src";
184 reg = <0x101e0000 0x1000>; 176 reg = <0x101e0000 0x1000>;
185 disable-sxtalo;
186 disable-mxtalo;
187 177
188 /* 178 /*
189 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz 179 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
@@ -683,18 +673,6 @@
683 }; 673 };
684 }; 674 };
685 675
686 external-bus@34000000 {
687 compatible = "simple-bus";
688 reg = <0x34000000 0x1000000>;
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x34000000 0x1000000>;
692 ethernet@300 {
693 compatible = "smsc,lan91c111";
694 reg = <0x300 0x0fd00>;
695 };
696 };
697
698 /* I2C0 connected to the STw4811 power management chip */ 676 /* I2C0 connected to the STw4811 power management chip */
699 i2c0 { 677 i2c0 {
700 compatible = "st,nomadik-i2c", "arm,primecell"; 678 compatible = "st,nomadik-i2c", "arm,primecell";
@@ -749,22 +727,6 @@
749 }; 727 };
750 }; 728 };
751 729
752 /* I2C2 connected to the USB portions of the STw4811 only */
753 i2c2 {
754 compatible = "i2c-gpio";
755 gpios = <&gpio2 10 0>, /* sda */
756 <&gpio2 9 0>; /* scl */
757 #address-cells = <1>;
758 #size-cells = <0>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&i2c2_default_mode>;
761
762 stw4811@2d {
763 compatible = "st,stw4811-usb";
764 reg = <0x2d>;
765 };
766 };
767
768 amba { 730 amba {
769 compatible = "arm,amba-bus"; 731 compatible = "arm,amba-bus";
770 #address-cells = <1>; 732 #address-cells = <1>;
@@ -844,7 +806,6 @@
844 bus-width = <4>; 806 bus-width = <4>;
845 cap-mmc-highspeed; 807 cap-mmc-highspeed;
846 cap-sd-highspeed; 808 cap-sd-highspeed;
847 cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
848 pinctrl-names = "default"; 809 pinctrl-names = "default";
849 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; 810 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
850 vmmc-supply = <&vmmc_regulator>; 811 vmmc-supply = <&vmmc_regulator>;
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92e5f82..261d5e2c48d2 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,13 +7,15 @@
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
8 */ 8 */
9/dts-v1/; 9/dts-v1/;
10#include "stih407.dtsi" 10#include "stih407-clock.dtsi"
11#include "stih407-family.dtsi"
12#include "stihxxx-b2120.dtsi"
11/ { 13/ {
12 model = "STiH407 B2120"; 14 model = "STiH407 B2120";
13 compatible = "st,stih407-b2120", "st,stih407"; 15 compatible = "st,stih407-b2120", "st,stih407";
14 16
15 chosen { 17 chosen {
16 bootargs = "console=ttyAS0,115200"; 18 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
17 linux,stdout-path = &sbc_serial0; 19 linux,stdout-path = &sbc_serial0;
18 }; 20 };
19 21
@@ -26,53 +28,4 @@
26 ttyAS0 = &sbc_serial0; 28 ttyAS0 = &sbc_serial0;
27 }; 29 };
28 30
29 soc {
30 sbc_serial0: serial@9530000 {
31 status = "okay";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 red {
37 #gpio-cells = <2>;
38 label = "Front Panel LED";
39 gpios = <&pio4 1 0>;
40 linux,default-trigger = "heartbeat";
41 };
42 green {
43 #gpio-cells = <2>;
44 gpios = <&pio1 3 0>;
45 default-state = "off";
46 };
47 };
48
49 i2c@9842000 {
50 status = "okay";
51 };
52
53 i2c@9843000 {
54 status = "okay";
55 };
56
57 i2c@9844000 {
58 status = "okay";
59 };
60
61 i2c@9845000 {
62 status = "okay";
63 };
64
65 i2c@9540000 {
66 status = "okay";
67 };
68
69 /* SSC11 to HDMI */
70 i2c@9541000 {
71 status = "okay";
72 /* HDMI V1.3a supports Standard mode only */
73 clock-frequency = <100000>;
74 st,i2c-min-scl-pulse-width-us = <0>;
75 st,i2c-min-sda-pulse-width-us = <5>;
76 };
77 };
78}; 31};
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 800f46f009f3..e65744fc12ab 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -5,8 +5,13 @@
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8#include <dt-bindings/clock/stih407-clks.h>
8/ { 9/ {
9 clocks { 10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
10 /* 15 /*
11 * Fixed 30MHz oscillator inputs to SoC 16 * Fixed 30MHz oscillator inputs to SoC
12 */ 17 */
@@ -19,10 +24,59 @@
19 /* 24 /*
20 * ARM Peripheral clock for timers 25 * ARM Peripheral clock for timers
21 */ 26 */
22 arm_periph_clk: arm-periph-clk { 27 arm_periph_clk: clk-m-a9-periphs {
23 #clock-cells = <0>; 28 #clock-cells = <0>;
24 compatible = "fixed-clock"; 29 compatible = "fixed-factor-clock";
25 clock-frequency = <600000000>; 30
31 clocks = <&clk_m_a9>;
32 clock-div = <2>;
33 clock-mult = <1>;
34 };
35
36 /*
37 * A9 PLL.
38 */
39 clockgen-a9@92b0000 {
40 compatible = "st,clkgen-c32";
41 reg = <0x92b0000 0xffff>;
42
43 clockgen_a9_pll: clockgen-a9-pll {
44 #clock-cells = <1>;
45 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
46
47 clocks = <&clk_sysin>;
48
49 clock-output-names = "clockgen-a9-pll-odf";
50 };
51 };
52
53 /*
54 * ARM CPU related clocks.
55 */
56 clk_m_a9: clk-m-a9@92b0000 {
57 #clock-cells = <0>;
58 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
59 reg = <0x92b0000 0x10000>;
60
61 clocks = <&clockgen_a9_pll 0>,
62 <&clockgen_a9_pll 0>,
63 <&clk_s_c0_flexgen 13>,
64 <&clk_m_a9_ext2f_div2>;
65 };
66
67 /*
68 * ARM Peripheral clock for timers
69 */
70 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73
74 clocks = <&clk_s_c0_flexgen 13>;
75
76 clock-output-names = "clk-m-a9-ext2f-div2";
77
78 clock-div = <2>;
79 clock-mult = <1>;
26 }; 80 };
27 81
28 /* 82 /*
@@ -35,5 +89,238 @@
35 clock-frequency = <200000000>; 89 clock-frequency = <200000000>;
36 clock-output-names = "clk-s-icn-reg-0"; 90 clock-output-names = "clk-s-icn-reg-0";
37 }; 91 };
92
93 clockgen-a@090ff000 {
94 compatible = "st,clkgen-c32";
95 reg = <0x90ff000 0x1000>;
96
97 clk_s_a0_pll: clk-s-a0-pll {
98 #clock-cells = <1>;
99 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
100
101 clocks = <&clk_sysin>;
102
103 clock-output-names = "clk-s-a0-pll-ofd-0";
104 };
105
106 clk_s_a0_flexgen: clk-s-a0-flexgen {
107 compatible = "st,flexgen";
108
109 #clock-cells = <1>;
110
111 clocks = <&clk_s_a0_pll 0>,
112 <&clk_sysin>;
113
114 clock-output-names = "clk-ic-lmi0";
115 };
116 };
117
118 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
119 #clock-cells = <1>;
120 compatible = "st,stih407-quadfs660-C", "st,quadfs";
121 reg = <0x9103000 0x1000>;
122
123 clocks = <&clk_sysin>;
124
125 clock-output-names = "clk-s-c0-fs0-ch0",
126 "clk-s-c0-fs0-ch1",
127 "clk-s-c0-fs0-ch2",
128 "clk-s-c0-fs0-ch3";
129 };
130
131 clk_s_c0: clockgen-c@09103000 {
132 compatible = "st,clkgen-c32";
133 reg = <0x9103000 0x1000>;
134
135 clk_s_c0_pll0: clk-s-c0-pll0 {
136 #clock-cells = <1>;
137 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
138
139 clocks = <&clk_sysin>;
140
141 clock-output-names = "clk-s-c0-pll0-odf-0";
142 };
143
144 clk_s_c0_pll1: clk-s-c0-pll1 {
145 #clock-cells = <1>;
146 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
147
148 clocks = <&clk_sysin>;
149
150 clock-output-names = "clk-s-c0-pll1-odf-0";
151 };
152
153 clk_s_c0_flexgen: clk-s-c0-flexgen {
154 #clock-cells = <1>;
155 compatible = "st,flexgen";
156
157 clocks = <&clk_s_c0_pll0 0>,
158 <&clk_s_c0_pll1 0>,
159 <&clk_s_c0_quadfs 0>,
160 <&clk_s_c0_quadfs 1>,
161 <&clk_s_c0_quadfs 2>,
162 <&clk_s_c0_quadfs 3>,
163 <&clk_sysin>;
164
165 clock-output-names = "clk-icn-gpu",
166 "clk-fdma",
167 "clk-nand",
168 "clk-hva",
169 "clk-proc-stfe",
170 "clk-proc-tp",
171 "clk-rx-icn-dmu",
172 "clk-rx-icn-hva",
173 "clk-icn-cpu",
174 "clk-tx-icn-dmu",
175 "clk-mmc-0",
176 "clk-mmc-1",
177 "clk-jpegdec",
178 "clk-ext2fa9",
179 "clk-ic-bdisp-0",
180 "clk-ic-bdisp-1",
181 "clk-pp-dmu",
182 "clk-vid-dmu",
183 "clk-dss-lpc",
184 "clk-st231-aud-0",
185 "clk-st231-gp-1",
186 "clk-st231-dmu",
187 "clk-icn-lmi",
188 "clk-tx-icn-disp-1",
189 "clk-icn-sbc",
190 "clk-stfe-frc2",
191 "clk-eth-phy",
192 "clk-eth-ref-phyclk",
193 "clk-flash-promip",
194 "clk-main-disp",
195 "clk-aux-disp",
196 "clk-compo-dvp";
197 };
198 };
199
200 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
201 #clock-cells = <1>;
202 compatible = "st,stih407-quadfs660-D", "st,quadfs";
203 reg = <0x9104000 0x1000>;
204
205 clocks = <&clk_sysin>;
206
207 clock-output-names = "clk-s-d0-fs0-ch0",
208 "clk-s-d0-fs0-ch1",
209 "clk-s-d0-fs0-ch2",
210 "clk-s-d0-fs0-ch3";
211 };
212
213 clockgen-d0@09104000 {
214 compatible = "st,clkgen-c32";
215 reg = <0x9104000 0x1000>;
216
217 clk_s_d0_flexgen: clk-s-d0-flexgen {
218 #clock-cells = <1>;
219 compatible = "st,flexgen";
220
221 clocks = <&clk_s_d0_quadfs 0>,
222 <&clk_s_d0_quadfs 1>,
223 <&clk_s_d0_quadfs 2>,
224 <&clk_s_d0_quadfs 3>,
225 <&clk_sysin>;
226
227 clock-output-names = "clk-pcm-0",
228 "clk-pcm-1",
229 "clk-pcm-2",
230 "clk-spdiff";
231 };
232 };
233
234 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
235 #clock-cells = <1>;
236 compatible = "st,stih407-quadfs660-D", "st,quadfs";
237 reg = <0x9106000 0x1000>;
238
239 clocks = <&clk_sysin>;
240
241 clock-output-names = "clk-s-d2-fs0-ch0",
242 "clk-s-d2-fs0-ch1",
243 "clk-s-d2-fs0-ch2",
244 "clk-s-d2-fs0-ch3";
245 };
246
247 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
248 #clock-cells = <0>;
249 compatible = "fixed-clock";
250 clock-frequency = <0>;
251 };
252
253 clockgen-d2@x9106000 {
254 compatible = "st,clkgen-c32";
255 reg = <0x9106000 0x1000>;
256
257 clk_s_d2_flexgen: clk-s-d2-flexgen {
258 #clock-cells = <1>;
259 compatible = "st,flexgen";
260
261 clocks = <&clk_s_d2_quadfs 0>,
262 <&clk_s_d2_quadfs 1>,
263 <&clk_s_d2_quadfs 2>,
264 <&clk_s_d2_quadfs 3>,
265 <&clk_sysin>,
266 <&clk_sysin>,
267 <&clk_tmdsout_hdmi>;
268
269 clock-output-names = "clk-pix-main-disp",
270 "clk-pix-pip",
271 "clk-pix-gdp1",
272 "clk-pix-gdp2",
273 "clk-pix-gdp3",
274 "clk-pix-gdp4",
275 "clk-pix-aux-disp",
276 "clk-denc",
277 "clk-pix-hddac",
278 "clk-hddac",
279 "clk-sddac",
280 "clk-pix-dvo",
281 "clk-dvo",
282 "clk-pix-hdmi",
283 "clk-tmds-hdmi",
284 "clk-ref-hdmiphy";
285 };
286 };
287
288 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
289 #clock-cells = <1>;
290 compatible = "st,stih407-quadfs660-D", "st,quadfs";
291 reg = <0x9107000 0x1000>;
292
293 clocks = <&clk_sysin>;
294
295 clock-output-names = "clk-s-d3-fs0-ch0",
296 "clk-s-d3-fs0-ch1",
297 "clk-s-d3-fs0-ch2",
298 "clk-s-d3-fs0-ch3";
299 };
300
301 clockgen-d3@9107000 {
302 compatible = "st,clkgen-c32";
303 reg = <0x9107000 0x1000>;
304
305 clk_s_d3_flexgen: clk-s-d3-flexgen {
306 #clock-cells = <1>;
307 compatible = "st,flexgen";
308
309 clocks = <&clk_s_d3_quadfs 0>,
310 <&clk_s_d3_quadfs 1>,
311 <&clk_s_d3_quadfs 2>,
312 <&clk_s_d3_quadfs 3>,
313 <&clk_sysin>;
314
315 clock-output-names = "clk-stfe-frc1",
316 "clk-tsout-0",
317 "clk-tsout-1",
318 "clk-mchi",
319 "clk-vsens-compo",
320 "clk-frc1-remote",
321 "clk-lpc-0",
322 "clk-lpc-1";
323 };
324 };
38 }; 325 };
39}; 326};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 4f9024f19866..3e31d32133b8 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -6,8 +6,8 @@
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation. 7 * publishhed by the Free Software Foundation.
8 */ 8 */
9#include "stih407-clock.dtsi"
10#include "stih407-pinctrl.dtsi" 9#include "stih407-pinctrl.dtsi"
10#include <dt-bindings/reset-controller/stih407-resets.h>
11/ { 11/ {
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
@@ -63,6 +63,21 @@
63 ranges; 63 ranges;
64 compatible = "simple-bus"; 64 compatible = "simple-bus";
65 65
66 powerdown: powerdown-controller {
67 compatible = "st,stih407-powerdown";
68 #reset-cells = <1>;
69 };
70
71 softreset: softreset-controller {
72 compatible = "st,stih407-softreset";
73 #reset-cells = <1>;
74 };
75
76 picophyreset: picophyreset-controller {
77 compatible = "st,stih407-picophyreset";
78 #reset-cells = <1>;
79 };
80
66 syscfg_sbc: sbc-syscfg@9620000 { 81 syscfg_sbc: sbc-syscfg@9620000 {
67 compatible = "st,stih407-sbc-syscfg", "syscon"; 82 compatible = "st,stih407-sbc-syscfg", "syscon";
68 reg = <0x9620000 0x1000>; 83 reg = <0x9620000 0x1000>;
@@ -104,7 +119,7 @@
104 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; 119 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
105 pinctrl-names = "default"; 120 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_serial0>; 121 pinctrl-0 = <&pinctrl_serial0>;
107 clocks = <&clk_ext2f_a9>; 122 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
108 123
109 status = "disabled"; 124 status = "disabled";
110 }; 125 };
@@ -115,7 +130,7 @@
115 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; 130 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
116 pinctrl-names = "default"; 131 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_serial1>; 132 pinctrl-0 = <&pinctrl_serial1>;
118 clocks = <&clk_ext2f_a9>; 133 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
119 134
120 status = "disabled"; 135 status = "disabled";
121 }; 136 };
@@ -126,7 +141,7 @@
126 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 141 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
127 pinctrl-names = "default"; 142 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_serial2>; 143 pinctrl-0 = <&pinctrl_serial2>;
129 clocks = <&clk_ext2f_a9>; 144 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
130 145
131 status = "disabled"; 146 status = "disabled";
132 }; 147 };
@@ -158,7 +173,7 @@
158 compatible = "st,comms-ssc4-i2c"; 173 compatible = "st,comms-ssc4-i2c";
159 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x9840000 0x110>; 175 reg = <0x9840000 0x110>;
161 clocks = <&clk_ext2f_a9>; 176 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
162 clock-names = "ssc"; 177 clock-names = "ssc";
163 clock-frequency = <400000>; 178 clock-frequency = <400000>;
164 pinctrl-names = "default"; 179 pinctrl-names = "default";
@@ -171,7 +186,7 @@
171 compatible = "st,comms-ssc4-i2c"; 186 compatible = "st,comms-ssc4-i2c";
172 reg = <0x9841000 0x110>; 187 reg = <0x9841000 0x110>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clk_ext2f_a9>; 189 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
175 clock-names = "ssc"; 190 clock-names = "ssc";
176 clock-frequency = <400000>; 191 clock-frequency = <400000>;
177 pinctrl-names = "default"; 192 pinctrl-names = "default";
@@ -184,7 +199,7 @@
184 compatible = "st,comms-ssc4-i2c"; 199 compatible = "st,comms-ssc4-i2c";
185 reg = <0x9842000 0x110>; 200 reg = <0x9842000 0x110>;
186 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk_ext2f_a9>; 202 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
188 clock-names = "ssc"; 203 clock-names = "ssc";
189 clock-frequency = <400000>; 204 clock-frequency = <400000>;
190 pinctrl-names = "default"; 205 pinctrl-names = "default";
@@ -197,7 +212,7 @@
197 compatible = "st,comms-ssc4-i2c"; 212 compatible = "st,comms-ssc4-i2c";
198 reg = <0x9843000 0x110>; 213 reg = <0x9843000 0x110>;
199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clk_ext2f_a9>; 215 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
201 clock-names = "ssc"; 216 clock-names = "ssc";
202 clock-frequency = <400000>; 217 clock-frequency = <400000>;
203 pinctrl-names = "default"; 218 pinctrl-names = "default";
@@ -210,7 +225,7 @@
210 compatible = "st,comms-ssc4-i2c"; 225 compatible = "st,comms-ssc4-i2c";
211 reg = <0x9844000 0x110>; 226 reg = <0x9844000 0x110>;
212 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clk_ext2f_a9>; 228 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
214 clock-names = "ssc"; 229 clock-names = "ssc";
215 clock-frequency = <400000>; 230 clock-frequency = <400000>;
216 pinctrl-names = "default"; 231 pinctrl-names = "default";
@@ -223,7 +238,7 @@
223 compatible = "st,comms-ssc4-i2c"; 238 compatible = "st,comms-ssc4-i2c";
224 reg = <0x9845000 0x110>; 239 reg = <0x9845000 0x110>;
225 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk_ext2f_a9>; 241 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
227 clock-names = "ssc"; 242 clock-names = "ssc";
228 clock-frequency = <400000>; 243 clock-frequency = <400000>;
229 pinctrl-names = "default"; 244 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 000000000000..2f61a9960dee
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/dts-v1/;
10#include "stih410.dtsi"
11#include "stihxxx-b2120.dtsi"
12/ {
13 model = "STiH410 B2120";
14 compatible = "st,stih410-b2120", "st,stih410";
15
16 chosen {
17 bootargs = "console=ttyAS0,115200 clk_ignore_unused";
18 linux,stdout-path = &sbc_serial0;
19 };
20
21 memory {
22 device_type = "memory";
23 reg = <0x40000000 0x80000000>;
24 };
25
26 aliases {
27 ttyAS0 = &sbc_serial0;
28 };
29};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 000000000000..6b5803a30096
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics R&D Limited
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <dt-bindings/clock/stih410-clks.h>
9/ {
10 clocks {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 ranges;
14
15 compatible = "st,stih410-clk", "simple-bus";
16
17 /*
18 * Fixed 30MHz oscillator inputs to SoC
19 */
20 clk_sysin: clk-sysin {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <30000000>;
24 clock-output-names = "CLK_SYSIN";
25 };
26
27 /*
28 * ARM Peripheral clock for timers
29 */
30 arm_periph_clk: clk-m-a9-periphs {
31 #clock-cells = <0>;
32 compatible = "fixed-factor-clock";
33 clocks = <&clk_m_a9>;
34 clock-div = <2>;
35 clock-mult = <1>;
36 };
37
38 /*
39 * A9 PLL.
40 */
41 clockgen-a9@92b0000 {
42 compatible = "st,clkgen-c32";
43 reg = <0x92b0000 0xffff>;
44
45 clockgen_a9_pll: clockgen-a9-pll {
46 #clock-cells = <1>;
47 compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
48
49 clocks = <&clk_sysin>;
50
51 clock-output-names = "clockgen-a9-pll-odf";
52 };
53 };
54
55 /*
56 * ARM CPU related clocks.
57 */
58 clk_m_a9: clk-m-a9@92b0000 {
59 #clock-cells = <0>;
60 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 reg = <0x92b0000 0x10000>;
62
63 clocks = <&clockgen_a9_pll 0>,
64 <&clockgen_a9_pll 0>,
65 <&clk_s_c0_flexgen 13>,
66 <&clk_m_a9_ext2f_div2>;
67 };
68
69 /*
70 * ARM Peripheral clock for timers
71 */
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
73 #clock-cells = <0>;
74 compatible = "fixed-factor-clock";
75
76 clocks = <&clk_s_c0_flexgen 13>;
77
78 clock-output-names = "clk-m-a9-ext2f-div2";
79
80 clock-div = <2>;
81 clock-mult = <1>;
82 };
83
84 /*
85 * Bootloader initialized system infrastructure clock for
86 * serial devices.
87 */
88 clk_ext2f_a9: clockgen-c0@13 {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <200000000>;
92 clock-output-names = "clk-s-icn-reg-0";
93 };
94
95 clockgen-a@090ff000 {
96 compatible = "st,clkgen-c32";
97 reg = <0x90ff000 0x1000>;
98
99 clk_s_a0_pll: clk-s-a0-pll {
100 #clock-cells = <1>;
101 compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
102
103 clocks = <&clk_sysin>;
104
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 };
107
108 clk_s_a0_flexgen: clk-s-a0-flexgen {
109 compatible = "st,flexgen";
110
111 #clock-cells = <1>;
112
113 clocks = <&clk_s_a0_pll 0>,
114 <&clk_sysin>;
115
116 clock-output-names = "clk-ic-lmi0",
117 "clk-ic-lmi1";
118 };
119 };
120
121 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
122 #clock-cells = <1>;
123 compatible = "st,stih407-quadfs660-C", "st,quadfs";
124 reg = <0x9103000 0x1000>;
125
126 clocks = <&clk_sysin>;
127
128 clock-output-names = "clk-s-c0-fs0-ch0",
129 "clk-s-c0-fs0-ch1",
130 "clk-s-c0-fs0-ch2",
131 "clk-s-c0-fs0-ch3";
132 };
133
134 clk_s_c0: clockgen-c@09103000 {
135 compatible = "st,clkgen-c32";
136 reg = <0x9103000 0x1000>;
137
138 clk_s_c0_pll0: clk-s-c0-pll0 {
139 #clock-cells = <1>;
140 compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
141
142 clocks = <&clk_sysin>;
143
144 clock-output-names = "clk-s-c0-pll0-odf-0";
145 };
146
147 clk_s_c0_pll1: clk-s-c0-pll1 {
148 #clock-cells = <1>;
149 compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
150
151 clocks = <&clk_sysin>;
152
153 clock-output-names = "clk-s-c0-pll1-odf-0";
154 };
155
156 clk_s_c0_flexgen: clk-s-c0-flexgen {
157 #clock-cells = <1>;
158 compatible = "st,flexgen";
159
160 clocks = <&clk_s_c0_pll0 0>,
161 <&clk_s_c0_pll1 0>,
162 <&clk_s_c0_quadfs 0>,
163 <&clk_s_c0_quadfs 1>,
164 <&clk_s_c0_quadfs 2>,
165 <&clk_s_c0_quadfs 3>,
166 <&clk_sysin>;
167
168 clock-output-names = "clk-icn-gpu",
169 "clk-fdma",
170 "clk-nand",
171 "clk-hva",
172 "clk-proc-stfe",
173 "clk-proc-tp",
174 "clk-rx-icn-dmu",
175 "clk-rx-icn-hva",
176 "clk-icn-cpu",
177 "clk-tx-icn-dmu",
178 "clk-mmc-0",
179 "clk-mmc-1",
180 "clk-jpegdec",
181 "clk-ext2fa9",
182 "clk-ic-bdisp-0",
183 "clk-ic-bdisp-1",
184 "clk-pp-dmu",
185 "clk-vid-dmu",
186 "clk-dss-lpc",
187 "clk-st231-aud-0",
188 "clk-st231-gp-1",
189 "clk-st231-dmu",
190 "clk-icn-lmi",
191 "clk-tx-icn-disp-1",
192 "clk-icn-sbc",
193 "clk-stfe-frc2",
194 "clk-eth-phy",
195 "clk-eth-ref-phyclk",
196 "clk-flash-promip",
197 "clk-main-disp",
198 "clk-aux-disp",
199 "clk-compo-dvp",
200 "clk-tx-icn-hades",
201 "clk-rx-icn-hades",
202 "clk-icn-reg-16",
203 "clk-pp-hades",
204 "clk-clust-hades",
205 "clk-hwpe-hades",
206 "clk-fc-hades";
207 };
208 };
209
210 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
211 #clock-cells = <1>;
212 compatible = "st,stih407-quadfs660-D", "st,quadfs";
213 reg = <0x9104000 0x1000>;
214
215 clocks = <&clk_sysin>;
216
217 clock-output-names = "clk-s-d0-fs0-ch0",
218 "clk-s-d0-fs0-ch1",
219 "clk-s-d0-fs0-ch2",
220 "clk-s-d0-fs0-ch3";
221 };
222
223 clockgen-d0@09104000 {
224 compatible = "st,clkgen-c32";
225 reg = <0x9104000 0x1000>;
226
227 clk_s_d0_flexgen: clk-s-d0-flexgen {
228 #clock-cells = <1>;
229 compatible = "st,flexgen";
230
231 clocks = <&clk_s_d0_quadfs 0>,
232 <&clk_s_d0_quadfs 1>,
233 <&clk_s_d0_quadfs 2>,
234 <&clk_s_d0_quadfs 3>,
235 <&clk_sysin>;
236
237 clock-output-names = "clk-pcm-0",
238 "clk-pcm-1",
239 "clk-pcm-2",
240 "clk-spdiff",
241 "clk-pcmr10-master",
242 "clk-usb2-phy";
243 };
244 };
245
246 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
247 #clock-cells = <1>;
248 compatible = "st,stih407-quadfs660-D", "st,quadfs";
249 reg = <0x9106000 0x1000>;
250
251 clocks = <&clk_sysin>;
252
253 clock-output-names = "clk-s-d2-fs0-ch0",
254 "clk-s-d2-fs0-ch1",
255 "clk-s-d2-fs0-ch2",
256 "clk-s-d2-fs0-ch3";
257 };
258
259 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
260 #clock-cells = <0>;
261 compatible = "fixed-clock";
262 clock-frequency = <0>;
263 };
264
265 clockgen-d2@x9106000 {
266 compatible = "st,clkgen-c32";
267 reg = <0x9106000 0x1000>;
268
269 clk_s_d2_flexgen: clk-s-d2-flexgen {
270 #clock-cells = <1>;
271 compatible = "st,flexgen";
272
273 clocks = <&clk_s_d2_quadfs 0>,
274 <&clk_s_d2_quadfs 1>,
275 <&clk_s_d2_quadfs 2>,
276 <&clk_s_d2_quadfs 3>,
277 <&clk_sysin>,
278 <&clk_sysin>,
279 <&clk_tmdsout_hdmi>;
280
281 clock-output-names = "clk-pix-main-disp",
282 "clk-pix-pip",
283 "clk-pix-gdp1",
284 "clk-pix-gdp2",
285 "clk-pix-gdp3",
286 "clk-pix-gdp4",
287 "clk-pix-aux-disp",
288 "clk-denc",
289 "clk-pix-hddac",
290 "clk-hddac",
291 "clk-sddac",
292 "clk-pix-dvo",
293 "clk-dvo",
294 "clk-pix-hdmi",
295 "clk-tmds-hdmi",
296 "clk-ref-hdmiphy";
297 };
298 };
299
300 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
301 #clock-cells = <1>;
302 compatible = "st,stih407-quadfs660-D", "st,quadfs";
303 reg = <0x9107000 0x1000>;
304
305 clocks = <&clk_sysin>;
306
307 clock-output-names = "clk-s-d3-fs0-ch0",
308 "clk-s-d3-fs0-ch1",
309 "clk-s-d3-fs0-ch2",
310 "clk-s-d3-fs0-ch3";
311 };
312
313 clockgen-d3@9107000 {
314 compatible = "st,clkgen-c32";
315 reg = <0x9107000 0x1000>;
316
317 clk_s_d3_flexgen: clk-s-d3-flexgen {
318 #clock-cells = <1>;
319 compatible = "st,flexgen";
320
321 clocks = <&clk_s_d3_quadfs 0>,
322 <&clk_s_d3_quadfs 1>,
323 <&clk_s_d3_quadfs 2>,
324 <&clk_s_d3_quadfs 3>,
325 <&clk_sysin>;
326
327 clock-output-names = "clk-stfe-frc1",
328 "clk-tsout-0",
329 "clk-tsout-1",
330 "clk-mchi",
331 "clk-vsens-compo",
332 "clk-frc1-remote",
333 "clk-lpc-0",
334 "clk-lpc-1";
335 };
336 };
337 };
338};
diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi
new file mode 100644
index 000000000000..b3e9dfc81c07
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10/ {
11
12 soc {
13 pin-controller-rear {
14
15 usb0 {
16 pinctrl_usb0: usb2-0 {
17 st,pins {
18 usb-oc-detect = <&pio35 0 ALT1 IN>;
19 usb-pwr-enable = <&pio35 1 ALT1 OUT>;
20 };
21 };
22 };
23
24 usb1 {
25 pinctrl_usb1: usb2-1 {
26 st,pins {
27 usb-oc-detect = <&pio35 2 ALT1 IN>;
28 usb-pwr-enable = <&pio35 3 ALT1 OUT>;
29 };
30 };
31 };
32 };
33 };
34};
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
new file mode 100644
index 000000000000..c05627eb717d
--- /dev/null
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -0,0 +1,14 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Peter Griffin <peter.griffin@linaro.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "stih410-clock.dtsi"
10#include "stih407-family.dtsi"
11#include "stih410-pinctrl.dtsi"
12/ {
13
14};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index 8509a037ae21..3791ad95dbaf 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -11,33 +11,33 @@
11/ { 11/ {
12 12
13 aliases { 13 aliases {
14 gpio0 = &PIO0; 14 gpio0 = &pio0;
15 gpio1 = &PIO1; 15 gpio1 = &pio1;
16 gpio2 = &PIO2; 16 gpio2 = &pio2;
17 gpio3 = &PIO3; 17 gpio3 = &pio3;
18 gpio4 = &PIO4; 18 gpio4 = &pio4;
19 gpio5 = &PIO5; 19 gpio5 = &pio5;
20 gpio6 = &PIO6; 20 gpio6 = &pio6;
21 gpio7 = &PIO7; 21 gpio7 = &pio7;
22 gpio8 = &PIO8; 22 gpio8 = &pio8;
23 gpio9 = &PIO9; 23 gpio9 = &pio9;
24 gpio10 = &PIO10; 24 gpio10 = &pio10;
25 gpio11 = &PIO11; 25 gpio11 = &pio11;
26 gpio12 = &PIO12; 26 gpio12 = &pio12;
27 gpio13 = &PIO13; 27 gpio13 = &pio13;
28 gpio14 = &PIO14; 28 gpio14 = &pio14;
29 gpio15 = &PIO15; 29 gpio15 = &pio15;
30 gpio16 = &PIO16; 30 gpio16 = &pio16;
31 gpio17 = &PIO17; 31 gpio17 = &pio17;
32 gpio18 = &PIO18; 32 gpio18 = &pio18;
33 gpio19 = &PIO100; 33 gpio19 = &pio100;
34 gpio20 = &PIO101; 34 gpio20 = &pio101;
35 gpio21 = &PIO102; 35 gpio21 = &pio102;
36 gpio22 = &PIO103; 36 gpio22 = &pio103;
37 gpio23 = &PIO104; 37 gpio23 = &pio104;
38 gpio24 = &PIO105; 38 gpio24 = &pio105;
39 gpio25 = &PIO106; 39 gpio25 = &pio106;
40 gpio26 = &PIO107; 40 gpio26 = &pio107;
41 }; 41 };
42 42
43 soc { 43 soc {
@@ -52,7 +52,7 @@
52 interrupt-names = "irqmux"; 52 interrupt-names = "irqmux";
53 ranges = <0 0xfe610000 0x5000>; 53 ranges = <0 0xfe610000 0x5000>;
54 54
55 PIO0: gpio@fe610000 { 55 pio0: gpio@fe610000 {
56 gpio-controller; 56 gpio-controller;
57 #gpio-cells = <1>; 57 #gpio-cells = <1>;
58 interrupt-controller; 58 interrupt-controller;
@@ -60,7 +60,7 @@
60 reg = <0 0x100>; 60 reg = <0 0x100>;
61 st,bank-name = "PIO0"; 61 st,bank-name = "PIO0";
62 }; 62 };
63 PIO1: gpio@fe611000 { 63 pio1: gpio@fe611000 {
64 gpio-controller; 64 gpio-controller;
65 #gpio-cells = <1>; 65 #gpio-cells = <1>;
66 interrupt-controller; 66 interrupt-controller;
@@ -68,7 +68,7 @@
68 reg = <0x1000 0x100>; 68 reg = <0x1000 0x100>;
69 st,bank-name = "PIO1"; 69 st,bank-name = "PIO1";
70 }; 70 };
71 PIO2: gpio@fe612000 { 71 pio2: gpio@fe612000 {
72 gpio-controller; 72 gpio-controller;
73 #gpio-cells = <1>; 73 #gpio-cells = <1>;
74 interrupt-controller; 74 interrupt-controller;
@@ -76,7 +76,7 @@
76 reg = <0x2000 0x100>; 76 reg = <0x2000 0x100>;
77 st,bank-name = "PIO2"; 77 st,bank-name = "PIO2";
78 }; 78 };
79 PIO3: gpio@fe613000 { 79 pio3: gpio@fe613000 {
80 gpio-controller; 80 gpio-controller;
81 #gpio-cells = <1>; 81 #gpio-cells = <1>;
82 interrupt-controller; 82 interrupt-controller;
@@ -84,7 +84,7 @@
84 reg = <0x3000 0x100>; 84 reg = <0x3000 0x100>;
85 st,bank-name = "PIO3"; 85 st,bank-name = "PIO3";
86 }; 86 };
87 PIO4: gpio@fe614000 { 87 pio4: gpio@fe614000 {
88 gpio-controller; 88 gpio-controller;
89 #gpio-cells = <1>; 89 #gpio-cells = <1>;
90 interrupt-controller; 90 interrupt-controller;
@@ -96,8 +96,8 @@
96 sbc_serial1 { 96 sbc_serial1 {
97 pinctrl_sbc_serial1:sbc_serial1 { 97 pinctrl_sbc_serial1:sbc_serial1 {
98 st,pins { 98 st,pins {
99 tx = <&PIO2 6 ALT3 OUT>; 99 tx = <&pio2 6 ALT3 OUT>;
100 rx = <&PIO2 7 ALT3 IN>; 100 rx = <&pio2 7 ALT3 IN>;
101 }; 101 };
102 }; 102 };
103 }; 103 };
@@ -105,15 +105,15 @@
105 keyscan { 105 keyscan {
106 pinctrl_keyscan: keyscan { 106 pinctrl_keyscan: keyscan {
107 st,pins { 107 st,pins {
108 keyin0 = <&PIO0 2 ALT2 IN>; 108 keyin0 = <&pio0 2 ALT2 IN>;
109 keyin1 = <&PIO0 3 ALT2 IN>; 109 keyin1 = <&pio0 3 ALT2 IN>;
110 keyin2 = <&PIO0 4 ALT2 IN>; 110 keyin2 = <&pio0 4 ALT2 IN>;
111 keyin3 = <&PIO2 6 ALT2 IN>; 111 keyin3 = <&pio2 6 ALT2 IN>;
112 112
113 keyout0 = <&PIO1 6 ALT2 OUT>; 113 keyout0 = <&pio1 6 ALT2 OUT>;
114 keyout1 = <&PIO1 7 ALT2 OUT>; 114 keyout1 = <&pio1 7 ALT2 OUT>;
115 keyout2 = <&PIO0 6 ALT2 OUT>; 115 keyout2 = <&pio0 6 ALT2 OUT>;
116 keyout3 = <&PIO2 7 ALT2 OUT>; 116 keyout3 = <&pio2 7 ALT2 OUT>;
117 }; 117 };
118 }; 118 };
119 }; 119 };
@@ -121,8 +121,8 @@
121 sbc_i2c0 { 121 sbc_i2c0 {
122 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 122 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
123 st,pins { 123 st,pins {
124 sda = <&PIO4 6 ALT1 BIDIR>; 124 sda = <&pio4 6 ALT1 BIDIR>;
125 scl = <&PIO4 5 ALT1 BIDIR>; 125 scl = <&pio4 5 ALT1 BIDIR>;
126 }; 126 };
127 }; 127 };
128 }; 128 };
@@ -130,8 +130,8 @@
130 sbc_i2c1 { 130 sbc_i2c1 {
131 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 131 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
132 st,pins { 132 st,pins {
133 sda = <&PIO3 2 ALT2 BIDIR>; 133 sda = <&pio3 2 ALT2 BIDIR>;
134 scl = <&PIO3 1 ALT2 BIDIR>; 134 scl = <&pio3 1 ALT2 BIDIR>;
135 }; 135 };
136 }; 136 };
137 }; 137 };
@@ -139,7 +139,7 @@
139 rc{ 139 rc{
140 pinctrl_ir: ir0 { 140 pinctrl_ir: ir0 {
141 st,pins { 141 st,pins {
142 ir = <&PIO4 0 ALT2 IN>; 142 ir = <&pio4 0 ALT2 IN>;
143 }; 143 };
144 }; 144 };
145 }; 145 };
@@ -147,49 +147,49 @@
147 gmac1 { 147 gmac1 {
148 pinctrl_mii1: mii1 { 148 pinctrl_mii1: mii1 {
149 st,pins { 149 st,pins {
150 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 150 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
151 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 151 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
152 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 152 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
153 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 153 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
154 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 154 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
155 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 155 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
156 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 156 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
157 col = <&PIO0 7 ALT1 IN BYPASS 1000>; 157 col = <&pio0 7 ALT1 IN BYPASS 1000>;
158 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 158 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
159 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 159 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
160 crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 160 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
161 mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 161 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
162 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 162 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
163 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 163 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
164 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 164 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
165 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 165 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
166 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 166 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
167 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 167 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
168 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 168 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
169 phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; 169 phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>;
170 }; 170 };
171 }; 171 };
172 172
173 pinctrl_rgmii1: rgmii1-0 { 173 pinctrl_rgmii1: rgmii1-0 {
174 st,pins { 174 st,pins {
175 txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; 175 txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>;
176 txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; 176 txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>;
177 txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; 177 txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>;
178 txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; 178 txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>;
179 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 179 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
180 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 180 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
181 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 181 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
182 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 182 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
183 rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; 183 rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
184 rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; 184 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
185 rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; 185 rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
186 rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; 186 rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
187 187
188 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 188 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
189 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 189 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
190 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 190 phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
191 191
192 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 192 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
193 }; 193 };
194 }; 194 };
195 }; 195 };
@@ -206,7 +206,7 @@
206 interrupt-names = "irqmux"; 206 interrupt-names = "irqmux";
207 ranges = <0 0xfee00000 0x8000>; 207 ranges = <0 0xfee00000 0x8000>;
208 208
209 PIO5: gpio@fee00000 { 209 pio5: gpio@fee00000 {
210 gpio-controller; 210 gpio-controller;
211 #gpio-cells = <1>; 211 #gpio-cells = <1>;
212 interrupt-controller; 212 interrupt-controller;
@@ -214,7 +214,7 @@
214 reg = <0 0x100>; 214 reg = <0 0x100>;
215 st,bank-name = "PIO5"; 215 st,bank-name = "PIO5";
216 }; 216 };
217 PIO6: gpio@fee01000 { 217 pio6: gpio@fee01000 {
218 gpio-controller; 218 gpio-controller;
219 #gpio-cells = <1>; 219 #gpio-cells = <1>;
220 interrupt-controller; 220 interrupt-controller;
@@ -222,7 +222,7 @@
222 reg = <0x1000 0x100>; 222 reg = <0x1000 0x100>;
223 st,bank-name = "PIO6"; 223 st,bank-name = "PIO6";
224 }; 224 };
225 PIO7: gpio@fee02000 { 225 pio7: gpio@fee02000 {
226 gpio-controller; 226 gpio-controller;
227 #gpio-cells = <1>; 227 #gpio-cells = <1>;
228 interrupt-controller; 228 interrupt-controller;
@@ -230,7 +230,7 @@
230 reg = <0x2000 0x100>; 230 reg = <0x2000 0x100>;
231 st,bank-name = "PIO7"; 231 st,bank-name = "PIO7";
232 }; 232 };
233 PIO8: gpio@fee03000 { 233 pio8: gpio@fee03000 {
234 gpio-controller; 234 gpio-controller;
235 #gpio-cells = <1>; 235 #gpio-cells = <1>;
236 interrupt-controller; 236 interrupt-controller;
@@ -238,7 +238,7 @@
238 reg = <0x3000 0x100>; 238 reg = <0x3000 0x100>;
239 st,bank-name = "PIO8"; 239 st,bank-name = "PIO8";
240 }; 240 };
241 PIO9: gpio@fee04000 { 241 pio9: gpio@fee04000 {
242 gpio-controller; 242 gpio-controller;
243 #gpio-cells = <1>; 243 #gpio-cells = <1>;
244 interrupt-controller; 244 interrupt-controller;
@@ -246,7 +246,7 @@
246 reg = <0x4000 0x100>; 246 reg = <0x4000 0x100>;
247 st,bank-name = "PIO9"; 247 st,bank-name = "PIO9";
248 }; 248 };
249 PIO10: gpio@fee05000 { 249 pio10: gpio@fee05000 {
250 gpio-controller; 250 gpio-controller;
251 #gpio-cells = <1>; 251 #gpio-cells = <1>;
252 interrupt-controller; 252 interrupt-controller;
@@ -254,7 +254,7 @@
254 reg = <0x5000 0x100>; 254 reg = <0x5000 0x100>;
255 st,bank-name = "PIO10"; 255 st,bank-name = "PIO10";
256 }; 256 };
257 PIO11: gpio@fee06000 { 257 pio11: gpio@fee06000 {
258 gpio-controller; 258 gpio-controller;
259 #gpio-cells = <1>; 259 #gpio-cells = <1>;
260 interrupt-controller; 260 interrupt-controller;
@@ -262,7 +262,7 @@
262 reg = <0x6000 0x100>; 262 reg = <0x6000 0x100>;
263 st,bank-name = "PIO11"; 263 st,bank-name = "PIO11";
264 }; 264 };
265 PIO12: gpio@fee07000 { 265 pio12: gpio@fee07000 {
266 gpio-controller; 266 gpio-controller;
267 #gpio-cells = <1>; 267 #gpio-cells = <1>;
268 interrupt-controller; 268 interrupt-controller;
@@ -274,8 +274,8 @@
274 i2c0 { 274 i2c0 {
275 pinctrl_i2c0_default: i2c0-default { 275 pinctrl_i2c0_default: i2c0-default {
276 st,pins { 276 st,pins {
277 sda = <&PIO9 3 ALT1 BIDIR>; 277 sda = <&pio9 3 ALT1 BIDIR>;
278 scl = <&PIO9 2 ALT1 BIDIR>; 278 scl = <&pio9 2 ALT1 BIDIR>;
279 }; 279 };
280 }; 280 };
281 }; 281 };
@@ -283,8 +283,8 @@
283 i2c1 { 283 i2c1 {
284 pinctrl_i2c1_default: i2c1-default { 284 pinctrl_i2c1_default: i2c1-default {
285 st,pins { 285 st,pins {
286 sda = <&PIO12 1 ALT1 BIDIR>; 286 sda = <&pio12 1 ALT1 BIDIR>;
287 scl = <&PIO12 0 ALT1 BIDIR>; 287 scl = <&pio12 0 ALT1 BIDIR>;
288 }; 288 };
289 }; 289 };
290 }; 290 };
@@ -301,7 +301,7 @@
301 interrupt-names = "irqmux"; 301 interrupt-names = "irqmux";
302 ranges = <0 0xfe820000 0x8000>; 302 ranges = <0 0xfe820000 0x8000>;
303 303
304 PIO13: gpio@fe820000 { 304 pio13: gpio@fe820000 {
305 gpio-controller; 305 gpio-controller;
306 #gpio-cells = <1>; 306 #gpio-cells = <1>;
307 interrupt-controller; 307 interrupt-controller;
@@ -309,7 +309,7 @@
309 reg = <0 0x100>; 309 reg = <0 0x100>;
310 st,bank-name = "PIO13"; 310 st,bank-name = "PIO13";
311 }; 311 };
312 PIO14: gpio@fe821000 { 312 pio14: gpio@fe821000 {
313 gpio-controller; 313 gpio-controller;
314 #gpio-cells = <1>; 314 #gpio-cells = <1>;
315 interrupt-controller; 315 interrupt-controller;
@@ -317,7 +317,7 @@
317 reg = <0x1000 0x100>; 317 reg = <0x1000 0x100>;
318 st,bank-name = "PIO14"; 318 st,bank-name = "PIO14";
319 }; 319 };
320 PIO15: gpio@fe822000 { 320 pio15: gpio@fe822000 {
321 gpio-controller; 321 gpio-controller;
322 #gpio-cells = <1>; 322 #gpio-cells = <1>;
323 interrupt-controller; 323 interrupt-controller;
@@ -325,7 +325,7 @@
325 reg = <0x2000 0x100>; 325 reg = <0x2000 0x100>;
326 st,bank-name = "PIO15"; 326 st,bank-name = "PIO15";
327 }; 327 };
328 PIO16: gpio@fe823000 { 328 pio16: gpio@fe823000 {
329 gpio-controller; 329 gpio-controller;
330 #gpio-cells = <1>; 330 #gpio-cells = <1>;
331 interrupt-controller; 331 interrupt-controller;
@@ -333,7 +333,7 @@
333 reg = <0x3000 0x100>; 333 reg = <0x3000 0x100>;
334 st,bank-name = "PIO16"; 334 st,bank-name = "PIO16";
335 }; 335 };
336 PIO17: gpio@fe824000 { 336 pio17: gpio@fe824000 {
337 gpio-controller; 337 gpio-controller;
338 #gpio-cells = <1>; 338 #gpio-cells = <1>;
339 interrupt-controller; 339 interrupt-controller;
@@ -341,7 +341,7 @@
341 reg = <0x4000 0x100>; 341 reg = <0x4000 0x100>;
342 st,bank-name = "PIO17"; 342 st,bank-name = "PIO17";
343 }; 343 };
344 PIO18: gpio@fe825000 { 344 pio18: gpio@fe825000 {
345 gpio-controller; 345 gpio-controller;
346 #gpio-cells = <1>; 346 #gpio-cells = <1>;
347 interrupt-controller; 347 interrupt-controller;
@@ -353,8 +353,8 @@
353 serial2 { 353 serial2 {
354 pinctrl_serial2: serial2-0 { 354 pinctrl_serial2: serial2-0 {
355 st,pins { 355 st,pins {
356 tx = <&PIO17 4 ALT2 OUT>; 356 tx = <&pio17 4 ALT2 OUT>;
357 rx = <&PIO17 5 ALT2 IN>; 357 rx = <&pio17 5 ALT2 IN>;
358 }; 358 };
359 }; 359 };
360 }; 360 };
@@ -362,73 +362,94 @@
362 gmac0{ 362 gmac0{
363 pinctrl_mii0: mii0 { 363 pinctrl_mii0: mii0 {
364 st,pins { 364 st,pins {
365 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 365 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
366 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 366 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
367 367
368 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 368 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
369 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 369 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
370 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 370 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
371 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 371 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
372 372
373 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 373 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
374 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 374 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
375 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 375 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
376 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 376 col = <&pio15 3 ALT2 IN BYPASS 1000>;
377 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 377 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
378 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 378 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
379 379
380 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 380 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
381 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 381 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
382 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 382 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
383 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 383 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
384 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 384 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
385 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 385 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
386 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 386 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
387 phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; 387 phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>;
388 388
389 }; 389 };
390 }; 390 };
391 391
392 pinctrl_gmii0: gmii0 { 392 pinctrl_gmii0: gmii0 {
393 st,pins { 393 st,pins {
394 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 394 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
395 mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; 395 mdio = <&pio15 4 ALT2 OUT BYPASS 3000>;
396 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 396 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
397 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 397 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
398 398
399 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 399 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
400 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 400 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
401 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 401 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
402 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 402 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
403 txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 403 txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
404 txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 404 txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
405 txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 405 txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
406 txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; 406 txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>;
407 407
408 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 408 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
409 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; 409 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>;
410 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 410 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
411 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 411 col = <&pio15 3 ALT2 IN BYPASS 1000>;
412 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 412 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
413 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 413 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
414 414
415 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 415 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
416 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 416 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
417 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 417 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
418 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 418 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
419 rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 419 rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
420 rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 420 rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
421 rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 421 rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
422 rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; 422 rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>;
423 423
424 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 424 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
425 clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 425 clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>;
426 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 426 phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
427 427
428 428
429 }; 429 };
430 }; 430 };
431 }; 431 };
432
433 mmc0 {
434 pinctrl_mmc0: mmc0 {
435 st,pins {
436 mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
437 data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
438 data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
439 data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
440 data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
441 cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
442 wp = <&pio15 3 ALT4 IN>;
443 data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
444 data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
445 data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
446 data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
447 pwr = <&pio17 1 ALT4 OUT>;
448 cd = <&pio17 2 ALT4 IN>;
449 led = <&pio17 3 ALT4 OUT>;
450 };
451 };
452 };
432 }; 453 };
433 454
434 pin-controller-left { 455 pin-controller-left {
@@ -442,7 +463,7 @@
442 interrupt-names = "irqmux"; 463 interrupt-names = "irqmux";
443 ranges = <0 0xfd6b0000 0x3000>; 464 ranges = <0 0xfd6b0000 0x3000>;
444 465
445 PIO100: gpio@fd6b0000 { 466 pio100: gpio@fd6b0000 {
446 gpio-controller; 467 gpio-controller;
447 #gpio-cells = <1>; 468 #gpio-cells = <1>;
448 interrupt-controller; 469 interrupt-controller;
@@ -450,7 +471,7 @@
450 reg = <0 0x100>; 471 reg = <0 0x100>;
451 st,bank-name = "PIO100"; 472 st,bank-name = "PIO100";
452 }; 473 };
453 PIO101: gpio@fd6b1000 { 474 pio101: gpio@fd6b1000 {
454 gpio-controller; 475 gpio-controller;
455 #gpio-cells = <1>; 476 #gpio-cells = <1>;
456 interrupt-controller; 477 interrupt-controller;
@@ -458,7 +479,7 @@
458 reg = <0x1000 0x100>; 479 reg = <0x1000 0x100>;
459 st,bank-name = "PIO101"; 480 st,bank-name = "PIO101";
460 }; 481 };
461 PIO102: gpio@fd6b2000 { 482 pio102: gpio@fd6b2000 {
462 gpio-controller; 483 gpio-controller;
463 #gpio-cells = <1>; 484 #gpio-cells = <1>;
464 interrupt-controller; 485 interrupt-controller;
@@ -479,7 +500,7 @@
479 interrupt-names = "irqmux"; 500 interrupt-names = "irqmux";
480 ranges = <0 0xfd330000 0x5000>; 501 ranges = <0 0xfd330000 0x5000>;
481 502
482 PIO103: gpio@fd330000 { 503 pio103: gpio@fd330000 {
483 gpio-controller; 504 gpio-controller;
484 #gpio-cells = <1>; 505 #gpio-cells = <1>;
485 interrupt-controller; 506 interrupt-controller;
@@ -487,7 +508,7 @@
487 reg = <0 0x100>; 508 reg = <0 0x100>;
488 st,bank-name = "PIO103"; 509 st,bank-name = "PIO103";
489 }; 510 };
490 PIO104: gpio@fd331000 { 511 pio104: gpio@fd331000 {
491 gpio-controller; 512 gpio-controller;
492 #gpio-cells = <1>; 513 #gpio-cells = <1>;
493 interrupt-controller; 514 interrupt-controller;
@@ -495,7 +516,7 @@
495 reg = <0x1000 0x100>; 516 reg = <0x1000 0x100>;
496 st,bank-name = "PIO104"; 517 st,bank-name = "PIO104";
497 }; 518 };
498 PIO105: gpio@fd332000 { 519 pio105: gpio@fd332000 {
499 gpio-controller; 520 gpio-controller;
500 #gpio-cells = <1>; 521 #gpio-cells = <1>;
501 interrupt-controller; 522 interrupt-controller;
@@ -503,7 +524,7 @@
503 reg = <0x2000 0x100>; 524 reg = <0x2000 0x100>;
504 st,bank-name = "PIO105"; 525 st,bank-name = "PIO105";
505 }; 526 };
506 PIO106: gpio@fd333000 { 527 pio106: gpio@fd333000 {
507 gpio-controller; 528 gpio-controller;
508 #gpio-cells = <1>; 529 #gpio-cells = <1>;
509 interrupt-controller; 530 interrupt-controller;
@@ -511,7 +532,7 @@
511 reg = <0x3000 0x100>; 532 reg = <0x3000 0x100>;
512 st,bank-name = "PIO106"; 533 st,bank-name = "PIO106";
513 }; 534 };
514 PIO107: gpio@fd334000 { 535 pio107: gpio@fd334000 {
515 gpio-controller; 536 gpio-controller;
516 #gpio-cells = <1>; 537 #gpio-cells = <1>;
517 interrupt-controller; 538 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index a0f6f75fe3b5..9198c12765ea 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -218,5 +218,17 @@
218 resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, 218 resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
219 <&softreset STIH415_KEYSCAN_SOFTRESET>; 219 <&softreset STIH415_KEYSCAN_SOFTRESET>;
220 }; 220 };
221
222 mmc0: sdhci@fe81e000 {
223 compatible = "st,sdhci";
224 status = "disabled";
225 reg = <0xfe81e000 0x1000>;
226 interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>;
227 interrupt-names = "mmcirq";
228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_mmc0>;
230 clock-names = "mmc";
231 clocks = <&clk_s_a1_ls 1>;
232 };
221 }; 233 };
222}; 234};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 4e2df66b99ea..200a81844765 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -12,4 +12,26 @@
12/ { 12/ {
13 model = "STiH416 B2020"; 13 model = "STiH416 B2020";
14 compatible = "st,stih416-b2020", "st,stih416"; 14 compatible = "st,stih416-b2020", "st,stih416";
15
16 soc {
17 mmc1: sdhci@fe81f000 {
18 status = "okay";
19 bus-width = <8>;
20 non-removable;
21 };
22
23 miphy365x_phy: phy@fe382000 {
24 phy_port0: port@fe382000 {
25 st,sata-gen = <3>;
26 };
27
28 phy_port1: port@fe38a000 {
29 st,pcie-tx-pol-inv;
30 };
31 };
32
33 sata0: sata@fe380000{
34 status = "okay";
35 };
36 };
15}; 37};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index ba0fa2caaf18..961799e1dc51 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -19,17 +19,37 @@
19 red { 19 red {
20 #gpio-cells = <1>; 20 #gpio-cells = <1>;
21 label = "Front Panel LED"; 21 label = "Front Panel LED";
22 gpios = <&PIO4 1>; 22 gpios = <&pio4 1>;
23 linux,default-trigger = "heartbeat"; 23 linux,default-trigger = "heartbeat";
24 }; 24 };
25 green { 25 green {
26 gpios = <&PIO1 3>; 26 gpios = <&pio1 3>;
27 default-state = "off"; 27 default-state = "off";
28 }; 28 };
29 }; 29 };
30 30
31 ethernet1: dwmac@fef08000 { 31 ethernet1: dwmac@fef08000 {
32 snps,reset-gpio = <&PIO0 7>; 32 snps,reset-gpio = <&pio0 7>;
33 };
34
35 mmc1: sdhci@fe81f000 {
36 status = "okay";
37 bus-width = <8>;
38 non-removable;
39 };
40
41 miphy365x_phy: phy@fe382000 {
42 phy_port0: port@fe382000 {
43 st,sata-gen = <3>;
44 };
45
46 phy_port1: port@fe38a000 {
47 st,pcie-tx-pol-inv;
48 };
49 };
50
51 sata0: sata@fe380000{
52 status = "okay";
33 }; 53 };
34 }; 54 };
35}; 55};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index ee6c119e261e..9cccf2d6aa26 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -12,36 +12,36 @@
12/ { 12/ {
13 13
14 aliases { 14 aliases {
15 gpio0 = &PIO0; 15 gpio0 = &pio0;
16 gpio1 = &PIO1; 16 gpio1 = &pio1;
17 gpio2 = &PIO2; 17 gpio2 = &pio2;
18 gpio3 = &PIO3; 18 gpio3 = &pio3;
19 gpio4 = &PIO4; 19 gpio4 = &pio4;
20 gpio5 = &PIO40; 20 gpio5 = &pio40;
21 gpio6 = &PIO5; 21 gpio6 = &pio5;
22 gpio7 = &PIO6; 22 gpio7 = &pio6;
23 gpio8 = &PIO7; 23 gpio8 = &pio7;
24 gpio9 = &PIO8; 24 gpio9 = &pio8;
25 gpio10 = &PIO9; 25 gpio10 = &pio9;
26 gpio11 = &PIO10; 26 gpio11 = &pio10;
27 gpio12 = &PIO11; 27 gpio12 = &pio11;
28 gpio13 = &PIO12; 28 gpio13 = &pio12;
29 gpio14 = &PIO30; 29 gpio14 = &pio30;
30 gpio15 = &PIO31; 30 gpio15 = &pio31;
31 gpio16 = &PIO13; 31 gpio16 = &pio13;
32 gpio17 = &PIO14; 32 gpio17 = &pio14;
33 gpio18 = &PIO15; 33 gpio18 = &pio15;
34 gpio19 = &PIO16; 34 gpio19 = &pio16;
35 gpio20 = &PIO17; 35 gpio20 = &pio17;
36 gpio21 = &PIO18; 36 gpio21 = &pio18;
37 gpio22 = &PIO100; 37 gpio22 = &pio100;
38 gpio23 = &PIO101; 38 gpio23 = &pio101;
39 gpio24 = &PIO102; 39 gpio24 = &pio102;
40 gpio25 = &PIO103; 40 gpio25 = &pio103;
41 gpio26 = &PIO104; 41 gpio26 = &pio104;
42 gpio27 = &PIO105; 42 gpio27 = &pio105;
43 gpio28 = &PIO106; 43 gpio28 = &pio106;
44 gpio29 = &PIO107; 44 gpio29 = &pio107;
45 }; 45 };
46 46
47 soc { 47 soc {
@@ -56,7 +56,7 @@
56 interrupt-names = "irqmux"; 56 interrupt-names = "irqmux";
57 ranges = <0 0xfe610000 0x6000>; 57 ranges = <0 0xfe610000 0x6000>;
58 58
59 PIO0: gpio@fe610000 { 59 pio0: gpio@fe610000 {
60 gpio-controller; 60 gpio-controller;
61 #gpio-cells = <1>; 61 #gpio-cells = <1>;
62 interrupt-controller; 62 interrupt-controller;
@@ -64,7 +64,7 @@
64 reg = <0 0x100>; 64 reg = <0 0x100>;
65 st,bank-name = "PIO0"; 65 st,bank-name = "PIO0";
66 }; 66 };
67 PIO1: gpio@fe611000 { 67 pio1: gpio@fe611000 {
68 gpio-controller; 68 gpio-controller;
69 #gpio-cells = <1>; 69 #gpio-cells = <1>;
70 interrupt-controller; 70 interrupt-controller;
@@ -72,7 +72,7 @@
72 reg = <0x1000 0x100>; 72 reg = <0x1000 0x100>;
73 st,bank-name = "PIO1"; 73 st,bank-name = "PIO1";
74 }; 74 };
75 PIO2: gpio@fe612000 { 75 pio2: gpio@fe612000 {
76 gpio-controller; 76 gpio-controller;
77 #gpio-cells = <1>; 77 #gpio-cells = <1>;
78 interrupt-controller; 78 interrupt-controller;
@@ -80,7 +80,7 @@
80 reg = <0x2000 0x100>; 80 reg = <0x2000 0x100>;
81 st,bank-name = "PIO2"; 81 st,bank-name = "PIO2";
82 }; 82 };
83 PIO3: gpio@fe613000 { 83 pio3: gpio@fe613000 {
84 gpio-controller; 84 gpio-controller;
85 #gpio-cells = <1>; 85 #gpio-cells = <1>;
86 interrupt-controller; 86 interrupt-controller;
@@ -88,7 +88,7 @@
88 reg = <0x3000 0x100>; 88 reg = <0x3000 0x100>;
89 st,bank-name = "PIO3"; 89 st,bank-name = "PIO3";
90 }; 90 };
91 PIO4: gpio@fe614000 { 91 pio4: gpio@fe614000 {
92 gpio-controller; 92 gpio-controller;
93 #gpio-cells = <1>; 93 #gpio-cells = <1>;
94 interrupt-controller; 94 interrupt-controller;
@@ -96,7 +96,7 @@
96 reg = <0x4000 0x100>; 96 reg = <0x4000 0x100>;
97 st,bank-name = "PIO4"; 97 st,bank-name = "PIO4";
98 }; 98 };
99 PIO40: gpio@fe615000 { 99 pio40: gpio@fe615000 {
100 gpio-controller; 100 gpio-controller;
101 #gpio-cells = <1>; 101 #gpio-cells = <1>;
102 interrupt-controller; 102 interrupt-controller;
@@ -109,15 +109,15 @@
109 rc{ 109 rc{
110 pinctrl_ir: ir0 { 110 pinctrl_ir: ir0 {
111 st,pins { 111 st,pins {
112 ir = <&PIO4 0 ALT2 IN>; 112 ir = <&pio4 0 ALT2 IN>;
113 }; 113 };
114 }; 114 };
115 }; 115 };
116 sbc_serial1 { 116 sbc_serial1 {
117 pinctrl_sbc_serial1: sbc_serial1 { 117 pinctrl_sbc_serial1: sbc_serial1 {
118 st,pins { 118 st,pins {
119 tx = <&PIO2 6 ALT3 OUT>; 119 tx = <&pio2 6 ALT3 OUT>;
120 rx = <&PIO2 7 ALT3 IN>; 120 rx = <&pio2 7 ALT3 IN>;
121 }; 121 };
122 }; 122 };
123 }; 123 };
@@ -125,15 +125,15 @@
125 keyscan { 125 keyscan {
126 pinctrl_keyscan: keyscan { 126 pinctrl_keyscan: keyscan {
127 st,pins { 127 st,pins {
128 keyin0 = <&PIO0 2 ALT2 IN>; 128 keyin0 = <&pio0 2 ALT2 IN>;
129 keyin1 = <&PIO0 3 ALT2 IN>; 129 keyin1 = <&pio0 3 ALT2 IN>;
130 keyin2 = <&PIO0 4 ALT2 IN>; 130 keyin2 = <&pio0 4 ALT2 IN>;
131 keyin3 = <&PIO2 6 ALT2 IN>; 131 keyin3 = <&pio2 6 ALT2 IN>;
132 132
133 keyout0 = <&PIO1 6 ALT2 OUT>; 133 keyout0 = <&pio1 6 ALT2 OUT>;
134 keyout1 = <&PIO1 7 ALT2 OUT>; 134 keyout1 = <&pio1 7 ALT2 OUT>;
135 keyout2 = <&PIO0 6 ALT2 OUT>; 135 keyout2 = <&pio0 6 ALT2 OUT>;
136 keyout3 = <&PIO2 7 ALT2 OUT>; 136 keyout3 = <&pio2 7 ALT2 OUT>;
137 }; 137 };
138 }; 138 };
139 }; 139 };
@@ -141,8 +141,17 @@
141 sbc_i2c0 { 141 sbc_i2c0 {
142 pinctrl_sbc_i2c0_default: sbc_i2c0-default { 142 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
143 st,pins { 143 st,pins {
144 sda = <&PIO4 6 ALT1 BIDIR>; 144 sda = <&pio4 6 ALT1 BIDIR>;
145 scl = <&PIO4 5 ALT1 BIDIR>; 145 scl = <&pio4 5 ALT1 BIDIR>;
146 };
147 };
148 };
149
150 usb {
151 pinctrl_usb3: usb3 {
152 st,pins {
153 oc-detect = <&pio40 0 ALT1 IN>;
154 pwr-enable = <&pio40 1 ALT1 OUT>;
146 }; 155 };
147 }; 156 };
148 }; 157 };
@@ -150,8 +159,8 @@
150 sbc_i2c1 { 159 sbc_i2c1 {
151 pinctrl_sbc_i2c1_default: sbc_i2c1-default { 160 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
152 st,pins { 161 st,pins {
153 sda = <&PIO3 2 ALT2 BIDIR>; 162 sda = <&pio3 2 ALT2 BIDIR>;
154 scl = <&PIO3 1 ALT2 BIDIR>; 163 scl = <&pio3 1 ALT2 BIDIR>;
155 }; 164 };
156 }; 165 };
157 }; 166 };
@@ -159,51 +168,51 @@
159 gmac1 { 168 gmac1 {
160 pinctrl_mii1: mii1 { 169 pinctrl_mii1: mii1 {
161 st,pins { 170 st,pins {
162 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 171 txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
163 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 172 txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
164 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 173 txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
165 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 174 txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
166 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 175 txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
167 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; 176 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
168 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 177 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
169 col = <&PIO0 7 ALT1 IN BYPASS 1000>; 178 col = <&pio0 7 ALT1 IN BYPASS 1000>;
170 179
171 mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; 180 mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
172 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 181 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
173 crs = <&PIO1 2 ALT1 IN BYPASS 1000>; 182 crs = <&pio1 2 ALT1 IN BYPASS 1000>;
174 mdint = <&PIO1 3 ALT1 IN BYPASS 0>; 183 mdint = <&pio1 3 ALT1 IN BYPASS 0>;
175 rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; 184 rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
176 rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; 185 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
177 rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; 186 rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
178 rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; 187 rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
179 188
180 rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; 189 rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
181 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; 190 rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
182 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 191 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
183 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; 192 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
184 }; 193 };
185 }; 194 };
186 pinctrl_rgmii1: rgmii1-0 { 195 pinctrl_rgmii1: rgmii1-0 {
187 st,pins { 196 st,pins {
188 txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; 197 txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
189 txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; 198 txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
190 txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; 199 txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
191 txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; 200 txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
192 txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; 201 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
193 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; 202 txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
194 203
195 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; 204 mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
196 mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; 205 mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
197 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; 206 rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
198 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; 207 rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
199 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; 208 rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
200 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; 209 rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
201 210
202 rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; 211 rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
203 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; 212 rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
204 phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; 213 phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
205 214
206 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; 215 clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
207 }; 216 };
208 }; 217 };
209 }; 218 };
@@ -220,7 +229,7 @@
220 interrupt-names = "irqmux"; 229 interrupt-names = "irqmux";
221 ranges = <0 0xfee00000 0x10000>; 230 ranges = <0 0xfee00000 0x10000>;
222 231
223 PIO5: gpio@fee00000 { 232 pio5: gpio@fee00000 {
224 gpio-controller; 233 gpio-controller;
225 #gpio-cells = <1>; 234 #gpio-cells = <1>;
226 interrupt-controller; 235 interrupt-controller;
@@ -228,7 +237,7 @@
228 reg = <0 0x100>; 237 reg = <0 0x100>;
229 st,bank-name = "PIO5"; 238 st,bank-name = "PIO5";
230 }; 239 };
231 PIO6: gpio@fee01000 { 240 pio6: gpio@fee01000 {
232 gpio-controller; 241 gpio-controller;
233 #gpio-cells = <1>; 242 #gpio-cells = <1>;
234 interrupt-controller; 243 interrupt-controller;
@@ -236,7 +245,7 @@
236 reg = <0x1000 0x100>; 245 reg = <0x1000 0x100>;
237 st,bank-name = "PIO6"; 246 st,bank-name = "PIO6";
238 }; 247 };
239 PIO7: gpio@fee02000 { 248 pio7: gpio@fee02000 {
240 gpio-controller; 249 gpio-controller;
241 #gpio-cells = <1>; 250 #gpio-cells = <1>;
242 interrupt-controller; 251 interrupt-controller;
@@ -244,7 +253,7 @@
244 reg = <0x2000 0x100>; 253 reg = <0x2000 0x100>;
245 st,bank-name = "PIO7"; 254 st,bank-name = "PIO7";
246 }; 255 };
247 PIO8: gpio@fee03000 { 256 pio8: gpio@fee03000 {
248 gpio-controller; 257 gpio-controller;
249 #gpio-cells = <1>; 258 #gpio-cells = <1>;
250 interrupt-controller; 259 interrupt-controller;
@@ -252,7 +261,7 @@
252 reg = <0x3000 0x100>; 261 reg = <0x3000 0x100>;
253 st,bank-name = "PIO8"; 262 st,bank-name = "PIO8";
254 }; 263 };
255 PIO9: gpio@fee04000 { 264 pio9: gpio@fee04000 {
256 gpio-controller; 265 gpio-controller;
257 #gpio-cells = <1>; 266 #gpio-cells = <1>;
258 interrupt-controller; 267 interrupt-controller;
@@ -260,7 +269,7 @@
260 reg = <0x4000 0x100>; 269 reg = <0x4000 0x100>;
261 st,bank-name = "PIO9"; 270 st,bank-name = "PIO9";
262 }; 271 };
263 PIO10: gpio@fee05000 { 272 pio10: gpio@fee05000 {
264 gpio-controller; 273 gpio-controller;
265 #gpio-cells = <1>; 274 #gpio-cells = <1>;
266 interrupt-controller; 275 interrupt-controller;
@@ -268,7 +277,7 @@
268 reg = <0x5000 0x100>; 277 reg = <0x5000 0x100>;
269 st,bank-name = "PIO10"; 278 st,bank-name = "PIO10";
270 }; 279 };
271 PIO11: gpio@fee06000 { 280 pio11: gpio@fee06000 {
272 gpio-controller; 281 gpio-controller;
273 #gpio-cells = <1>; 282 #gpio-cells = <1>;
274 interrupt-controller; 283 interrupt-controller;
@@ -276,7 +285,7 @@
276 reg = <0x6000 0x100>; 285 reg = <0x6000 0x100>;
277 st,bank-name = "PIO11"; 286 st,bank-name = "PIO11";
278 }; 287 };
279 PIO12: gpio@fee07000 { 288 pio12: gpio@fee07000 {
280 gpio-controller; 289 gpio-controller;
281 #gpio-cells = <1>; 290 #gpio-cells = <1>;
282 interrupt-controller; 291 interrupt-controller;
@@ -284,7 +293,7 @@
284 reg = <0x7000 0x100>; 293 reg = <0x7000 0x100>;
285 st,bank-name = "PIO12"; 294 st,bank-name = "PIO12";
286 }; 295 };
287 PIO30: gpio@fee08000 { 296 pio30: gpio@fee08000 {
288 gpio-controller; 297 gpio-controller;
289 #gpio-cells = <1>; 298 #gpio-cells = <1>;
290 interrupt-controller; 299 interrupt-controller;
@@ -292,7 +301,7 @@
292 reg = <0x8000 0x100>; 301 reg = <0x8000 0x100>;
293 st,bank-name = "PIO30"; 302 st,bank-name = "PIO30";
294 }; 303 };
295 PIO31: gpio@fee09000 { 304 pio31: gpio@fee09000 {
296 gpio-controller; 305 gpio-controller;
297 #gpio-cells = <1>; 306 #gpio-cells = <1>;
298 interrupt-controller; 307 interrupt-controller;
@@ -304,7 +313,7 @@
304 serial2-oe { 313 serial2-oe {
305 pinctrl_serial2_oe: serial2-1 { 314 pinctrl_serial2_oe: serial2-1 {
306 st,pins { 315 st,pins {
307 output-enable = <&PIO11 3 ALT2 OUT>; 316 output-enable = <&pio11 3 ALT2 OUT>;
308 }; 317 };
309 }; 318 };
310 }; 319 };
@@ -312,17 +321,27 @@
312 i2c0 { 321 i2c0 {
313 pinctrl_i2c0_default: i2c0-default { 322 pinctrl_i2c0_default: i2c0-default {
314 st,pins { 323 st,pins {
315 sda = <&PIO9 3 ALT1 BIDIR>; 324 sda = <&pio9 3 ALT1 BIDIR>;
316 scl = <&PIO9 2 ALT1 BIDIR>; 325 scl = <&pio9 2 ALT1 BIDIR>;
326 };
327 };
328 };
329
330 usb {
331 pinctrl_usb0: usb0 {
332 st,pins {
333 oc-detect = <&pio9 4 ALT1 IN>;
334 pwr-enable = <&pio9 5 ALT1 OUT>;
317 }; 335 };
318 }; 336 };
319 }; 337 };
320 338
339
321 i2c1 { 340 i2c1 {
322 pinctrl_i2c1_default: i2c1-default { 341 pinctrl_i2c1_default: i2c1-default {
323 st,pins { 342 st,pins {
324 sda = <&PIO12 1 ALT1 BIDIR>; 343 sda = <&pio12 1 ALT1 BIDIR>;
325 scl = <&PIO12 0 ALT1 BIDIR>; 344 scl = <&pio12 0 ALT1 BIDIR>;
326 }; 345 };
327 }; 346 };
328 }; 347 };
@@ -330,12 +349,12 @@
330 fsm { 349 fsm {
331 pinctrl_fsm: fsm { 350 pinctrl_fsm: fsm {
332 st,pins { 351 st,pins {
333 spi-fsm-clk = <&PIO12 2 ALT1 OUT>; 352 spi-fsm-clk = <&pio12 2 ALT1 OUT>;
334 spi-fsm-cs = <&PIO12 3 ALT1 OUT>; 353 spi-fsm-cs = <&pio12 3 ALT1 OUT>;
335 spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; 354 spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
336 spi-fsm-miso = <&PIO12 5 ALT1 IN>; 355 spi-fsm-miso = <&pio12 5 ALT1 IN>;
337 spi-fsm-hol = <&PIO12 6 ALT1 OUT>; 356 spi-fsm-hol = <&pio12 6 ALT1 OUT>;
338 spi-fsm-wp = <&PIO12 7 ALT1 OUT>; 357 spi-fsm-wp = <&pio12 7 ALT1 OUT>;
339 }; 358 };
340 }; 359 };
341 }; 360 };
@@ -352,7 +371,7 @@
352 interrupt-names = "irqmux"; 371 interrupt-names = "irqmux";
353 ranges = <0 0xfe820000 0x6000>; 372 ranges = <0 0xfe820000 0x6000>;
354 373
355 PIO13: gpio@fe820000 { 374 pio13: gpio@fe820000 {
356 gpio-controller; 375 gpio-controller;
357 #gpio-cells = <1>; 376 #gpio-cells = <1>;
358 interrupt-controller; 377 interrupt-controller;
@@ -360,7 +379,7 @@
360 reg = <0 0x100>; 379 reg = <0 0x100>;
361 st,bank-name = "PIO13"; 380 st,bank-name = "PIO13";
362 }; 381 };
363 PIO14: gpio@fe821000 { 382 pio14: gpio@fe821000 {
364 gpio-controller; 383 gpio-controller;
365 #gpio-cells = <1>; 384 #gpio-cells = <1>;
366 interrupt-controller; 385 interrupt-controller;
@@ -368,7 +387,7 @@
368 reg = <0x1000 0x100>; 387 reg = <0x1000 0x100>;
369 st,bank-name = "PIO14"; 388 st,bank-name = "PIO14";
370 }; 389 };
371 PIO15: gpio@fe822000 { 390 pio15: gpio@fe822000 {
372 gpio-controller; 391 gpio-controller;
373 #gpio-cells = <1>; 392 #gpio-cells = <1>;
374 interrupt-controller; 393 interrupt-controller;
@@ -376,7 +395,7 @@
376 reg = <0x2000 0x100>; 395 reg = <0x2000 0x100>;
377 st,bank-name = "PIO15"; 396 st,bank-name = "PIO15";
378 }; 397 };
379 PIO16: gpio@fe823000 { 398 pio16: gpio@fe823000 {
380 gpio-controller; 399 gpio-controller;
381 #gpio-cells = <1>; 400 #gpio-cells = <1>;
382 interrupt-controller; 401 interrupt-controller;
@@ -384,7 +403,7 @@
384 reg = <0x3000 0x100>; 403 reg = <0x3000 0x100>;
385 st,bank-name = "PIO16"; 404 st,bank-name = "PIO16";
386 }; 405 };
387 PIO17: gpio@fe824000 { 406 pio17: gpio@fe824000 {
388 gpio-controller; 407 gpio-controller;
389 #gpio-cells = <1>; 408 #gpio-cells = <1>;
390 interrupt-controller; 409 interrupt-controller;
@@ -392,7 +411,7 @@
392 reg = <0x4000 0x100>; 411 reg = <0x4000 0x100>;
393 st,bank-name = "PIO17"; 412 st,bank-name = "PIO17";
394 }; 413 };
395 PIO18: gpio@fe825000 { 414 pio18: gpio@fe825000 {
396 gpio-controller; 415 gpio-controller;
397 #gpio-cells = <1>; 416 #gpio-cells = <1>;
398 interrupt-controller; 417 interrupt-controller;
@@ -405,8 +424,8 @@
405 serial2 { 424 serial2 {
406 pinctrl_serial2: serial2-0 { 425 pinctrl_serial2: serial2-0 {
407 st,pins { 426 st,pins {
408 tx = <&PIO17 4 ALT2 OUT>; 427 tx = <&pio17 4 ALT2 OUT>;
409 rx = <&PIO17 5 ALT2 IN>; 428 rx = <&pio17 5 ALT2 IN>;
410 }; 429 };
411 }; 430 };
412 }; 431 };
@@ -414,28 +433,28 @@
414 gmac0 { 433 gmac0 {
415 pinctrl_mii0: mii0 { 434 pinctrl_mii0: mii0 {
416 st,pins { 435 st,pins {
417 mdint = <&PIO13 6 ALT2 IN BYPASS 0>; 436 mdint = <&pio13 6 ALT2 IN BYPASS 0>;
418 txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 437 txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
419 txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 438 txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
420 txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 439 txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
421 txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 440 txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
422 txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; 441 txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
423 442
424 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 443 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
425 txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; 444 txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
426 crs = <&PIO15 2 ALT2 IN BYPASS 1000>; 445 crs = <&pio15 2 ALT2 IN BYPASS 1000>;
427 col = <&PIO15 3 ALT2 IN BYPASS 1000>; 446 col = <&pio15 3 ALT2 IN BYPASS 1000>;
428 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; 447 mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
429 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 448 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
430 449
431 rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; 450 rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
432 rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; 451 rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
433 rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; 452 rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
434 rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; 453 rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
435 rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; 454 rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
436 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; 455 rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
437 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 456 rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
438 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; 457 phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
439 }; 458 };
440 }; 459 };
441 460
@@ -445,25 +464,79 @@
445 }; 464 };
446 pinctrl_rgmii0: rgmii0 { 465 pinctrl_rgmii0: rgmii0 {
447 st,pins { 466 st,pins {
448 phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; 467 phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
449 txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; 468 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
450 txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; 469 txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
451 txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; 470 txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
452 txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; 471 txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
453 txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; 472 txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
454 txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; 473 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
455 474
456 mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; 475 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
457 mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; 476 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
458 477
459 rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; 478 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
460 rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; 479 rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
461 rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; 480 rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
462 rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; 481 rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
463 rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; 482 rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
464 rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; 483 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
465 484
466 clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; 485 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
486 };
487 };
488 };
489
490 mmc0 {
491 pinctrl_mmc0: mmc0 {
492 st,pins {
493 mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
494 data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>;
495 data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>;
496 data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>;
497 data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>;
498 cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>;
499 wp = <&pio15 3 ALT4 IN>;
500 data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>;
501 data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>;
502 data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>;
503 data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>;
504 pwr = <&pio17 1 ALT4 OUT>;
505 cd = <&pio17 2 ALT4 IN>;
506 led = <&pio17 3 ALT4 OUT>;
507 };
508 };
509 };
510 mmc1 {
511 pinctrl_mmc1: mmc1 {
512 st,pins {
513 mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>;
514 data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>;
515 data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>;
516 data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>;
517 data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>;
518 cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>;
519 data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>;
520 data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>;
521 data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>;
522 data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>;
523 pwr = <&pio16 2 ALT3 OUT>;
524 nreset = <&pio13 6 ALT3 OUT>;
525 };
526 };
527 };
528
529 usb {
530 pinctrl_usb1: usb1 {
531 st,pins {
532 oc-detect = <&pio18 0 ALT1 IN>;
533 pwr-enable = <&pio18 1 ALT1 OUT>;
534 };
535 };
536 pinctrl_usb2: usb2 {
537 st,pins {
538 oc-detect = <&pio18 2 ALT1 IN>;
539 pwr-enable = <&pio18 3 ALT1 OUT>;
467 }; 540 };
468 }; 541 };
469 }; 542 };
@@ -480,7 +553,7 @@
480 interrupt-names = "irqmux"; 553 interrupt-names = "irqmux";
481 ranges = <0 0xfd6b0000 0x3000>; 554 ranges = <0 0xfd6b0000 0x3000>;
482 555
483 PIO100: gpio@fd6b0000 { 556 pio100: gpio@fd6b0000 {
484 gpio-controller; 557 gpio-controller;
485 #gpio-cells = <1>; 558 #gpio-cells = <1>;
486 interrupt-controller; 559 interrupt-controller;
@@ -488,7 +561,7 @@
488 reg = <0 0x100>; 561 reg = <0 0x100>;
489 st,bank-name = "PIO100"; 562 st,bank-name = "PIO100";
490 }; 563 };
491 PIO101: gpio@fd6b1000 { 564 pio101: gpio@fd6b1000 {
492 gpio-controller; 565 gpio-controller;
493 #gpio-cells = <1>; 566 #gpio-cells = <1>;
494 interrupt-controller; 567 interrupt-controller;
@@ -496,7 +569,7 @@
496 reg = <0x1000 0x100>; 569 reg = <0x1000 0x100>;
497 st,bank-name = "PIO101"; 570 st,bank-name = "PIO101";
498 }; 571 };
499 PIO102: gpio@fd6b2000 { 572 pio102: gpio@fd6b2000 {
500 gpio-controller; 573 gpio-controller;
501 #gpio-cells = <1>; 574 #gpio-cells = <1>;
502 interrupt-controller; 575 interrupt-controller;
@@ -517,7 +590,7 @@
517 interrupt-names = "irqmux"; 590 interrupt-names = "irqmux";
518 ranges = <0 0xfd330000 0x5000>; 591 ranges = <0 0xfd330000 0x5000>;
519 592
520 PIO103: gpio@fd330000 { 593 pio103: gpio@fd330000 {
521 gpio-controller; 594 gpio-controller;
522 #gpio-cells = <1>; 595 #gpio-cells = <1>;
523 interrupt-controller; 596 interrupt-controller;
@@ -525,7 +598,7 @@
525 reg = <0 0x100>; 598 reg = <0 0x100>;
526 st,bank-name = "PIO103"; 599 st,bank-name = "PIO103";
527 }; 600 };
528 PIO104: gpio@fd331000 { 601 pio104: gpio@fd331000 {
529 gpio-controller; 602 gpio-controller;
530 #gpio-cells = <1>; 603 #gpio-cells = <1>;
531 interrupt-controller; 604 interrupt-controller;
@@ -533,7 +606,7 @@
533 reg = <0x1000 0x100>; 606 reg = <0x1000 0x100>;
534 st,bank-name = "PIO104"; 607 st,bank-name = "PIO104";
535 }; 608 };
536 PIO105: gpio@fd332000 { 609 pio105: gpio@fd332000 {
537 gpio-controller; 610 gpio-controller;
538 #gpio-cells = <1>; 611 #gpio-cells = <1>;
539 interrupt-controller; 612 interrupt-controller;
@@ -541,7 +614,7 @@
541 reg = <0x2000 0x100>; 614 reg = <0x2000 0x100>;
542 st,bank-name = "PIO105"; 615 st,bank-name = "PIO105";
543 }; 616 };
544 PIO106: gpio@fd333000 { 617 pio106: gpio@fd333000 {
545 gpio-controller; 618 gpio-controller;
546 #gpio-cells = <1>; 619 #gpio-cells = <1>;
547 interrupt-controller; 620 interrupt-controller;
@@ -550,7 +623,7 @@
550 st,bank-name = "PIO106"; 623 st,bank-name = "PIO106";
551 }; 624 };
552 625
553 PIO107: gpio@fd334000 { 626 pio107: gpio@fd334000 {
554 gpio-controller; 627 gpio-controller;
555 #gpio-cells = <1>; 628 #gpio-cells = <1>;
556 interrupt-controller; 629 interrupt-controller;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 84758d76d064..fad9073ddeed 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
9#include "stih41x.dtsi" 9#include "stih41x.dtsi"
10#include "stih416-clock.dtsi" 10#include "stih416-clock.dtsi"
11#include "stih416-pinctrl.dtsi" 11#include "stih416-pinctrl.dtsi"
12
13#include <dt-bindings/phy/phy-miphy365x.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset-controller/stih416-resets.h> 15#include <dt-bindings/reset-controller/stih416-resets.h>
14/ { 16/ {
@@ -236,5 +238,212 @@
236 resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, 238 resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
237 <&softreset STIH416_KEYSCAN_SOFTRESET>; 239 <&softreset STIH416_KEYSCAN_SOFTRESET>;
238 }; 240 };
241
242 temp0 {
243 compatible = "st,stih416-sas-thermal";
244 clock-names = "thermal";
245 clocks = <&clockgen_c_vcc 14>;
246
247 status = "okay";
248 };
249
250 temp1@fdfe8000 {
251 compatible = "st,stih416-mpe-thermal";
252 reg = <0xfdfe8000 0x10>;
253 clocks = <&clockgen_e 3>;
254 clock-names = "thermal";
255 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
256
257 status = "okay";
258 };
259
260 mmc0: sdhci@fe81e000 {
261 compatible = "st,sdhci";
262 status = "disabled";
263 reg = <0xfe81e000 0x1000>;
264 interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
265 interrupt-names = "mmcirq";
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_mmc0>;
268 clock-names = "mmc";
269 clocks = <&clk_s_a1_ls 1>;
270 };
271
272 mmc1: sdhci@fe81f000 {
273 compatible = "st,sdhci";
274 status = "disabled";
275 reg = <0xfe81f000 0x1000>;
276 interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
277 interrupt-names = "mmcirq";
278 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_mmc1>;
280 clock-names = "mmc";
281 clocks = <&clk_s_a1_ls 8>;
282 };
283
284 miphy365x_phy: phy@fe382000 {
285 compatible = "st,miphy365x-phy";
286 st,syscfg = <&syscfg_rear>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
290
291 phy_port0: port@fe382000 {
292 #phy-cells = <1>;
293 reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
294 reg-names = "sata", "pcie", "syscfg";
295 };
296
297 phy_port1: port@fe38a000 {
298 #phy-cells = <1>;
299 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
300 reg-names = "sata", "pcie", "syscfg";
301 };
302 };
303
304 sata0: sata@fe380000 {
305 compatible = "st,sti-ahci";
306 reg = <0xfe380000 0x1000>;
307 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
308 interrupt-names = "hostc";
309 phys = <&phy_port0 MIPHY_TYPE_SATA>;
310 phy-names = "sata-phy";
311 resets = <&powerdown STIH416_SATA0_POWERDOWN>,
312 <&softreset STIH416_SATA0_SOFTRESET>;
313 reset-names = "pwr-dwn", "sw-rst";
314 clock-names = "ahci_clk";
315 clocks = <&clk_s_a0_ls CLK_ICN_REG>;
316
317 status = "disabled";
318 };
319
320 usb2_phy: phy@0 {
321 compatible = "st,stih416-usb-phy";
322 #phy-cells = <0>;
323 st,syscfg = <&syscfg_rear>;
324 clocks = <&clk_sysin>;
325 clock-names = "osc_phy";
326 };
327
328 ehci0: usb@fe1ffe00 {
329 compatible = "st,st-ehci-300x";
330 reg = <0xfe1ffe00 0x100>;
331 interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usb0>;
334 clocks = <&clk_s_a1_ls 0>,
335 <&clockgen_b0 0>;
336 clock-names = "ic", "clk48";
337 phys = <&usb2_phy>;
338 phy-names = "usb";
339 resets = <&powerdown STIH416_USB0_POWERDOWN>,
340 <&softreset STIH416_USB0_SOFTRESET>;
341 reset-names = "power", "softreset";
342 };
343
344 ohci0: usb@fe1ffc00 {
345 compatible = "st,st-ohci-300x";
346 reg = <0xfe1ffc00 0x100>;
347 interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
348 clocks = <&clk_s_a1_ls 0>,
349 <&clockgen_b0 0>;
350 clock-names = "ic", "clk48";
351 phys = <&usb2_phy>;
352 phy-names = "usb";
353 status = "okay";
354 resets = <&powerdown STIH416_USB0_POWERDOWN>,
355 <&softreset STIH416_USB0_SOFTRESET>;
356 reset-names = "power", "softreset";
357 };
358
359 ehci1: usb@fe203e00 {
360 compatible = "st,st-ehci-300x";
361 reg = <0xfe203e00 0x100>;
362 interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_usb1>;
365 clocks = <&clk_s_a1_ls 0>,
366 <&clockgen_b0 0>;
367 clock-names = "ic", "clk48";
368 phys = <&usb2_phy>;
369 phy-names = "usb";
370 resets = <&powerdown STIH416_USB1_POWERDOWN>,
371 <&softreset STIH416_USB1_SOFTRESET>;
372 reset-names = "power", "softreset";
373 };
374
375 ohci1: usb@fe203c00 {
376 compatible = "st,st-ohci-300x";
377 reg = <0xfe203c00 0x100>;
378 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
379 clocks = <&clk_s_a1_ls 0>,
380 <&clockgen_b0 0>;
381 clock-names = "ic", "clk48";
382 phys = <&usb2_phy>;
383 phy-names = "usb";
384 resets = <&powerdown STIH416_USB1_POWERDOWN>,
385 <&softreset STIH416_USB1_SOFTRESET>;
386 reset-names = "power", "softreset";
387 };
388
389 ehci2: usb@fe303e00 {
390 compatible = "st,st-ehci-300x";
391 reg = <0xfe303e00 0x100>;
392 interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_usb2>;
395 clocks = <&clk_s_a1_ls 0>,
396 <&clockgen_b0 0>;
397 clock-names = "ic", "clk48";
398 phys = <&usb2_phy>;
399 phy-names = "usb";
400 resets = <&powerdown STIH416_USB2_POWERDOWN>,
401 <&softreset STIH416_USB2_SOFTRESET>;
402 reset-names = "power", "softreset";
403 };
404
405 ohci2: usb@fe303c00 {
406 compatible = "st,st-ohci-300x";
407 reg = <0xfe303c00 0x100>;
408 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
409 clocks = <&clk_s_a1_ls 0>,
410 <&clockgen_b0 0>;
411 clock-names = "ic", "clk48";
412 phys = <&usb2_phy>;
413 phy-names = "usb";
414 resets = <&powerdown STIH416_USB2_POWERDOWN>,
415 <&softreset STIH416_USB2_SOFTRESET>;
416 reset-names = "power", "softreset";
417 };
418
419 ehci3: usb@fe343e00 {
420 compatible = "st,st-ehci-300x";
421 reg = <0xfe343e00 0x100>;
422 interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_usb3>;
425 clocks = <&clk_s_a1_ls 0>,
426 <&clockgen_b0 0>;
427 clock-names = "ic", "clk48";
428 phys = <&usb2_phy>;
429 phy-names = "usb";
430 resets = <&powerdown STIH416_USB3_POWERDOWN>,
431 <&softreset STIH416_USB3_SOFTRESET>;
432 reset-names = "power", "softreset";
433 };
434
435 ohci3: usb@fe343c00 {
436 compatible = "st,st-ohci-300x";
437 reg = <0xfe343c00 0x100>;
438 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
439 clocks = <&clk_s_a1_ls 0>,
440 <&clockgen_b0 0>;
441 clock-names = "ic", "clk48";
442 phys = <&usb2_phy>;
443 phy-names = "usb";
444 resets = <&powerdown STIH416_USB3_POWERDOWN>,
445 <&softreset STIH416_USB3_SOFTRESET>;
446 reset-names = "power", "softreset";
447 };
239 }; 448 };
240}; 449};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index b3dd6ca5c2ae..5f91f455f05b 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -35,7 +35,7 @@
35 fp_led { 35 fp_led {
36 #gpio-cells = <1>; 36 #gpio-cells = <1>;
37 label = "Front Panel LED"; 37 label = "Front Panel LED";
38 gpios = <&PIO105 7>; 38 gpios = <&pio105 7>;
39 linux,default-trigger = "heartbeat"; 39 linux,default-trigger = "heartbeat";
40 }; 40 };
41 }; 41 };
@@ -55,7 +55,7 @@
55 phy-mode = "mii"; 55 phy-mode = "mii";
56 pinctrl-0 = <&pinctrl_mii0>; 56 pinctrl-0 = <&pinctrl_mii0>;
57 57
58 snps,reset-gpio = <&PIO106 2>; 58 snps,reset-gpio = <&pio106 2>;
59 snps,reset-active-low; 59 snps,reset-active-low;
60 snps,reset-delays-us = <0 10000 10000>; 60 snps,reset-delays-us = <0 10000 10000>;
61 }; 61 };
@@ -65,7 +65,7 @@
65 phy-mode = "mii"; 65 phy-mode = "mii";
66 st,tx-retime-src = "txclk"; 66 st,tx-retime-src = "txclk";
67 67
68 snps,reset-gpio = <&PIO4 7>; 68 snps,reset-gpio = <&pio4 7>;
69 snps,reset-active-low; 69 snps,reset-active-low;
70 snps,reset-delays-us = <0 10000 10000>; 70 snps,reset-delays-us = <0 10000 10000>;
71 }; 71 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index d8a84295c328..487d7d87dbef 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -32,11 +32,11 @@
32 red { 32 red {
33 #gpio-cells = <1>; 33 #gpio-cells = <1>;
34 label = "Front Panel LED"; 34 label = "Front Panel LED";
35 gpios = <&PIO4 1>; 35 gpios = <&pio4 1>;
36 linux,default-trigger = "heartbeat"; 36 linux,default-trigger = "heartbeat";
37 }; 37 };
38 green { 38 green {
39 gpios = <&PIO4 7>; 39 gpios = <&pio4 7>;
40 default-state = "off"; 40 default-state = "off";
41 }; 41 };
42 }; 42 };
@@ -68,11 +68,15 @@
68 phy-mode = "rgmii-id"; 68 phy-mode = "rgmii-id";
69 max-speed = <1000>; 69 max-speed = <1000>;
70 st,tx-retime-src = "clk_125"; 70 st,tx-retime-src = "clk_125";
71 snps,reset-gpio = <&PIO3 0>; 71 snps,reset-gpio = <&pio3 0>;
72 snps,reset-active-low; 72 snps,reset-active-low;
73 snps,reset-delays-us = <0 10000 10000>; 73 snps,reset-delays-us = <0 10000 10000>;
74 74
75 pinctrl-0 = <&pinctrl_rgmii1>; 75 pinctrl-0 = <&pinctrl_rgmii1>;
76 }; 76 };
77
78 mmc0: sdhci@fe81e000 {
79 bus-width = <8>;
80 };
77 }; 81 };
78}; 82};
diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi
index df01c1211b32..f797a0607382 100644
--- a/arch/arm/boot/dts/stih41x-b2020x.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi
@@ -8,6 +8,10 @@
8 */ 8 */
9/ { 9/ {
10 soc { 10 soc {
11 mmc0: sdhci@fe81e000 {
12 status = "okay";
13 };
14
11 spifsm: spifsm@fe902000 { 15 spifsm: spifsm@fe902000 {
12 #address-cells = <1>; 16 #address-cells = <1>;
13 #size-cells = <1>; 17 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 000000000000..0074bd49797c
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9/ {
10 soc {
11 sbc_serial0: serial@9530000 {
12 status = "okay";
13 };
14
15 leds {
16 compatible = "gpio-leds";
17 red {
18 #gpio-cells = <2>;
19 label = "Front Panel LED";
20 gpios = <&pio4 1 0>;
21 linux,default-trigger = "heartbeat";
22 };
23 green {
24 #gpio-cells = <2>;
25 gpios = <&pio1 3 0>;
26 default-state = "off";
27 };
28 };
29
30 i2c@9842000 {
31 status = "okay";
32 };
33
34 i2c@9843000 {
35 status = "okay";
36 };
37
38 i2c@9844000 {
39 status = "okay";
40 };
41
42 i2c@9845000 {
43 status = "okay";
44 };
45
46 i2c@9540000 {
47 status = "okay";
48 };
49
50 /* SSC11 to HDMI */
51 i2c@9541000 {
52 status = "okay";
53 /* HDMI V1.3a supports Standard mode only */
54 clock-frequency = <100000>;
55 st,i2c-min-scl-pulse-width-us = <0>;
56 st,i2c-min-sda-pulse-width-us = <5>;
57 };
58 };
59};
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 9e99ade35e37..3bcfd81837f0 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Emilio López <emilio@elopez.com.ar> 4 * Emilio López <emilio@elopez.com.ar>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
index 1763cc7ec023..f3f2974658e4 100644
--- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 3ce56bfbc0b5..6a310da53f18 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -2,12 +2,48 @@
2 * Copyright 2012 Stefan Roese 2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de> 3 * Stefan Roese <sr@denx.de>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 891ea446abae..efc116287e0f 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index 6b0c37812ade..3e25ee4d3248 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * David Lanzendörfer <david.lanzendoerfer@o2s.ch> 4 * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index b9ecce60f2e7..8b3f97470249 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index d046d568f5a1..88cf1a531155 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 6675bcd7860e..ce5994597407 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -2,12 +2,48 @@
2 * Copyright 2014 Zoltan HERPAI 2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu> 3 * Zoltan HERPAI <wigyori@uid0.hu>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 380f914b226d..e3ab942fd148 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -27,6 +27,20 @@
27 serial7 = &uart7; 27 serial7 = &uart7;
28 }; 28 };
29 29
30 chosen {
31 #address-cells = <1>;
32 #size-cells = <1>;
33 ranges;
34
35 framebuffer@0 {
36 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
37 allwinner,pipeline = "de_be0-lcd0-hdmi";
38 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
39 <&ahb_gates 44>;
40 status = "disabled";
41 };
42 };
43
30 cpus { 44 cpus {
31 #address-cells = <1>; 45 #address-cells = <1>;
32 #size-cells = <0>; 46 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index ea9519da5764..fe3c559ca6a8 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
index 43a93762d4f2..1fa2916eafc2 100644
--- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 531272c0e526..81ad4b94e812 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -24,6 +24,20 @@
24 serial3 = &uart3; 24 serial3 = &uart3;
25 }; 25 };
26 26
27 chosen {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges;
31
32 framebuffer@0 {
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
36 <&ahb_gates 44>;
37 status = "disabled";
38 };
39 };
40
27 cpus { 41 cpus {
28 cpu@0 { 42 cpu@0 {
29 compatible = "arm,cortex-a8"; 43 compatible = "arm,cortex-a8";
diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
index 8b3cd0907b32..eeed1f236ee8 100644
--- a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts
@@ -6,18 +6,18 @@
6 * licensing only applies to this file, and not this project as a 6 * licensing only applies to this file, and not this project as a
7 * whole. 7 * whole.
8 * 8 *
9 * a) This library is free software; you can redistribute it and/or 9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the 11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version. 12 * License, or (at your option) any later version.
13 * 13 *
14 * This library is distributed in the hope that it will be useful, 14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public 19 * You should have received a copy of the GNU General Public
20 * License along with this library; if not, write to the Free 20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA 22 * MA 02110-1301 USA
23 * 23 *
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fa44b026483b..916ee8bb826f 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -1,15 +1,49 @@
1/* 1/*
2 * Copyright 2012 Maxime Ripard 2 * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
3 * Copyright 2013 Hans de Goede <hdegoede@redhat.com> 3 * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
4 * 4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
6 * 9 *
7 * The code contained herein is licensed under the GNU General Public 10 * a) This file is free software; you can redistribute it and/or
8 * License. You may obtain a copy of the GNU General Public License 11 * modify it under the terms of the GNU General Public License as
9 * Version 2 or later at the following locations: 12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
10 * 14 *
11 * http://www.opensource.org/licenses/gpl-license.html 15 * This file is distributed in the hope that it will be useful,
12 * http://www.gnu.org/copyleft/gpl.html 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 47 */
14 48
15/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 429994e1943e..e31d291d14cb 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
index 2bbf8867362b..c74a63a39531 100644
--- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Boris Brezillon <boris.brezillon@free-electrons.com> 4 * Boris Brezillon <boris.brezillon@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 546cf6eff5c7..c36b4dc89c13 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
index f142065b3c1f..6e924d9d2912 100644
--- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com> 4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index bc6115da5ae1..3ab544f3af4a 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
@@ -32,13 +68,40 @@
32 status = "okay"; 68 status = "okay";
33 }; 69 };
34 70
71 usbphy: phy@01c19400 {
72 usb1_vbus-supply = <&reg_usb1_vbus>;
73 status = "okay";
74 };
75
76 ehci0: usb@01c1a000 {
77 status = "okay";
78 };
79
80 ehci1: usb@01c1b000 {
81 status = "okay";
82 };
83
35 pio: pinctrl@01c20800 { 84 pio: pinctrl@01c20800 {
85 led_pins_m9: led_pins@0 {
86 allwinner,pins = "PH13";
87 allwinner,function = "gpio_out";
88 allwinner,drive = <0>;
89 allwinner,pull = <0>;
90 };
91
36 mmc0_cd_pin_m9: mmc0_cd_pin@0 { 92 mmc0_cd_pin_m9: mmc0_cd_pin@0 {
37 allwinner,pins = "PH22"; 93 allwinner,pins = "PH22";
38 allwinner,function = "gpio_in"; 94 allwinner,function = "gpio_in";
39 allwinner,drive = <0>; 95 allwinner,drive = <0>;
40 allwinner,pull = <1>; 96 allwinner,pull = <1>;
41 }; 97 };
98
99 usb1_vbus_pin_m9: usb1_vbus_pin@0 {
100 allwinner,pins = "PC27";
101 allwinner,function = "gpio_out";
102 allwinner,drive = <0>;
103 allwinner,pull = <0>;
104 };
42 }; 105 };
43 106
44 uart0: serial@01c28000 { 107 uart0: serial@01c28000 {
@@ -46,5 +109,35 @@
46 pinctrl-0 = <&uart0_pins_a>; 109 pinctrl-0 = <&uart0_pins_a>;
47 status = "okay"; 110 status = "okay";
48 }; 111 };
112
113 gmac: ethernet@01c30000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&gmac_pins_mii_a>;
116 phy = <&phy1>;
117 phy-mode = "mii";
118 status = "okay";
119
120 phy1: ethernet-phy@1 {
121 reg = <1>;
122 };
123 };
124 };
125
126 leds {
127 compatible = "gpio-leds";
128 pinctrl-names = "default";
129 pinctrl-0 = <&led_pins_m9>;
130
131 blue {
132 label = "m9:blue:usr";
133 gpios = <&pio 7 13 0>;
134 };
135 };
136
137 reg_usb1_vbus: usb1-vbus {
138 pinctrl-names = "default";
139 pinctrl-0 = <&usb1_vbus_pin_m9>;
140 gpio = <&pio 2 27 0>;
141 status = "okay";
49 }; 142 };
50}; 143};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 2e652e2339e9..a400172a8a52 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
@@ -62,6 +62,18 @@
62 ethernet0 = &gmac; 62 ethernet0 = &gmac;
63 }; 63 };
64 64
65 chosen {
66 #address-cells = <1>;
67 #size-cells = <1>;
68 ranges;
69
70 framebuffer@0 {
71 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
72 allwinner,pipeline = "de_be0-lcd0-hdmi";
73 clocks = <&pll6 0>;
74 status = "disabled";
75 };
76 };
65 77
66 cpus { 78 cpus {
67 enable-method = "allwinner,sun6i-a31"; 79 enable-method = "allwinner,sun6i-a31";
@@ -132,11 +144,11 @@
132 }; 144 };
133 145
134 pll6: clk@01c20028 { 146 pll6: clk@01c20028 {
135 #clock-cells = <0>; 147 #clock-cells = <1>;
136 compatible = "allwinner,sun6i-a31-pll6-clk"; 148 compatible = "allwinner,sun6i-a31-pll6-clk";
137 reg = <0x01c20028 0x4>; 149 reg = <0x01c20028 0x4>;
138 clocks = <&osc24M>; 150 clocks = <&osc24M>;
139 clock-output-names = "pll6"; 151 clock-output-names = "pll6", "pll6x2";
140 }; 152 };
141 153
142 cpu: cpu@01c20050 { 154 cpu: cpu@01c20050 {
@@ -166,7 +178,7 @@
166 #clock-cells = <0>; 178 #clock-cells = <0>;
167 compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; 179 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
168 reg = <0x01c20054 0x4>; 180 reg = <0x01c20054 0x4>;
169 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; 181 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
170 clock-output-names = "ahb1_mux"; 182 clock-output-names = "ahb1_mux";
171 }; 183 };
172 184
@@ -221,7 +233,7 @@
221 #clock-cells = <0>; 233 #clock-cells = <0>;
222 compatible = "allwinner,sun4i-a10-apb1-mux-clk"; 234 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
223 reg = <0x01c20058 0x4>; 235 reg = <0x01c20058 0x4>;
224 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 236 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
225 clock-output-names = "apb2_mux"; 237 clock-output-names = "apb2_mux";
226 }; 238 };
227 239
@@ -248,7 +260,7 @@
248 #clock-cells = <0>; 260 #clock-cells = <0>;
249 compatible = "allwinner,sun4i-a10-mod0-clk"; 261 compatible = "allwinner,sun4i-a10-mod0-clk";
250 reg = <0x01c20088 0x4>; 262 reg = <0x01c20088 0x4>;
251 clocks = <&osc24M>, <&pll6>; 263 clocks = <&osc24M>, <&pll6 0>;
252 clock-output-names = "mmc0"; 264 clock-output-names = "mmc0";
253 }; 265 };
254 266
@@ -256,7 +268,7 @@
256 #clock-cells = <0>; 268 #clock-cells = <0>;
257 compatible = "allwinner,sun4i-a10-mod0-clk"; 269 compatible = "allwinner,sun4i-a10-mod0-clk";
258 reg = <0x01c2008c 0x4>; 270 reg = <0x01c2008c 0x4>;
259 clocks = <&osc24M>, <&pll6>; 271 clocks = <&osc24M>, <&pll6 0>;
260 clock-output-names = "mmc1"; 272 clock-output-names = "mmc1";
261 }; 273 };
262 274
@@ -264,7 +276,7 @@
264 #clock-cells = <0>; 276 #clock-cells = <0>;
265 compatible = "allwinner,sun4i-a10-mod0-clk"; 277 compatible = "allwinner,sun4i-a10-mod0-clk";
266 reg = <0x01c20090 0x4>; 278 reg = <0x01c20090 0x4>;
267 clocks = <&osc24M>, <&pll6>; 279 clocks = <&osc24M>, <&pll6 0>;
268 clock-output-names = "mmc2"; 280 clock-output-names = "mmc2";
269 }; 281 };
270 282
@@ -272,7 +284,7 @@
272 #clock-cells = <0>; 284 #clock-cells = <0>;
273 compatible = "allwinner,sun4i-a10-mod0-clk"; 285 compatible = "allwinner,sun4i-a10-mod0-clk";
274 reg = <0x01c20094 0x4>; 286 reg = <0x01c20094 0x4>;
275 clocks = <&osc24M>, <&pll6>; 287 clocks = <&osc24M>, <&pll6 0>;
276 clock-output-names = "mmc3"; 288 clock-output-names = "mmc3";
277 }; 289 };
278 290
@@ -280,7 +292,7 @@
280 #clock-cells = <0>; 292 #clock-cells = <0>;
281 compatible = "allwinner,sun4i-a10-mod0-clk"; 293 compatible = "allwinner,sun4i-a10-mod0-clk";
282 reg = <0x01c200a0 0x4>; 294 reg = <0x01c200a0 0x4>;
283 clocks = <&osc24M>, <&pll6>; 295 clocks = <&osc24M>, <&pll6 0>;
284 clock-output-names = "spi0"; 296 clock-output-names = "spi0";
285 }; 297 };
286 298
@@ -288,7 +300,7 @@
288 #clock-cells = <0>; 300 #clock-cells = <0>;
289 compatible = "allwinner,sun4i-a10-mod0-clk"; 301 compatible = "allwinner,sun4i-a10-mod0-clk";
290 reg = <0x01c200a4 0x4>; 302 reg = <0x01c200a4 0x4>;
291 clocks = <&osc24M>, <&pll6>; 303 clocks = <&osc24M>, <&pll6 0>;
292 clock-output-names = "spi1"; 304 clock-output-names = "spi1";
293 }; 305 };
294 306
@@ -296,7 +308,7 @@
296 #clock-cells = <0>; 308 #clock-cells = <0>;
297 compatible = "allwinner,sun4i-a10-mod0-clk"; 309 compatible = "allwinner,sun4i-a10-mod0-clk";
298 reg = <0x01c200a8 0x4>; 310 reg = <0x01c200a8 0x4>;
299 clocks = <&osc24M>, <&pll6>; 311 clocks = <&osc24M>, <&pll6 0>;
300 clock-output-names = "spi2"; 312 clock-output-names = "spi2";
301 }; 313 };
302 314
@@ -304,7 +316,7 @@
304 #clock-cells = <0>; 316 #clock-cells = <0>;
305 compatible = "allwinner,sun4i-a10-mod0-clk"; 317 compatible = "allwinner,sun4i-a10-mod0-clk";
306 reg = <0x01c200ac 0x4>; 318 reg = <0x01c200ac 0x4>;
307 clocks = <&osc24M>, <&pll6>; 319 clocks = <&osc24M>, <&pll6 0>;
308 clock-output-names = "spi3"; 320 clock-output-names = "spi3";
309 }; 321 };
310 322
@@ -364,7 +376,7 @@
364 376
365 /* DMA controller requires AHB1 clocked from PLL6 */ 377 /* DMA controller requires AHB1 clocked from PLL6 */
366 assigned-clocks = <&ahb1_mux>; 378 assigned-clocks = <&ahb1_mux>;
367 assigned-clock-parents = <&pll6>; 379 assigned-clock-parents = <&pll6 0>;
368 }; 380 };
369 381
370 mmc0: mmc@01c0f000 { 382 mmc0: mmc@01c0f000 {
@@ -844,7 +856,7 @@
844 ar100: ar100_clk { 856 ar100: ar100_clk {
845 compatible = "allwinner,sun6i-a31-ar100-clk"; 857 compatible = "allwinner,sun6i-a31-ar100-clk";
846 #clock-cells = <0>; 858 #clock-cells = <0>;
847 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; 859 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
848 clock-output-names = "ar100"; 860 clock-output-names = "ar100";
849 }; 861 };
850 862
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
new file mode 100644
index 000000000000..1cf1214cc068
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts
@@ -0,0 +1,214 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * Hans de Goede <hdegoede@redhat.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi"
53
54/ {
55 model = "LeMaker Banana Pi";
56 compatible = "lemaker,bananapi", "allwinner,sun7i-a20";
57
58 soc@01c00000 {
59 spi0: spi@01c05000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&spi0_pins_a>;
62 status = "okay";
63 };
64
65 mmc0: mmc@01c0f000 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>;
68 vmmc-supply = <&reg_vcc3v3>;
69 bus-width = <4>;
70 cd-gpios = <&pio 7 10 0>; /* PH10 */
71 cd-inverted;
72 status = "okay";
73 };
74
75 usbphy: phy@01c13400 {
76 usb1_vbus-supply = <&reg_usb1_vbus>;
77 usb2_vbus-supply = <&reg_usb2_vbus>;
78 status = "okay";
79 };
80
81 ehci0: usb@01c14000 {
82 status = "okay";
83 };
84
85 ohci0: usb@01c14400 {
86 status = "okay";
87 };
88
89 ahci: sata@01c18000 {
90 status = "okay";
91 };
92
93 ehci1: usb@01c1c000 {
94 status = "okay";
95 };
96
97 ohci1: usb@01c1c400 {
98 status = "okay";
99 };
100
101 pinctrl@01c20800 {
102 mmc0_cd_pin_bananapi: mmc0_cd_pin@0 {
103 allwinner,pins = "PH10";
104 allwinner,function = "gpio_in";
105 allwinner,drive = <0>;
106 allwinner,pull = <1>;
107 };
108
109 gmac_power_pin_bananapi: gmac_power_pin@0 {
110 allwinner,pins = "PH23";
111 allwinner,function = "gpio_out";
112 allwinner,drive = <0>;
113 allwinner,pull = <0>;
114 };
115
116 led_pins_bananapi: led_pins@0 {
117 allwinner,pins = "PH24";
118 allwinner,function = "gpio_out";
119 allwinner,drive = <0>;
120 allwinner,pull = <0>;
121 };
122 };
123
124 ir0: ir@01c21800 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&ir0_pins_a>;
127 status = "okay";
128 };
129
130 uart0: serial@01c28000 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&uart0_pins_a>;
133 status = "okay";
134 };
135
136 uart3: serial@01c28c00 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&uart3_pins_b>;
139 status = "okay";
140 };
141
142 uart7: serial@01c29c00 {
143 pinctrl-names = "default";
144 pinctrl-0 = <&uart7_pins_a>;
145 status = "okay";
146 };
147
148 i2c0: i2c@01c2ac00 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&i2c0_pins_a>;
151 status = "okay";
152
153 axp209: pmic@34 {
154 compatible = "x-powers,axp209";
155 reg = <0x34>;
156 interrupt-parent = <&nmi_intc>;
157 interrupts = <0 8>;
158
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 };
162 };
163
164 i2c2: i2c@01c2b400 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&i2c2_pins_a>;
167 status = "okay";
168 };
169
170 gmac: ethernet@01c50000 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&gmac_pins_rgmii_a>;
173 phy = <&phy1>;
174 phy-mode = "rgmii";
175 phy-supply = <&reg_gmac_3v3>;
176 status = "okay";
177
178 phy1: ethernet-phy@1 {
179 reg = <1>;
180 };
181 };
182 };
183
184 leds {
185 compatible = "gpio-leds";
186 pinctrl-names = "default";
187 pinctrl-0 = <&led_pins_bananapi>;
188
189 green {
190 label = "bananapi:green:usr";
191 gpios = <&pio 7 24 0>;
192 };
193 };
194
195 reg_usb1_vbus: usb1-vbus {
196 status = "okay";
197 };
198
199 reg_usb2_vbus: usb2-vbus {
200 status = "okay";
201 };
202
203 reg_gmac_3v3: gmac-3v3 {
204 compatible = "regulator-fixed";
205 pinctrl-names = "default";
206 pinctrl-0 = <&gmac_power_pin_bananapi>;
207 regulator-name = "gmac-3v3";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 startup-delay-us = <100000>;
211 enable-active-high;
212 gpio = <&pio 7 23 0>;
213 };
214};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c717bc..a281d259b9b8 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -40,6 +40,7 @@
40 }; 40 };
41 41
42 usbphy: phy@01c13400 { 42 usbphy: phy@01c13400 {
43 usb0_vbus-supply = <&reg_usb0_vbus>;
43 usb1_vbus-supply = <&reg_usb1_vbus>; 44 usb1_vbus-supply = <&reg_usb1_vbus>;
44 usb2_vbus-supply = <&reg_usb2_vbus>; 45 usb2_vbus-supply = <&reg_usb2_vbus>;
45 status = "okay"; 46 status = "okay";
@@ -92,6 +93,13 @@
92 allwinner,drive = <0>; 93 allwinner,drive = <0>;
93 allwinner,pull = <0>; 94 allwinner,pull = <0>;
94 }; 95 };
96
97 usb0_vbus_pin_a: usb0_vbus_pin@0 {
98 allwinner,pins = "PH17";
99 allwinner,function = "gpio_out";
100 allwinner,drive = <0>;
101 allwinner,pull = <0>;
102 };
95 }; 103 };
96 104
97 pwm: pwm@01c20e00 { 105 pwm: pwm@01c20e00 {
@@ -185,6 +193,12 @@
185 status = "okay"; 193 status = "okay";
186 }; 194 };
187 195
196 reg_usb0_vbus: usb0-vbus {
197 pinctrl-0 = <&usb0_vbus_pin_a>;
198 gpio = <&pio 7 17 0>;
199 status = "okay";
200 };
201
188 reg_usb1_vbus: usb1-vbus { 202 reg_usb1_vbus: usb1-vbus {
189 status = "okay"; 203 status = "okay";
190 }; 204 };
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index 6a67712d417a..f38bb1a6656c 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -1,12 +1,48 @@
1/* 1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com> 2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * This file is dual-licensed: you can use it either under the terms
5 * License. You may obtain a copy of the GNU General Public License 5 * of the GPL or the X11 license, at your option. Note that this dual
6 * Version 2 or later at the following locations: 6 * licensing only applies to this file, and not this project as a
7 * whole.
7 * 8 *
8 * http://www.opensource.org/licenses/gpl-license.html 9 * a) This file is free software; you can redistribute it and/or
9 * http://www.gnu.org/copyleft/gpl.html 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12/dts-v1/; 48/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts
new file mode 100644
index 000000000000..b8e568c55271
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
@@ -0,0 +1,168 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * Hans de Goede <hdegoede@redhat.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun7i-a20.dtsi"
52/include/ "sunxi-common-regulators.dtsi"
53
54/ {
55 model = "Mele M3";
56 compatible = "mele,m3", "allwinner,sun7i-a20";
57
58 soc@01c00000 {
59 mmc0: mmc@01c0f000 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
62 vmmc-supply = <&reg_vcc3v3>;
63 bus-width = <4>;
64 cd-gpios = <&pio 7 1 0>; /* PH1 */
65 cd-inverted;
66 status = "okay";
67 };
68
69 mmc2: mmc@01c11000 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&mmc2_pins_a>;
72 vmmc-supply = <&reg_vcc3v3>;
73 bus-width = <4>;
74 non-removable;
75 status = "okay";
76 };
77
78 usbphy: phy@01c13400 {
79 usb1_vbus-supply = <&reg_usb1_vbus>;
80 usb2_vbus-supply = <&reg_usb2_vbus>;
81 status = "okay";
82 };
83
84 ehci0: usb@01c14000 {
85 status = "okay";
86 };
87
88 ohci0: usb@01c14400 {
89 status = "okay";
90 };
91
92 ehci1: usb@01c1c000 {
93 status = "okay";
94 };
95
96 ohci1: usb@01c1c400 {
97 status = "okay";
98 };
99
100 pinctrl@01c20800 {
101 led_pins_m3: led_pins@0 {
102 allwinner,pins = "PH20";
103 allwinner,function = "gpio_out";
104 allwinner,drive = <0>;
105 allwinner,pull = <0>;
106 };
107 };
108
109 ir0: ir@01c21800 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&ir0_pins_a>;
112 status = "okay";
113 };
114
115 uart0: serial@01c28000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&uart0_pins_a>;
118 status = "okay";
119 };
120
121 i2c0: i2c@01c2ac00 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c0_pins_a>;
124 status = "okay";
125
126 axp209: pmic@34 {
127 compatible = "x-powers,axp209";
128 reg = <0x34>;
129 interrupt-parent = <&nmi_intc>;
130 interrupts = <0 8>;
131
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 };
135 };
136
137 gmac: ethernet@01c50000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&gmac_pins_mii_a>;
140 phy = <&phy1>;
141 phy-mode = "mii";
142 status = "okay";
143
144 phy1: ethernet-phy@1 {
145 reg = <1>;
146 };
147 };
148 };
149
150 leds {
151 compatible = "gpio-leds";
152 pinctrl-names = "default";
153 pinctrl-0 = <&led_pins_m3>;
154
155 blue {
156 label = "m3:blue:usr";
157 gpios = <&pio 7 20 0>;
158 };
159 };
160
161 reg_usb1_vbus: usb1-vbus {
162 status = "okay";
163 };
164
165 reg_usb2_vbus: usb2-vbus {
166 status = "okay";
167 };
168};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
index 1eb8175959a6..3f3ff9693992 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
@@ -4,12 +4,48 @@
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com> 5 * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com>
6 * 6 *
7 * The code contained herein is licensed under the GNU General Public 7 * This file is dual-licensed: you can use it either under the terms
8 * License. You may obtain a copy of the GNU General Public License 8 * of the GPL or the X11 license, at your option. Note that this dual
9 * Version 2 or later at the following locations: 9 * licensing only applies to this file, and not this project as a
10 * whole.
10 * 11 *
11 * http://www.opensource.org/licenses/gpl-license.html 12 * a) This file is free software; you can redistribute it and/or
12 * http://www.gnu.org/copyleft/gpl.html 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public
23 * License along with this file; if not, write to the Free
24 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
25 * MA 02110-1301 USA
26 *
27 * Or, alternatively,
28 *
29 * b) Permission is hereby granted, free of charge, to any person
30 * obtaining a copy of this software and associated documentation
31 * files (the "Software"), to deal in the Software without
32 * restriction, including without limitation the rights to use,
33 * copy, modify, merge, publish, distribute, sublicense, and/or
34 * sell copies of the Software, and to permit persons to whom the
35 * Software is furnished to do so, subject to the following
36 * conditions:
37 *
38 * The above copyright notice and this permission notice shall be
39 * included in all copies or substantial portions of the Software.
40 *
41 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
42 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
43 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
44 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
45 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
48 * OTHER DEALINGS IN THE SOFTWARE.
13 */ 49 */
14 50
15/dts-v1/; 51/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
new file mode 100644
index 000000000000..ed364d5e755e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@ -0,0 +1,228 @@
1/*
2 * Copyright 2014 - Iain Paton <ipaton0@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49/include/ "sun7i-a20.dtsi"
50/include/ "sunxi-common-regulators.dtsi"
51
52/ {
53 model = "Olimex A20-OLinuXino-LIME2";
54 compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20";
55
56 soc@01c00000 {
57 mmc0: mmc@01c0f000 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
60 vmmc-supply = <&reg_vcc3v3>;
61 bus-width = <4>;
62 cd-gpios = <&pio 7 1 0>; /* PH1 */
63 cd-inverted;
64 status = "okay";
65 };
66
67 usbphy: phy@01c13400 {
68 usb1_vbus-supply = <&reg_usb1_vbus>;
69 usb2_vbus-supply = <&reg_usb2_vbus>;
70 status = "okay";
71 };
72
73 ehci0: usb@01c14000 {
74 status = "okay";
75 };
76
77 ohci0: usb@01c14400 {
78 status = "okay";
79 };
80
81 ahci: sata@01c18000 {
82 target-supply = <&reg_ahci_5v>;
83 status = "okay";
84 };
85
86 ehci1: usb@01c1c000 {
87 status = "okay";
88 };
89
90 ohci1: usb@01c1c400 {
91 status = "okay";
92 };
93
94 pinctrl@01c20800 {
95 ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 {
96 allwinner,pins = "PC3";
97 allwinner,function = "gpio_out";
98 allwinner,drive = <0>;
99 allwinner,pull = <0>;
100 };
101
102 led_pins_olinuxinolime: led_pins@0 {
103 allwinner,pins = "PH2";
104 allwinner,function = "gpio_out";
105 allwinner,drive = <1>;
106 allwinner,pull = <0>;
107 };
108 };
109
110 uart0: serial@01c28000 {
111 pinctrl-names = "default";
112 pinctrl-0 = <&uart0_pins_a>;
113 status = "okay";
114 };
115
116 i2c0: i2c@01c2ac00 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&i2c0_pins_a>;
119 status = "okay";
120
121 axp209: pmic@34 {
122 compatible = "x-powers,axp209";
123 reg = <0x34>;
124 interrupt-parent = <&nmi_intc>;
125 interrupts = <0 8>;
126
127 interrupt-controller;
128 #interrupt-cells = <1>;
129
130 acin-supply = <&reg_axp_ipsout>;
131 vin2-supply = <&reg_axp_ipsout>;
132 vin3-supply = <&reg_axp_ipsout>;
133 ldo24in-supply = <&reg_axp_ipsout>;
134 ldo3in-supply = <&reg_axp_ipsout>;
135
136 regulators {
137 vdd_rtc: ldo1 {
138 regulator-min-microvolt = <1300000>;
139 regulator-max-microvolt = <1300000>;
140 regulator-always-on;
141 };
142
143 avcc: ldo2 {
144 regulator-min-microvolt = <1800000>;
145 regulator-max-microvolt = <3300000>;
146 regulator-always-on;
147 };
148
149 vcc_csi0: ldo3 {
150 regulator-min-microvolt = <700000>;
151 regulator-max-microvolt = <3500000>;
152 regulator-always-on;
153 };
154
155 vcc_csi1: ldo4 {
156 regulator-min-microvolt = <1250000>;
157 regulator-max-microvolt = <3300000>;
158 regulator-always-on;
159 };
160
161 vdd_cpu: dcdc2 {
162 regulator-min-microvolt = <700000>;
163 regulator-max-microvolt = <2275000>;
164 regulator-always-on;
165 };
166
167 vdd_int: dcdc3 {
168 regulator-min-microvolt = <700000>;
169 regulator-max-microvolt = <3500000>;
170 regulator-always-on;
171 };
172 };
173 };
174 };
175
176 i2c1: i2c@01c2b000 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins_a>;
179 status = "okay";
180 };
181
182 gmac: ethernet@01c50000 {
183 pinctrl-names = "default";
184 pinctrl-0 = <&gmac_pins_rgmii_a>;
185 phy = <&phy1>;
186 phy-mode = "rgmii";
187 status = "okay";
188
189 phy1: ethernet-phy@1 {
190 reg = <1>;
191 };
192 };
193 };
194
195 leds {
196 compatible = "gpio-leds";
197 pinctrl-names = "default";
198 pinctrl-0 = <&led_pins_olinuxinolime>;
199
200 green {
201 label = "a20-olinuxino-lime2:green:usr";
202 gpios = <&pio 7 2 0>;
203 default-state = "on";
204 };
205 };
206
207 reg_ahci_5v: ahci-5v {
208 pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>;
209 gpio = <&pio 2 3 0>;
210 status = "okay";
211 };
212
213 reg_usb1_vbus: usb1-vbus {
214 status = "okay";
215 };
216
217 reg_usb2_vbus: usb2-vbus {
218 status = "okay";
219 };
220
221 reg_axp_ipsout: axp_ipsout {
222 compatible = "regulator-fixed";
223 regulator-name = "axp-ipsout";
224 regulator-min-microvolt = <5000000>;
225 regulator-max-microvolt = <5000000>;
226 regulator-always-on;
227 };
228};
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
index 046dfc0d45d8..8dca49b2477b 100644
--- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -2,12 +2,48 @@
2 * Copyright 2014 Zoltan HERPAI 2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu> 3 * Zoltan HERPAI <wigyori@uid0.hu>
4 * 4 *
5 * The code contained herein is licensed under the GNU General Public 5 * This file is dual-licensed: you can use it either under the terms
6 * License. You may obtain a copy of the GNU General Public License 6 * of the GPL or the X11 license, at your option. Note that this dual
7 * Version 2 or later at the following locations: 7 * licensing only applies to this file, and not this project as a
8 * whole.
8 * 9 *
9 * http://www.opensource.org/licenses/gpl-license.html 10 * a) This file is free software; you can redistribute it and/or
10 * http://www.gnu.org/copyleft/gpl.html 11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public
21 * License along with this file; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 * MA 02110-1301 USA
24 *
25 * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
11 */ 47 */
12 48
13/dts-v1/; 49/dts-v1/;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 82097c905c48..82a524ce28ad 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
@@ -64,6 +64,20 @@
64 serial7 = &uart7; 64 serial7 = &uart7;
65 }; 65 };
66 66
67 chosen {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 framebuffer@0 {
73 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
74 allwinner,pipeline = "de_be0-lcd0-hdmi";
75 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
76 <&ahb_gates 44>;
77 status = "disabled";
78 };
79 };
80
67 cpus { 81 cpus {
68 #address-cells = <1>; 82 #address-cells = <1>;
69 #size-cells = <0>; 83 #size-cells = <0>;
@@ -552,8 +566,8 @@
552 reg-names = "phy_ctrl", "pmu1", "pmu2"; 566 reg-names = "phy_ctrl", "pmu1", "pmu2";
553 clocks = <&usb_clk 8>; 567 clocks = <&usb_clk 8>;
554 clock-names = "usb_phy"; 568 clock-names = "usb_phy";
555 resets = <&usb_clk 1>, <&usb_clk 2>; 569 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
556 reset-names = "usb1_reset", "usb2_reset"; 570 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
557 status = "disabled"; 571 status = "disabled";
558 }; 572 };
559 573
@@ -677,6 +691,13 @@
677 allwinner,pull = <0>; 691 allwinner,pull = <0>;
678 }; 692 };
679 693
694 uart3_pins_b: uart3@1 {
695 allwinner,pins = "PH0", "PH1";
696 allwinner,function = "uart3";
697 allwinner,drive = <0>;
698 allwinner,pull = <0>;
699 };
700
680 uart4_pins_a: uart4@0 { 701 uart4_pins_a: uart4@0 {
681 allwinner,pins = "PG10", "PG11"; 702 allwinner,pins = "PG10", "PG11";
682 allwinner,function = "uart4"; 703 allwinner,function = "uart4";
@@ -784,6 +805,13 @@
784 allwinner,pull = <0>; 805 allwinner,pull = <0>;
785 }; 806 };
786 807
808 spi0_pins_a: spi0@0 {
809 allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14";
810 allwinner,function = "spi0";
811 allwinner,drive = <0>;
812 allwinner,pull = <0>;
813 };
814
787 spi1_pins_a: spi1@0 { 815 spi1_pins_a: spi1@0 {
788 allwinner,pins = "PI16", "PI17", "PI18", "PI19"; 816 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
789 allwinner,function = "spi1"; 817 allwinner,function = "spi1";
@@ -819,6 +847,13 @@
819 allwinner,pull = <1>; 847 allwinner,pull = <1>;
820 }; 848 };
821 849
850 mmc2_pins_a: mmc2@0 {
851 allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11";
852 allwinner,function = "mmc2";
853 allwinner,drive = <2>;
854 allwinner,pull = <1>;
855 };
856
822 mmc3_pins_a: mmc3@0 { 857 mmc3_pins_a: mmc3@0 {
823 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; 858 allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
824 allwinner,function = "mmc3"; 859 allwinner,function = "mmc3";
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index e9b8cca8dcc1..7f2117ce6985 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -3,12 +3,48 @@
3 * 3 *
4 * Chen-Yu Tsai <wens@csie.org> 4 * Chen-Yu Tsai <wens@csie.org>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/dts-v1/; 50/dts-v1/;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6146ef15efbe..6086adbf9d74 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -8,18 +8,18 @@
8 * licensing only applies to this file, and not this project as a 8 * licensing only applies to this file, and not this project as a
9 * whole. 9 * whole.
10 * 10 *
11 * a) This library is free software; you can redistribute it and/or 11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the 13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version. 14 * License, or (at your option) any later version.
15 * 15 *
16 * This library is distributed in the hope that it will be useful, 16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public 21 * You should have received a copy of the GNU General Public
22 * License along with this library; if not, write to the Free 22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA 24 * MA 02110-1301 USA
25 * 25 *
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
new file mode 100644
index 000000000000..506948f582ee
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/dts-v1/;
51/include/ "sun9i-a80.dtsi"
52
53/ {
54 model = "Merrii A80 Optimus Board";
55 compatible = "merrii,a80-optimus", "allwinner,sun9i-a80";
56
57 chosen {
58 bootargs = "earlyprintk console=ttyS0,115200";
59 };
60
61 soc {
62 pio: pinctrl@06000800 {
63 i2c3_pins_a: i2c3@0 {
64 /* Enable internal pull-up */
65 allwinner,pull = <1>;
66 };
67
68 led_pins_optimus: led-pins@0 {
69 allwinner,pins = "PH0", "PH1";
70 allwinner,function = "gpio_out";
71 allwinner,drive = <0>;
72 allwinner,pull = <0>;
73 };
74
75 uart4_pins_a: uart4@0 {
76 /* Enable internal pull-up */
77 allwinner,pull = <1>;
78 };
79 };
80
81 uart0: serial@07000000 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart0_pins_a>;
84 status = "okay";
85 };
86
87 uart4: serial@07001000 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&uart4_pins_a>;
90 status = "okay";
91 };
92
93 i2c3: i2c@07003400 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c3_pins_a>;
96 status = "okay";
97 };
98 };
99
100 leds {
101 compatible = "gpio-leds";
102 pinctrl-names = "default";
103 pinctrl-0 = <&led_pins_optimus>;
104
105 /* The LED names match those found on the board */
106
107 led2 {
108 label = "optimus:led2:usr";
109 gpios = <&pio 7 1 0>;
110 };
111
112 /* led3 is on PM15, in R_PIO */
113
114 led4 {
115 label = "optimus:led4:usr";
116 gpios = <&pio 7 0 0>;
117 };
118 };
119};
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
new file mode 100644
index 000000000000..494714f67b57
--- /dev/null
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -0,0 +1,514 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
48 */
49
50/include/ "skeleton64.dtsi"
51
52/ {
53 interrupt-parent = <&gic>;
54
55 aliases {
56 serial0 = &uart0;
57 serial1 = &uart1;
58 serial2 = &uart2;
59 serial3 = &uart3;
60 serial4 = &uart4;
61 serial5 = &uart5;
62 serial6 = &r_uart;
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 cpu0: cpu@0 {
70 compatible = "arm,cortex-a7";
71 device_type = "cpu";
72 reg = <0x0>;
73 };
74
75 cpu1: cpu@1 {
76 compatible = "arm,cortex-a7";
77 device_type = "cpu";
78 reg = <0x1>;
79 };
80
81 cpu2: cpu@2 {
82 compatible = "arm,cortex-a7";
83 device_type = "cpu";
84 reg = <0x2>;
85 };
86
87 cpu3: cpu@3 {
88 compatible = "arm,cortex-a7";
89 device_type = "cpu";
90 reg = <0x3>;
91 };
92
93 cpu4: cpu@100 {
94 compatible = "arm,cortex-a15";
95 device_type = "cpu";
96 reg = <0x100>;
97 };
98
99 cpu5: cpu@101 {
100 compatible = "arm,cortex-a15";
101 device_type = "cpu";
102 reg = <0x101>;
103 };
104
105 cpu6: cpu@102 {
106 compatible = "arm,cortex-a15";
107 device_type = "cpu";
108 reg = <0x102>;
109 };
110
111 cpu7: cpu@103 {
112 compatible = "arm,cortex-a15";
113 device_type = "cpu";
114 reg = <0x103>;
115 };
116 };
117
118 memory {
119 /* 8GB max. with LPAE */
120 reg = <0 0x20000000 0x02 0>;
121 };
122
123 clocks {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 /*
127 * map 64 bit address range down to 32 bits,
128 * as the peripherals are all under 512MB.
129 */
130 ranges = <0 0 0 0x20000000>;
131
132 osc24M: osc24M_clk {
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
135 clock-frequency = <24000000>;
136 clock-output-names = "osc24M";
137 };
138
139 osc32k: osc32k_clk {
140 #clock-cells = <0>;
141 compatible = "fixed-clock";
142 clock-frequency = <32768>;
143 clock-output-names = "osc32k";
144 };
145
146 pll4: clk@0600000c {
147 #clock-cells = <0>;
148 compatible = "allwinner,sun9i-a80-pll4-clk";
149 reg = <0x0600000c 0x4>;
150 clocks = <&osc24M>;
151 clock-output-names = "pll4";
152 };
153
154 pll12: clk@0600002c {
155 #clock-cells = <0>;
156 compatible = "allwinner,sun9i-a80-pll4-clk";
157 reg = <0x0600002c 0x4>;
158 clocks = <&osc24M>;
159 clock-output-names = "pll12";
160 };
161
162 gt_clk: clk@0600005c {
163 #clock-cells = <0>;
164 compatible = "allwinner,sun9i-a80-gt-clk";
165 reg = <0x0600005c 0x4>;
166 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
167 clock-output-names = "gt";
168 };
169
170 ahb0: clk@06000060 {
171 #clock-cells = <0>;
172 compatible = "allwinner,sun9i-a80-ahb-clk";
173 reg = <0x06000060 0x4>;
174 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
175 clock-output-names = "ahb0";
176 };
177
178 ahb1: clk@06000064 {
179 #clock-cells = <0>;
180 compatible = "allwinner,sun9i-a80-ahb-clk";
181 reg = <0x06000064 0x4>;
182 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
183 clock-output-names = "ahb1";
184 };
185
186 ahb2: clk@06000068 {
187 #clock-cells = <0>;
188 compatible = "allwinner,sun9i-a80-ahb-clk";
189 reg = <0x06000068 0x4>;
190 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
191 clock-output-names = "ahb2";
192 };
193
194 apb0: clk@06000070 {
195 #clock-cells = <0>;
196 compatible = "allwinner,sun9i-a80-apb0-clk";
197 reg = <0x06000070 0x4>;
198 clocks = <&osc24M>, <&pll4>;
199 clock-output-names = "apb0";
200 };
201
202 apb1: clk@06000074 {
203 #clock-cells = <0>;
204 compatible = "allwinner,sun9i-a80-apb1-clk";
205 reg = <0x06000074 0x4>;
206 clocks = <&osc24M>, <&pll4>;
207 clock-output-names = "apb1";
208 };
209
210 cci400_clk: clk@06000078 {
211 #clock-cells = <0>;
212 compatible = "allwinner,sun9i-a80-gt-clk";
213 reg = <0x06000078 0x4>;
214 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
215 clock-output-names = "cci400";
216 };
217
218 ahb0_gates: clk@06000580 {
219 #clock-cells = <1>;
220 compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
221 reg = <0x06000580 0x4>;
222 clocks = <&ahb0>;
223 clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
224 "ahb0_ss", "ahb0_sd", "ahb0_nand1",
225 "ahb0_nand0", "ahb0_sdram",
226 "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
227 "ahb0_spi0","ahb0_spi1", "ahb0_spi2",
228 "ahb0_spi3";
229 };
230
231 ahb1_gates: clk@06000584 {
232 #clock-cells = <1>;
233 compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
234 reg = <0x06000584 0x4>;
235 clocks = <&ahb1>;
236 clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
237 "ahb1_gmac", "ahb1_msgbox",
238 "ahb1_spinlock", "ahb1_hstimer",
239 "ahb1_dma";
240 };
241
242 ahb2_gates: clk@06000588 {
243 #clock-cells = <1>;
244 compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
245 reg = <0x06000588 0x4>;
246 clocks = <&ahb2>;
247 clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
248 "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
249 "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
250 };
251
252 apb0_gates: clk@06000590 {
253 #clock-cells = <1>;
254 compatible = "allwinner,sun9i-a80-apb0-gates-clk";
255 reg = <0x06000590 0x4>;
256 clocks = <&apb0>;
257 clock-output-names = "apb0_spdif", "apb0_pio",
258 "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
259 "apb0_lradc", "apb0_gpadc", "apb0_twd",
260 "apb0_cirtx";
261 };
262
263 apb1_gates: clk@06000594 {
264 #clock-cells = <1>;
265 compatible = "allwinner,sun9i-a80-apb1-gates-clk";
266 reg = <0x06000594 0x4>;
267 clocks = <&apb1>;
268 clock-output-names = "apb1_i2c0", "apb1_i2c1",
269 "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
270 "apb1_uart0", "apb1_uart1",
271 "apb1_uart2", "apb1_uart3",
272 "apb1_uart4", "apb1_uart5";
273 };
274 };
275
276 soc {
277 compatible = "simple-bus";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 /*
281 * map 64 bit address range down to 32 bits,
282 * as the peripherals are all under 512MB.
283 */
284 ranges = <0 0 0 0x20000000>;
285
286 gic: interrupt-controller@01c41000 {
287 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
288 reg = <0x01c41000 0x1000>,
289 <0x01c42000 0x1000>,
290 <0x01c44000 0x2000>,
291 <0x01c46000 0x2000>;
292 interrupt-controller;
293 #interrupt-cells = <3>;
294 interrupts = <1 9 0xf04>;
295 };
296
297 ahb0_resets: reset@060005a0 {
298 #reset-cells = <1>;
299 compatible = "allwinner,sun6i-a31-clock-reset";
300 reg = <0x060005a0 0x4>;
301 };
302
303 ahb1_resets: reset@060005a4 {
304 #reset-cells = <1>;
305 compatible = "allwinner,sun6i-a31-clock-reset";
306 reg = <0x060005a4 0x4>;
307 };
308
309 ahb2_resets: reset@060005a8 {
310 #reset-cells = <1>;
311 compatible = "allwinner,sun6i-a31-clock-reset";
312 reg = <0x060005a8 0x4>;
313 };
314
315 apb0_resets: reset@060005b0 {
316 #reset-cells = <1>;
317 compatible = "allwinner,sun6i-a31-clock-reset";
318 reg = <0x060005b0 0x4>;
319 };
320
321 apb1_resets: reset@060005b4 {
322 #reset-cells = <1>;
323 compatible = "allwinner,sun6i-a31-clock-reset";
324 reg = <0x060005b4 0x4>;
325 };
326
327 timer@06000c00 {
328 compatible = "allwinner,sun4i-a10-timer";
329 reg = <0x06000c00 0xa0>;
330 interrupts = <0 18 4>,
331 <0 19 4>,
332 <0 20 4>,
333 <0 21 4>,
334 <0 22 4>,
335 <0 23 4>;
336
337 clocks = <&osc24M>;
338 };
339
340 pio: pinctrl@06000800 {
341 compatible = "allwinner,sun9i-a80-pinctrl";
342 reg = <0x06000800 0x400>;
343 interrupts = <0 11 4>,
344 <0 15 4>,
345 <0 16 4>,
346 <0 17 4>,
347 <0 120 4>;
348 clocks = <&apb0_gates 5>;
349 gpio-controller;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 #size-cells = <0>;
353 #gpio-cells = <3>;
354
355 i2c3_pins_a: i2c3@0 {
356 allwinner,pins = "PG10", "PG11";
357 allwinner,function = "i2c3";
358 allwinner,drive = <0>;
359 allwinner,pull = <0>;
360 };
361
362 uart0_pins_a: uart0@0 {
363 allwinner,pins = "PH12", "PH13";
364 allwinner,function = "uart0";
365 allwinner,drive = <0>;
366 allwinner,pull = <0>;
367 };
368
369 uart4_pins_a: uart4@0 {
370 allwinner,pins = "PG12", "PG13", "PG14", "PG15";
371 allwinner,function = "uart4";
372 allwinner,drive = <0>;
373 allwinner,pull = <0>;
374 };
375 };
376
377 uart0: serial@07000000 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x07000000 0x400>;
380 interrupts = <0 0 4>;
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 clocks = <&apb1_gates 16>;
384 resets = <&apb1_resets 16>;
385 status = "disabled";
386 };
387
388 uart1: serial@07000400 {
389 compatible = "snps,dw-apb-uart";
390 reg = <0x07000400 0x400>;
391 interrupts = <0 1 4>;
392 reg-shift = <2>;
393 reg-io-width = <4>;
394 clocks = <&apb1_gates 17>;
395 resets = <&apb1_resets 17>;
396 status = "disabled";
397 };
398
399 uart2: serial@07000800 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x07000800 0x400>;
402 interrupts = <0 2 4>;
403 reg-shift = <2>;
404 reg-io-width = <4>;
405 clocks = <&apb1_gates 18>;
406 resets = <&apb1_resets 18>;
407 status = "disabled";
408 };
409
410 uart3: serial@07000c00 {
411 compatible = "snps,dw-apb-uart";
412 reg = <0x07000c00 0x400>;
413 interrupts = <0 3 4>;
414 reg-shift = <2>;
415 reg-io-width = <4>;
416 clocks = <&apb1_gates 19>;
417 resets = <&apb1_resets 19>;
418 status = "disabled";
419 };
420
421 uart4: serial@07001000 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0x07001000 0x400>;
424 interrupts = <0 4 4>;
425 reg-shift = <2>;
426 reg-io-width = <4>;
427 clocks = <&apb1_gates 20>;
428 resets = <&apb1_resets 20>;
429 status = "disabled";
430 };
431
432 uart5: serial@07001400 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x07001400 0x400>;
435 interrupts = <0 5 4>;
436 reg-shift = <2>;
437 reg-io-width = <4>;
438 clocks = <&apb1_gates 21>;
439 resets = <&apb1_resets 21>;
440 status = "disabled";
441 };
442
443 i2c0: i2c@07002800 {
444 compatible = "allwinner,sun6i-a31-i2c";
445 reg = <0x07002800 0x400>;
446 interrupts = <0 6 4>;
447 clocks = <&apb1_gates 0>;
448 resets = <&apb1_resets 0>;
449 status = "disabled";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 };
453
454 i2c1: i2c@07002c00 {
455 compatible = "allwinner,sun6i-a31-i2c";
456 reg = <0x07002c00 0x400>;
457 interrupts = <0 7 4>;
458 clocks = <&apb1_gates 1>;
459 resets = <&apb1_resets 1>;
460 status = "disabled";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 };
464
465 i2c2: i2c@07003000 {
466 compatible = "allwinner,sun6i-a31-i2c";
467 reg = <0x07003000 0x400>;
468 interrupts = <0 8 4>;
469 clocks = <&apb1_gates 2>;
470 resets = <&apb1_resets 2>;
471 status = "disabled";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 };
475
476 i2c3: i2c@07003400 {
477 compatible = "allwinner,sun6i-a31-i2c";
478 reg = <0x07003400 0x400>;
479 interrupts = <0 9 4>;
480 clocks = <&apb1_gates 3>;
481 resets = <&apb1_resets 3>;
482 status = "disabled";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 };
486
487 i2c4: i2c@07003800 {
488 compatible = "allwinner,sun6i-a31-i2c";
489 reg = <0x07003800 0x400>;
490 interrupts = <0 10 4>;
491 clocks = <&apb1_gates 4>;
492 resets = <&apb1_resets 4>;
493 status = "disabled";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 };
497
498 r_wdt: watchdog@08001000 {
499 compatible = "allwinner,sun6i-a31-wdt";
500 reg = <0x08001000 0x20>;
501 interrupts = <0 36 4>;
502 };
503
504 r_uart: serial@08002800 {
505 compatible = "snps,dw-apb-uart";
506 reg = <0x08002800 0x400>;
507 interrupts = <0 38 4>;
508 reg-shift = <2>;
509 reg-io-width = <4>;
510 clocks = <&osc24M>;
511 status = "disabled";
512 };
513 };
514};
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index c9c5b10e03eb..d8876634f965 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -3,12 +3,48 @@
3 * 3 *
4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> 4 * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
5 * 5 *
6 * The code contained herein is licensed under the GNU General Public 6 * This file is dual-licensed: you can use it either under the terms
7 * License. You may obtain a copy of the GNU General Public License 7 * of the GPL or the X11 license, at your option. Note that this dual
8 * Version 2 or later at the following locations: 8 * licensing only applies to this file, and not this project as a
9 * whole.
9 * 10 *
10 * http://www.opensource.org/licenses/gpl-license.html 11 * a) This file is free software; you can redistribute it and/or
11 * http://www.gnu.org/copyleft/gpl.html 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public
22 * License along with this file; if not, write to the Free
23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
24 * MA 02110-1301 USA
25 *
26 * Or, alternatively,
27 *
28 * b) Permission is hereby granted, free of charge, to any person
29 * obtaining a copy of this software and associated documentation
30 * files (the "Software"), to deal in the Software without
31 * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 * conditions:
36 *
37 * The above copyright notice and this permission notice shall be
38 * included in all copies or substantial portions of the Software.
39 *
40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
47 * OTHER DEALINGS IN THE SOFTWARE.
12 */ 48 */
13 49
14/ { 50/ {
@@ -21,6 +57,13 @@
21 allwinner,pull = <0>; 57 allwinner,pull = <0>;
22 }; 58 };
23 59
60 usb0_vbus_pin_a: usb0_vbus_pin@0 {
61 allwinner,pins = "PB9";
62 allwinner,function = "gpio_out";
63 allwinner,drive = <0>;
64 allwinner,pull = <0>;
65 };
66
24 usb1_vbus_pin_a: usb1_vbus_pin@0 { 67 usb1_vbus_pin_a: usb1_vbus_pin@0 {
25 allwinner,pins = "PH6"; 68 allwinner,pins = "PH6";
26 allwinner,function = "gpio_out"; 69 allwinner,function = "gpio_out";
@@ -44,11 +87,24 @@
44 regulator-name = "ahci-5v"; 87 regulator-name = "ahci-5v";
45 regulator-min-microvolt = <5000000>; 88 regulator-min-microvolt = <5000000>;
46 regulator-max-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>;
90 regulator-boot-on;
47 enable-active-high; 91 enable-active-high;
48 gpio = <&pio 1 8 0>; 92 gpio = <&pio 1 8 0>;
49 status = "disabled"; 93 status = "disabled";
50 }; 94 };
51 95
96 reg_usb0_vbus: usb0-vbus {
97 compatible = "regulator-fixed";
98 pinctrl-names = "default";
99 pinctrl-0 = <&usb0_vbus_pin_a>;
100 regulator-name = "usb0-vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 enable-active-high;
104 gpio = <&pio 1 9 0>;
105 status = "disabled";
106 };
107
52 reg_usb1_vbus: usb1-vbus { 108 reg_usb1_vbus: usb1-vbus {
53 compatible = "regulator-fixed"; 109 compatible = "regulator-fixed";
54 pinctrl-names = "default"; 110 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index a1b682ea01bd..cbf5a1ae0ca7 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -189,7 +189,7 @@
189 189
190 /* ALS and Proximity sensor */ 190 /* ALS and Proximity sensor */
191 isl29028@44 { 191 isl29028@44 {
192 compatible = "isil,isl29028"; 192 compatible = "isl,isl29028";
193 reg = <0x44>; 193 reg = <0x44>;
194 interrupt-parent = <&gpio>; 194 interrupt-parent = <&gpio>;
195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..56a452bc326c
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -0,0 +1,96 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/ {
11 chosen {
12 bootargs = "console=ttyLP0,115200";
13 };
14
15 regulators {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 sys_5v0_reg: regulator@0 {
21 compatible = "regulator-fixed";
22 reg = <0>;
23 regulator-name = "5v0";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 regulator-always-on;
27 };
28
29 /* USBH_PEN */
30 usbh_vbus_reg: regulator@1 {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_usbh1_reg>;
34 reg = <1>;
35 regulator-name = "usbh_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
39 vin-supply = <&sys_5v0_reg>;
40 };
41 };
42};
43
44&bl {
45 brightness-levels = <0 4 8 16 32 64 128 255>;
46 default-brightness-level = <6>;
47 status = "okay";
48};
49
50&esdhc1 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_esdhc1>;
53 bus-width = <4>;
54 status = "okay";
55};
56
57&fec1 {
58 phy-mode = "rmii";
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_fec1>;
61 status = "okay";
62};
63
64&i2c0 {
65 status = "okay";
66
67 /* M41T0M6 real time clock on carrier board */
68 rtc: m41t0m6@68 {
69 compatible = "st,m41t00";
70 reg = <0x68>;
71 };
72};
73
74&pwm0 {
75 status = "okay";
76};
77
78&pwm1 {
79 status = "okay";
80};
81
82&uart0 {
83 status = "okay";
84};
85
86&uart1 {
87 status = "okay";
88};
89
90&uart2 {
91 status = "okay";
92};
93
94&usbh1 {
95 vbus-supply = <&usbh_vbus_reg>;
96};
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
new file mode 100644
index 000000000000..82f5728be5c9
--- /dev/null
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -0,0 +1,186 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/ {
11 bl: backlight {
12 compatible = "pwm-backlight";
13 pwms = <&pwm0 0 5000000 0>;
14 status = "disabled";
15 };
16};
17
18&adc0 {
19 status = "okay";
20};
21
22&adc1 {
23 status = "okay";
24};
25
26&edma0 {
27 status = "okay";
28};
29
30&esdhc1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>;
34 cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
35};
36
37&fec1 {
38 phy-mode = "rmii";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_fec1>;
41};
42
43&i2c0 {
44 clock-frequency = <400000>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_i2c0>;
47};
48
49&pwm0 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_pwm0>;
52};
53
54&pwm1 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_pwm1>;
57};
58
59&uart0 {
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_uart0>;
62};
63
64&uart1 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_uart1>;
67};
68
69&uart2 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_uart2>;
72};
73
74&usbdev0 {
75 disable-over-current;
76 status = "okay";
77};
78
79&usbh1 {
80 disable-over-current;
81 status = "okay";
82};
83
84&usbmisc0 {
85 status = "okay";
86};
87
88&usbmisc1 {
89 status = "okay";
90};
91
92&usbphy0 {
93 status = "okay";
94};
95
96&usbphy1 {
97 status = "okay";
98};
99
100&iomuxc {
101 vf610-colibri {
102 pinctrl_gpio_ext: gpio_ext {
103 fsl,pins = <
104 VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
105 VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
106 VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
107 >;
108 };
109
110 pinctrl_esdhc1: esdhc1grp {
111 fsl,pins = <
112 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
113 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
114 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
115 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
116 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
117 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
118 VF610_PAD_PTB20__GPIO_42 0x219d
119 >;
120 };
121
122 pinctrl_fec1: fec1grp {
123 fsl,pins = <
124 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
125 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
126 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
127 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
128 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
129 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
130 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
131 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
132 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
133 >;
134 };
135
136 pinctrl_i2c0: i2c0grp {
137 fsl,pins = <
138 VF610_PAD_PTB14__I2C0_SCL 0x37ff
139 VF610_PAD_PTB15__I2C0_SDA 0x37ff
140 >;
141 };
142
143 pinctrl_pwm0: pwm0grp {
144 fsl,pins = <
145 VF610_PAD_PTB0__FTM0_CH0 0x1182
146 VF610_PAD_PTB1__FTM0_CH1 0x1182
147 >;
148 };
149
150 pinctrl_pwm1: pwm1grp {
151 fsl,pins = <
152 VF610_PAD_PTB8__FTM1_CH0 0x1182
153 VF610_PAD_PTB9__FTM1_CH1 0x1182
154 >;
155 };
156
157 pinctrl_uart0: uart0grp {
158 fsl,pins = <
159 VF610_PAD_PTB10__UART0_TX 0x21a2
160 VF610_PAD_PTB11__UART0_RX 0x21a1
161 >;
162 };
163
164 pinctrl_uart1: uart1grp {
165 fsl,pins = <
166 VF610_PAD_PTB4__UART1_TX 0x21a2
167 VF610_PAD_PTB5__UART1_RX 0x21a1
168 >;
169 };
170
171 pinctrl_uart2: uart2grp {
172 fsl,pins = <
173 VF610_PAD_PTD0__UART2_TX 0x21a2
174 VF610_PAD_PTD1__UART2_RX 0x21a1
175 VF610_PAD_PTD2__UART2_RTS 0x21a2
176 VF610_PAD_PTD3__UART2_CTS 0x21a1
177 >;
178 };
179
180 pinctrl_usbh1_reg: gpio_usb_vbus {
181 fsl,pins = <
182 VF610_PAD_PTD4__GPIO_83 0x22ed
183 >;
184 };
185 };
186};
diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7fc782c4fc52
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10/dts-v1/;
11#include "vf500-colibri.dtsi"
12#include "vf-colibri-eval-v3.dtsi"
13
14/ {
15 model = "Toradex Colibri VF50 on Colibri Evaluation Board";
16 compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500";
17};
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
new file mode 100644
index 000000000000..cee34a32f25b
--- /dev/null
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -0,0 +1,20 @@
1/*
2 * Copyright 2014 Toradex AG
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf500.dtsi"
11#include "vf-colibri.dtsi"
12
13/ {
14 model = "Toradex Colibri VF50 COM";
15 compatible = "toradex,vf610-colibri_vf50", "fsl,vf500";
16
17 memory {
18 reg = <0x80000000 0x8000000>;
19 };
20};
diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi
new file mode 100644
index 000000000000..de6700542714
--- /dev/null
+++ b/arch/arm/boot/dts/vf500.dtsi
@@ -0,0 +1,171 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "skeleton.dtsi"
11#include "vfxxx.dtsi"
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 a5_cpu: cpu@0 {
20 compatible = "arm,cortex-a5";
21 device_type = "cpu";
22 reg = <0x0>;
23 };
24 };
25
26 soc {
27 interrupt-parent = <&intc>;
28
29 aips-bus@40000000 {
30
31 intc: interrupt-controller@40002000 {
32 compatible = "arm,cortex-a9-gic";
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 reg = <0x40003000 0x1000>,
36 <0x40002100 0x100>;
37 };
38
39 global_timer: timer@40002200 {
40 compatible = "arm,cortex-a9-global-timer";
41 reg = <0x40002200 0x20>;
42 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&clks VF610_CLK_PLATFORM_BUS>;
44 };
45 };
46 };
47};
48
49&adc0 {
50 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
51};
52
53&adc1 {
54 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
55};
56
57&can0 {
58 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
59};
60
61&can1 {
62 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
63};
64
65&dspi0 {
66 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
67};
68
69&edma0 {
70 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
72 interrupt-names = "edma-tx", "edma-err";
73};
74
75&edma1 {
76 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
78 interrupt-names = "edma-tx", "edma-err";
79};
80
81&esdhc1 {
82 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
83};
84
85&fec0 {
86 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
87};
88
89&fec1 {
90 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
91};
92
93&ftm {
94 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
95};
96
97&gpio1 {
98 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
99};
100
101&gpio2 {
102 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
103};
104
105&gpio3 {
106 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
107};
108
109&gpio4 {
110 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
111};
112
113&gpio5 {
114 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
115};
116
117&i2c0 {
118 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
119};
120
121&pit {
122 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
123};
124
125&qspi0 {
126 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
127};
128
129&sai2 {
130 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
131};
132
133&uart0 {
134 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
135};
136
137&uart1 {
138 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
139};
140
141&uart2 {
142 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
143};
144
145&uart3 {
146 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
147};
148
149&uart4 {
150 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
151};
152
153&uart5 {
154 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
155};
156
157&usbdev0 {
158 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
159};
160
161&usbh1 {
162 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
163};
164
165&usbphy0 {
166 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
167};
168
169&usbphy1 {
170 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
171};
diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
index 7fb306679341..10ebe99e2751 100644
--- a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts
@@ -9,38 +9,9 @@
9 9
10/dts-v1/; 10/dts-v1/;
11#include "vf610-colibri.dtsi" 11#include "vf610-colibri.dtsi"
12#include "vf-colibri-eval-v3.dtsi"
12 13
13/ { 14/ {
14 model = "Toradex Colibri VF61 on Colibri Evaluation Board"; 15 model = "Toradex Colibri VF61 on Colibri Evaluation Board";
15 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; 16 compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610";
16 17}; \ No newline at end of file
17 chosen {
18 bootargs = "console=ttyLP0,115200";
19 };
20};
21
22&esdhc1 {
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_esdhc1>;
25 bus-width = <4>;
26 status = "okay";
27};
28
29&fec1 {
30 phy-mode = "rmii";
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_fec1>;
33 status = "okay";
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 status = "okay";
42};
43
44&uart2 {
45 status = "okay";
46};
diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi
index 0cd83434b073..19fe045b8334 100644
--- a/arch/arm/boot/dts/vf610-colibri.dtsi
+++ b/arch/arm/boot/dts/vf610-colibri.dtsi
@@ -8,6 +8,7 @@
8 */ 8 */
9 9
10#include "vf610.dtsi" 10#include "vf610.dtsi"
11#include "vf-colibri.dtsi"
11 12
12/ { 13/ {
13 model = "Toradex Colibri VF61 COM"; 14 model = "Toradex Colibri VF61 COM";
@@ -16,108 +17,9 @@
16 memory { 17 memory {
17 reg = <0x80000000 0x10000000>; 18 reg = <0x80000000 0x10000000>;
18 }; 19 };
19
20 clocks {
21 enet_ext {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <50000000>;
25 };
26 };
27
28};
29
30&esdhc1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_esdhc1>;
33 bus-width = <4>;
34};
35
36&fec1 {
37 phy-mode = "rmii";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec1>;
40}; 20};
41 21
42&L2 { 22&L2 {
43 arm,data-latency = <2 1 2>; 23 arm,data-latency = <2 1 2>;
44 arm,tag-latency = <3 2 3>; 24 arm,tag-latency = <3 2 3>;
45}; 25};
46
47&uart0 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_uart0>;
50};
51
52&uart1 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_uart1>;
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_uart2>;
60};
61
62&usbdev0 {
63 disable-over-current;
64 status = "okay";
65};
66
67&usbh1 {
68 disable-over-current;
69 status = "okay";
70};
71
72&iomuxc {
73 vf610-colibri {
74 pinctrl_esdhc1: esdhc1grp {
75 fsl,pins = <
76 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
77 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
78 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
79 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
80 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
81 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
82 VF610_PAD_PTB20__GPIO_42 0x219d
83 >;
84 };
85
86 pinctrl_fec1: fec1grp {
87 fsl,pins = <
88 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
89 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
90 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
91 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
92 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
93 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
94 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
95 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
96 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
97 >;
98 };
99
100 pinctrl_uart0: uart0grp {
101 fsl,pins = <
102 VF610_PAD_PTB10__UART0_TX 0x21a2
103 VF610_PAD_PTB11__UART0_RX 0x21a1
104 >;
105 };
106
107 pinctrl_uart1: uart1grp {
108 fsl,pins = <
109 VF610_PAD_PTB4__UART1_TX 0x21a2
110 VF610_PAD_PTB5__UART1_RX 0x21a1
111 >;
112 };
113
114 pinctrl_uart2: uart2grp {
115 fsl,pins = <
116 VF610_PAD_PTD0__UART2_TX 0x21a2
117 VF610_PAD_PTD1__UART2_RX 0x21a1
118 VF610_PAD_PTD2__UART2_RTS 0x21a2
119 VF610_PAD_PTD3__UART2_CTS 0x21a1
120 >;
121 };
122 };
123};
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index de1b453c2932..fd8758b639f5 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -23,14 +23,16 @@
23 reg = <0x80000000 0x10000000>; 23 reg = <0x80000000 0x10000000>;
24 }; 24 };
25 25
26 clocks { 26 enet_ext: enet_ext {
27 enet_ext { 27 compatible = "fixed-clock";
28 compatible = "fixed-clock"; 28 #clock-cells = <0>;
29 #clock-cells = <0>; 29 clock-frequency = <50000000>;
30 clock-frequency = <50000000>;
31 };
32 }; 30 };
31};
33 32
33&clks {
34 clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
35 clock-names = "sxosc", "fxosc", "enet_ext";
34}; 36};
35 37
36&esdhc1 { 38&esdhc1 {
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 189b6975fe7d..a0f762159cb2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -22,18 +22,16 @@
22 reg = <0x80000000 0x8000000>; 22 reg = <0x80000000 0x8000000>;
23 }; 23 };
24 24
25 clocks { 25 audio_ext: mclk_osc {
26 audio_ext { 26 compatible = "fixed-clock";
27 compatible = "fixed-clock"; 27 #clock-cells = <0>;
28 #clock-cells = <0>; 28 clock-frequency = <24576000>;
29 clock-frequency = <24576000>; 29 };
30 };
31 30
32 enet_ext { 31 enet_ext: eth_osc {
33 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
34 #clock-cells = <0>; 33 #clock-cells = <0>;
35 clock-frequency = <50000000>; 34 clock-frequency = <50000000>;
36 };
37 }; 35 };
38 36
39 regulators { 37 regulators {
@@ -95,6 +93,11 @@
95 status = "okay"; 93 status = "okay";
96}; 94};
97 95
96&clks {
97 clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
98 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
99};
100
98&dspi0 { 101&dspi0 {
99 bus-num = <0>; 102 bus-num = <0>;
100 pinctrl-names = "default"; 103 pinctrl-names = "default";
@@ -112,10 +115,15 @@
112 }; 115 };
113}; 116};
114 117
118&edma0 {
119 status = "okay";
120};
121
115&esdhc1 { 122&esdhc1 {
116 pinctrl-names = "default"; 123 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_esdhc1>; 124 pinctrl-0 = <&pinctrl_esdhc1>;
118 bus-width = <4>; 125 bus-width = <4>;
126 cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
119 status = "okay"; 127 status = "okay";
120}; 128};
121 129
@@ -285,3 +293,19 @@
285 disable-over-current; 293 disable-over-current;
286 status = "okay"; 294 status = "okay";
287}; 295};
296
297&usbmisc0 {
298 status = "okay";
299};
300
301&usbmisc1 {
302 status = "okay";
303};
304
305&usbphy0 {
306 status = "okay";
307};
308
309&usbphy1 {
310 status = "okay";
311};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 4d2ec32de96f..5f8eb1bd782b 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -7,481 +7,19 @@
7 * (at your option) any later version. 7 * (at your option) any later version.
8 */ 8 */
9 9
10#include "skeleton.dtsi" 10#include "vf500.dtsi"
11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14 11
15/ { 12&a5_cpu {
16 aliases { 13 next-level-cache = <&L2>;
17 can0 = &can0; 14};
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 compatible = "arm,cortex-a5";
40 device_type = "cpu";
41 reg = <0x0>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 clocks {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 sxosc {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <32768>;
54 };
55
56 fxosc {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&intc>;
68 ranges;
69
70 aips0: aips-bus@40000000 {
71 compatible = "fsl,aips-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 interrupt-parent = <&intc>;
75 reg = <0x40000000 0x70000>;
76 ranges;
77
78 intc: interrupt-controller@40002000 {
79 compatible = "arm,cortex-a9-gic";
80 #interrupt-cells = <3>;
81 interrupt-controller;
82 reg = <0x40003000 0x1000>,
83 <0x40002100 0x100>;
84 };
85
86 L2: l2-cache@40006000 {
87 compatible = "arm,pl310-cache";
88 reg = <0x40006000 0x1000>;
89 cache-unified;
90 cache-level = <2>;
91 arm,data-latency = <1 1 1>;
92 arm,tag-latency = <2 2 2>;
93 };
94
95 edma0: dma-controller@40018000 {
96 #dma-cells = <2>;
97 compatible = "fsl,vf610-edma";
98 reg = <0x40018000 0x2000>,
99 <0x40024000 0x1000>,
100 <0x40025000 0x1000>;
101 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
102 <0 9 IRQ_TYPE_LEVEL_HIGH>;
103 interrupt-names = "edma-tx", "edma-err";
104 dma-channels = <32>;
105 clock-names = "dmamux0", "dmamux1";
106 clocks = <&clks VF610_CLK_DMAMUX0>,
107 <&clks VF610_CLK_DMAMUX1>;
108 };
109
110 can0: flexcan@40020000 {
111 compatible = "fsl,vf610-flexcan";
112 reg = <0x40020000 0x4000>;
113 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&clks VF610_CLK_FLEXCAN0>,
115 <&clks VF610_CLK_FLEXCAN0>;
116 clock-names = "ipg", "per";
117 status = "disabled";
118 };
119
120 uart0: serial@40027000 {
121 compatible = "fsl,vf610-lpuart";
122 reg = <0x40027000 0x1000>;
123 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&clks VF610_CLK_UART0>;
125 clock-names = "ipg";
126 dmas = <&edma0 0 2>,
127 <&edma0 0 3>;
128 dma-names = "rx","tx";
129 status = "disabled";
130 };
131
132 uart1: serial@40028000 {
133 compatible = "fsl,vf610-lpuart";
134 reg = <0x40028000 0x1000>;
135 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&clks VF610_CLK_UART1>;
137 clock-names = "ipg";
138 dmas = <&edma0 0 4>,
139 <&edma0 0 5>;
140 dma-names = "rx","tx";
141 status = "disabled";
142 };
143
144 uart2: serial@40029000 {
145 compatible = "fsl,vf610-lpuart";
146 reg = <0x40029000 0x1000>;
147 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&clks VF610_CLK_UART2>;
149 clock-names = "ipg";
150 dmas = <&edma0 0 6>,
151 <&edma0 0 7>;
152 dma-names = "rx","tx";
153 status = "disabled";
154 };
155
156 uart3: serial@4002a000 {
157 compatible = "fsl,vf610-lpuart";
158 reg = <0x4002a000 0x1000>;
159 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clks VF610_CLK_UART3>;
161 clock-names = "ipg";
162 dmas = <&edma0 0 8>,
163 <&edma0 0 9>;
164 dma-names = "rx","tx";
165 status = "disabled";
166 };
167
168 dspi0: dspi0@4002c000 {
169 #address-cells = <1>;
170 #size-cells = <0>;
171 compatible = "fsl,vf610-dspi";
172 reg = <0x4002c000 0x1000>;
173 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clks VF610_CLK_DSPI0>;
175 clock-names = "dspi";
176 spi-num-chipselects = <5>;
177 status = "disabled";
178 };
179
180 sai2: sai@40031000 {
181 compatible = "fsl,vf610-sai";
182 reg = <0x40031000 0x1000>;
183 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&clks VF610_CLK_SAI2>;
185 clock-names = "sai";
186 dma-names = "tx", "rx";
187 dmas = <&edma0 0 21>,
188 <&edma0 0 20>;
189 status = "disabled";
190 };
191
192 pit: pit@40037000 {
193 compatible = "fsl,vf610-pit";
194 reg = <0x40037000 0x1000>;
195 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&clks VF610_CLK_PIT>;
197 clock-names = "pit";
198 };
199
200 pwm0: pwm@40038000 {
201 compatible = "fsl,vf610-ftm-pwm";
202 #pwm-cells = <3>;
203 reg = <0x40038000 0x1000>;
204 clock-names = "ftm_sys", "ftm_ext",
205 "ftm_fix", "ftm_cnt_clk_en";
206 clocks = <&clks VF610_CLK_FTM0>,
207 <&clks VF610_CLK_FTM0_EXT_SEL>,
208 <&clks VF610_CLK_FTM0_FIX_SEL>,
209 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
210 status = "disabled";
211 };
212
213 adc0: adc@4003b000 {
214 compatible = "fsl,vf610-adc";
215 reg = <0x4003b000 0x1000>;
216 interrupts = <0 53 0x04>;
217 clocks = <&clks VF610_CLK_ADC0>;
218 clock-names = "adc";
219 status = "disabled";
220 };
221
222 wdog@4003e000 {
223 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
224 reg = <0x4003e000 0x1000>;
225 clocks = <&clks VF610_CLK_WDT>;
226 clock-names = "wdog";
227 };
228
229 qspi0: quadspi@40044000 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,vf610-qspi";
233 reg = <0x40044000 0x1000>;
234 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks VF610_CLK_QSPI0_EN>,
236 <&clks VF610_CLK_QSPI0>;
237 clock-names = "qspi_en", "qspi";
238 status = "disabled";
239 };
240
241 iomuxc: iomuxc@40048000 {
242 compatible = "fsl,vf610-iomuxc";
243 reg = <0x40048000 0x1000>;
244 #gpio-range-cells = <3>;
245 };
246
247 gpio1: gpio@40049000 {
248 compatible = "fsl,vf610-gpio";
249 reg = <0x40049000 0x1000 0x400ff000 0x40>;
250 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
251 gpio-controller;
252 #gpio-cells = <2>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 gpio-ranges = <&iomuxc 0 0 32>;
256 };
257
258 gpio2: gpio@4004a000 {
259 compatible = "fsl,vf610-gpio";
260 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
261 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 gpio-ranges = <&iomuxc 0 32 32>;
267 };
268
269 gpio3: gpio@4004b000 {
270 compatible = "fsl,vf610-gpio";
271 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
272 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 gpio-ranges = <&iomuxc 0 64 32>;
278 };
279
280 gpio4: gpio@4004c000 {
281 compatible = "fsl,vf610-gpio";
282 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
283 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
284 gpio-controller;
285 #gpio-cells = <2>;
286 interrupt-controller;
287 #interrupt-cells = <2>;
288 gpio-ranges = <&iomuxc 0 96 32>;
289 };
290
291 gpio5: gpio@4004d000 {
292 compatible = "fsl,vf610-gpio";
293 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
294 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 gpio-ranges = <&iomuxc 0 128 7>;
300 };
301
302 anatop: anatop@40050000 {
303 compatible = "fsl,vf610-anatop", "syscon";
304 reg = <0x40050000 0x400>;
305 };
306
307 usbphy0: usbphy@40050800 {
308 compatible = "fsl,vf610-usbphy";
309 reg = <0x40050800 0x400>;
310 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clks VF610_CLK_USBPHY0>;
312 fsl,anatop = <&anatop>;
313 };
314
315 usbphy1: usbphy@40050c00 {
316 compatible = "fsl,vf610-usbphy";
317 reg = <0x40050c00 0x400>;
318 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&clks VF610_CLK_USBPHY1>;
320 fsl,anatop = <&anatop>;
321 };
322
323 i2c0: i2c@40066000 {
324 #address-cells = <1>;
325 #size-cells = <0>;
326 compatible = "fsl,vf610-i2c";
327 reg = <0x40066000 0x1000>;
328 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clks VF610_CLK_I2C0>;
330 clock-names = "ipg";
331 dmas = <&edma0 0 50>,
332 <&edma0 0 51>;
333 dma-names = "rx","tx";
334 status = "disabled";
335 };
336
337 clks: ccm@4006b000 {
338 compatible = "fsl,vf610-ccm";
339 reg = <0x4006b000 0x1000>;
340 #clock-cells = <1>;
341 };
342
343 usbdev0: usb@40034000 {
344 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
345 reg = <0x40034000 0x800>;
346 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks VF610_CLK_USBC0>;
348 fsl,usbphy = <&usbphy0>;
349 fsl,usbmisc = <&usbmisc0 0>;
350 dr_mode = "peripheral";
351 status = "disabled";
352 };
353
354 usbmisc0: usb@40034800 {
355 #index-cells = <1>;
356 compatible = "fsl,vf610-usbmisc";
357 reg = <0x40034800 0x200>;
358 clocks = <&clks VF610_CLK_USBC0>;
359 };
360 };
361
362 aips1: aips-bus@40080000 {
363 compatible = "fsl,aips-bus", "simple-bus";
364 #address-cells = <1>;
365 #size-cells = <1>;
366 reg = <0x40080000 0x80000>;
367 ranges;
368
369 edma1: dma-controller@40098000 {
370 #dma-cells = <2>;
371 compatible = "fsl,vf610-edma";
372 reg = <0x40098000 0x2000>,
373 <0x400a1000 0x1000>,
374 <0x400a2000 0x1000>;
375 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
376 <0 11 IRQ_TYPE_LEVEL_HIGH>;
377 interrupt-names = "edma-tx", "edma-err";
378 dma-channels = <32>;
379 clock-names = "dmamux0", "dmamux1";
380 clocks = <&clks VF610_CLK_DMAMUX2>,
381 <&clks VF610_CLK_DMAMUX3>;
382 };
383
384 uart4: serial@400a9000 {
385 compatible = "fsl,vf610-lpuart";
386 reg = <0x400a9000 0x1000>;
387 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&clks VF610_CLK_UART4>;
389 clock-names = "ipg";
390 status = "disabled";
391 };
392
393 uart5: serial@400aa000 {
394 compatible = "fsl,vf610-lpuart";
395 reg = <0x400aa000 0x1000>;
396 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks VF610_CLK_UART5>;
398 clock-names = "ipg";
399 status = "disabled";
400 };
401
402 adc1: adc@400bb000 {
403 compatible = "fsl,vf610-adc";
404 reg = <0x400bb000 0x1000>;
405 interrupts = <0 54 0x04>;
406 clocks = <&clks VF610_CLK_ADC1>;
407 clock-names = "adc";
408 status = "disabled";
409 };
410
411 esdhc1: esdhc@400b2000 {
412 compatible = "fsl,imx53-esdhc";
413 reg = <0x400b2000 0x1000>;
414 interrupts = <0 28 0x04>;
415 clocks = <&clks VF610_CLK_IPG_BUS>,
416 <&clks VF610_CLK_PLATFORM_BUS>,
417 <&clks VF610_CLK_ESDHC1>;
418 clock-names = "ipg", "ahb", "per";
419 status = "disabled";
420 };
421
422 usbh1: usb@400b4000 {
423 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
424 reg = <0x400b4000 0x800>;
425 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks VF610_CLK_USBC1>;
427 fsl,usbphy = <&usbphy1>;
428 fsl,usbmisc = <&usbmisc1 0>;
429 dr_mode = "host";
430 status = "disabled";
431 };
432
433 usbmisc1: usb@400b4800 {
434 #index-cells = <1>;
435 compatible = "fsl,vf610-usbmisc";
436 reg = <0x400b4800 0x200>;
437 clocks = <&clks VF610_CLK_USBC1>;
438 };
439
440 ftm: ftm@400b8000 {
441 compatible = "fsl,ftm-timer";
442 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
443 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
444 clock-names = "ftm-evt", "ftm-src",
445 "ftm-evt-counter-en", "ftm-src-counter-en";
446 clocks = <&clks VF610_CLK_FTM2>,
447 <&clks VF610_CLK_FTM3>,
448 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
449 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
450 status = "disabled";
451 };
452
453 fec0: ethernet@400d0000 {
454 compatible = "fsl,mvf600-fec";
455 reg = <0x400d0000 0x1000>;
456 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks VF610_CLK_ENET0>,
458 <&clks VF610_CLK_ENET0>,
459 <&clks VF610_CLK_ENET>;
460 clock-names = "ipg", "ahb", "ptp";
461 status = "disabled";
462 };
463
464 fec1: ethernet@400d1000 {
465 compatible = "fsl,mvf600-fec";
466 reg = <0x400d1000 0x1000>;
467 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks VF610_CLK_ENET1>,
469 <&clks VF610_CLK_ENET1>,
470 <&clks VF610_CLK_ENET>;
471 clock-names = "ipg", "ahb", "ptp";
472 status = "disabled";
473 };
474
475 can1: flexcan@400d4000 {
476 compatible = "fsl,vf610-flexcan";
477 reg = <0x400d4000 0x4000>;
478 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&clks VF610_CLK_FLEXCAN1>,
480 <&clks VF610_CLK_FLEXCAN1>;
481 clock-names = "ipg", "per";
482 status = "disabled";
483 };
484 15
485 }; 16&aips0 {
17 L2: l2-cache@40006000 {
18 compatible = "arm,pl310-cache";
19 reg = <0x40006000 0x1000>;
20 cache-unified;
21 cache-level = <2>;
22 arm,data-latency = <1 1 1>;
23 arm,tag-latency = <2 2 2>;
486 }; 24 };
487}; 25};
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi
new file mode 100644
index 000000000000..505969ae8093
--- /dev/null
+++ b/arch/arm/boot/dts/vfxxx.dtsi
@@ -0,0 +1,437 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "vf610-pinfunc.h"
11#include <dt-bindings/clock/vf610-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 aliases {
17 can0 = &can0;
18 can1 = &can1;
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 usbphy0 = &usbphy0;
31 usbphy1 = &usbphy1;
32 };
33
34 fxosc: fxosc {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <24000000>;
38 };
39
40 sxosc: sxosc {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32768>;
44 };
45
46 soc {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "simple-bus";
50 ranges;
51
52 aips0: aips-bus@40000000 {
53 compatible = "fsl,aips-bus", "simple-bus";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 ranges;
57
58 edma0: dma-controller@40018000 {
59 #dma-cells = <2>;
60 compatible = "fsl,vf610-edma";
61 reg = <0x40018000 0x2000>,
62 <0x40024000 0x1000>,
63 <0x40025000 0x1000>;
64 dma-channels = <32>;
65 clock-names = "dmamux0", "dmamux1";
66 clocks = <&clks VF610_CLK_DMAMUX0>,
67 <&clks VF610_CLK_DMAMUX1>;
68 status = "disabled";
69 };
70
71 can0: flexcan@40020000 {
72 compatible = "fsl,vf610-flexcan";
73 reg = <0x40020000 0x4000>;
74 clocks = <&clks VF610_CLK_FLEXCAN0>,
75 <&clks VF610_CLK_FLEXCAN0>;
76 clock-names = "ipg", "per";
77 status = "disabled";
78 };
79
80 uart0: serial@40027000 {
81 compatible = "fsl,vf610-lpuart";
82 reg = <0x40027000 0x1000>;
83 clocks = <&clks VF610_CLK_UART0>;
84 clock-names = "ipg";
85 dmas = <&edma0 0 2>,
86 <&edma0 0 3>;
87 dma-names = "rx","tx";
88 status = "disabled";
89 };
90
91 uart1: serial@40028000 {
92 compatible = "fsl,vf610-lpuart";
93 reg = <0x40028000 0x1000>;
94 clocks = <&clks VF610_CLK_UART1>;
95 clock-names = "ipg";
96 dmas = <&edma0 0 4>,
97 <&edma0 0 5>;
98 dma-names = "rx","tx";
99 status = "disabled";
100 };
101
102 uart2: serial@40029000 {
103 compatible = "fsl,vf610-lpuart";
104 reg = <0x40029000 0x1000>;
105 clocks = <&clks VF610_CLK_UART2>;
106 clock-names = "ipg";
107 dmas = <&edma0 0 6>,
108 <&edma0 0 7>;
109 dma-names = "rx","tx";
110 status = "disabled";
111 };
112
113 uart3: serial@4002a000 {
114 compatible = "fsl,vf610-lpuart";
115 reg = <0x4002a000 0x1000>;
116 clocks = <&clks VF610_CLK_UART3>;
117 clock-names = "ipg";
118 dmas = <&edma0 0 8>,
119 <&edma0 0 9>;
120 dma-names = "rx","tx";
121 status = "disabled";
122 };
123
124 dspi0: dspi0@4002c000 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 compatible = "fsl,vf610-dspi";
128 reg = <0x4002c000 0x1000>;
129 clocks = <&clks VF610_CLK_DSPI0>;
130 clock-names = "dspi";
131 spi-num-chipselects = <5>;
132 status = "disabled";
133 };
134
135 sai2: sai@40031000 {
136 compatible = "fsl,vf610-sai";
137 reg = <0x40031000 0x1000>;
138 clocks = <&clks VF610_CLK_SAI2>;
139 clock-names = "sai";
140 dma-names = "tx", "rx";
141 dmas = <&edma0 0 21>,
142 <&edma0 0 20>;
143 status = "disabled";
144 };
145
146 pit: pit@40037000 {
147 compatible = "fsl,vf610-pit";
148 reg = <0x40037000 0x1000>;
149 clocks = <&clks VF610_CLK_PIT>;
150 clock-names = "pit";
151 };
152
153 pwm0: pwm@40038000 {
154 compatible = "fsl,vf610-ftm-pwm";
155 #pwm-cells = <3>;
156 reg = <0x40038000 0x1000>;
157 clock-names = "ftm_sys", "ftm_ext",
158 "ftm_fix", "ftm_cnt_clk_en";
159 clocks = <&clks VF610_CLK_FTM0>,
160 <&clks VF610_CLK_FTM0_EXT_SEL>,
161 <&clks VF610_CLK_FTM0_FIX_SEL>,
162 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
163 status = "disabled";
164 };
165
166 pwm1: pwm@40039000 {
167 compatible = "fsl,vf610-ftm-pwm";
168 #pwm-cells = <3>;
169 reg = <0x40039000 0x1000>;
170 clock-names = "ftm_sys", "ftm_ext",
171 "ftm_fix", "ftm_cnt_clk_en";
172 clocks = <&clks VF610_CLK_FTM1>,
173 <&clks VF610_CLK_FTM1_EXT_SEL>,
174 <&clks VF610_CLK_FTM1_FIX_SEL>,
175 <&clks VF610_CLK_FTM1_EXT_FIX_EN>;
176 status = "disabled";
177 };
178
179 adc0: adc@4003b000 {
180 compatible = "fsl,vf610-adc";
181 reg = <0x4003b000 0x1000>;
182 clocks = <&clks VF610_CLK_ADC0>;
183 clock-names = "adc";
184 status = "disabled";
185 };
186
187 wdog@4003e000 {
188 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
189 reg = <0x4003e000 0x1000>;
190 clocks = <&clks VF610_CLK_WDT>;
191 clock-names = "wdog";
192 status = "disabled";
193 };
194
195 qspi0: quadspi@40044000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 compatible = "fsl,vf610-qspi";
199 reg = <0x40044000 0x1000>;
200 clocks = <&clks VF610_CLK_QSPI0_EN>,
201 <&clks VF610_CLK_QSPI0>;
202 clock-names = "qspi_en", "qspi";
203 status = "disabled";
204 };
205
206 iomuxc: iomuxc@40048000 {
207 compatible = "fsl,vf610-iomuxc";
208 reg = <0x40048000 0x1000>;
209 #gpio-range-cells = <3>;
210 };
211
212 gpio1: gpio@40049000 {
213 compatible = "fsl,vf610-gpio";
214 reg = <0x40049000 0x1000 0x400ff000 0x40>;
215 gpio-controller;
216 #gpio-cells = <2>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 gpio-ranges = <&iomuxc 0 0 32>;
220 };
221
222 gpio2: gpio@4004a000 {
223 compatible = "fsl,vf610-gpio";
224 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 gpio-ranges = <&iomuxc 0 32 32>;
230 };
231
232 gpio3: gpio@4004b000 {
233 compatible = "fsl,vf610-gpio";
234 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 gpio-ranges = <&iomuxc 0 64 32>;
240 };
241
242 gpio4: gpio@4004c000 {
243 compatible = "fsl,vf610-gpio";
244 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-controller;
248 #interrupt-cells = <2>;
249 gpio-ranges = <&iomuxc 0 96 32>;
250 };
251
252 gpio5: gpio@4004d000 {
253 compatible = "fsl,vf610-gpio";
254 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
255 gpio-controller;
256 #gpio-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
259 gpio-ranges = <&iomuxc 0 128 7>;
260 };
261
262 anatop: anatop@40050000 {
263 compatible = "fsl,vf610-anatop", "syscon";
264 reg = <0x40050000 0x400>;
265 };
266
267 usbphy0: usbphy@40050800 {
268 compatible = "fsl,vf610-usbphy";
269 reg = <0x40050800 0x400>;
270 clocks = <&clks VF610_CLK_USBPHY0>;
271 fsl,anatop = <&anatop>;
272 status = "disabled";
273 };
274
275 usbphy1: usbphy@40050c00 {
276 compatible = "fsl,vf610-usbphy";
277 reg = <0x40050c00 0x400>;
278 clocks = <&clks VF610_CLK_USBPHY1>;
279 fsl,anatop = <&anatop>;
280 status = "disabled";
281 };
282
283 i2c0: i2c@40066000 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible = "fsl,vf610-i2c";
287 reg = <0x40066000 0x1000>;
288 clocks = <&clks VF610_CLK_I2C0>;
289 clock-names = "ipg";
290 dmas = <&edma0 0 50>,
291 <&edma0 0 51>;
292 dma-names = "rx","tx";
293 status = "disabled";
294 };
295
296 clks: ccm@4006b000 {
297 compatible = "fsl,vf610-ccm";
298 reg = <0x4006b000 0x1000>;
299 clocks = <&sxosc>, <&fxosc>;
300 clock-names = "sxosc", "fxosc";
301 #clock-cells = <1>;
302 };
303
304 usbdev0: usb@40034000 {
305 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
306 reg = <0x40034000 0x800>;
307 clocks = <&clks VF610_CLK_USBC0>;
308 fsl,usbphy = <&usbphy0>;
309 fsl,usbmisc = <&usbmisc0 0>;
310 dr_mode = "peripheral";
311 status = "disabled";
312 };
313
314 usbmisc0: usb@40034800 {
315 #index-cells = <1>;
316 compatible = "fsl,vf610-usbmisc";
317 reg = <0x40034800 0x200>;
318 clocks = <&clks VF610_CLK_USBC0>;
319 status = "disabled";
320 };
321 };
322
323 aips1: aips-bus@40080000 {
324 compatible = "fsl,aips-bus", "simple-bus";
325 #address-cells = <1>;
326 #size-cells = <1>;
327 ranges;
328
329 edma1: dma-controller@40098000 {
330 #dma-cells = <2>;
331 compatible = "fsl,vf610-edma";
332 reg = <0x40098000 0x2000>,
333 <0x400a1000 0x1000>,
334 <0x400a2000 0x1000>;
335 dma-channels = <32>;
336 clock-names = "dmamux0", "dmamux1";
337 clocks = <&clks VF610_CLK_DMAMUX2>,
338 <&clks VF610_CLK_DMAMUX3>;
339 status = "disabled";
340 };
341
342 uart4: serial@400a9000 {
343 compatible = "fsl,vf610-lpuart";
344 reg = <0x400a9000 0x1000>;
345 clocks = <&clks VF610_CLK_UART4>;
346 clock-names = "ipg";
347 status = "disabled";
348 };
349
350 uart5: serial@400aa000 {
351 compatible = "fsl,vf610-lpuart";
352 reg = <0x400aa000 0x1000>;
353 clocks = <&clks VF610_CLK_UART5>;
354 clock-names = "ipg";
355 status = "disabled";
356 };
357
358 adc1: adc@400bb000 {
359 compatible = "fsl,vf610-adc";
360 reg = <0x400bb000 0x1000>;
361 clocks = <&clks VF610_CLK_ADC1>;
362 clock-names = "adc";
363 status = "disabled";
364 };
365
366 esdhc1: esdhc@400b2000 {
367 compatible = "fsl,imx53-esdhc";
368 reg = <0x400b2000 0x1000>;
369 clocks = <&clks VF610_CLK_IPG_BUS>,
370 <&clks VF610_CLK_PLATFORM_BUS>,
371 <&clks VF610_CLK_ESDHC1>;
372 clock-names = "ipg", "ahb", "per";
373 status = "disabled";
374 };
375
376 usbh1: usb@400b4000 {
377 compatible = "fsl,vf610-usb", "fsl,imx27-usb";
378 reg = <0x400b4000 0x800>;
379 clocks = <&clks VF610_CLK_USBC1>;
380 fsl,usbphy = <&usbphy1>;
381 fsl,usbmisc = <&usbmisc1 0>;
382 dr_mode = "host";
383 status = "disabled";
384 };
385
386 usbmisc1: usb@400b4800 {
387 #index-cells = <1>;
388 compatible = "fsl,vf610-usbmisc";
389 reg = <0x400b4800 0x200>;
390 clocks = <&clks VF610_CLK_USBC1>;
391 status = "disabled";
392 };
393
394 ftm: ftm@400b8000 {
395 compatible = "fsl,ftm-timer";
396 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
397 clock-names = "ftm-evt", "ftm-src",
398 "ftm-evt-counter-en", "ftm-src-counter-en";
399 clocks = <&clks VF610_CLK_FTM2>,
400 <&clks VF610_CLK_FTM3>,
401 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
402 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
403 status = "disabled";
404 };
405
406 fec0: ethernet@400d0000 {
407 compatible = "fsl,mvf600-fec";
408 reg = <0x400d0000 0x1000>;
409 clocks = <&clks VF610_CLK_ENET0>,
410 <&clks VF610_CLK_ENET0>,
411 <&clks VF610_CLK_ENET>;
412 clock-names = "ipg", "ahb", "ptp";
413 status = "disabled";
414 };
415
416 fec1: ethernet@400d1000 {
417 compatible = "fsl,mvf600-fec";
418 reg = <0x400d1000 0x1000>;
419 clocks = <&clks VF610_CLK_ENET1>,
420 <&clks VF610_CLK_ENET1>,
421 <&clks VF610_CLK_ENET>;
422 clock-names = "ipg", "ahb", "ptp";
423 status = "disabled";
424 };
425
426 can1: flexcan@400d4000 {
427 compatible = "fsl,vf610-flexcan";
428 reg = <0x400d4000 0x4000>;
429 clocks = <&clks VF610_CLK_FLEXCAN1>,
430 <&clks VF610_CLK_FLEXCAN1>;
431 clock-names = "ipg", "per";
432 status = "disabled";
433 };
434
435 };
436 };
437};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index ce2ef5bec4f2..ee3e5d675b05 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -243,7 +243,6 @@
243 clkc: clkc@100 { 243 clkc: clkc@100 {
244 #clock-cells = <1>; 244 #clock-cells = <1>;
245 compatible = "xlnx,ps7-clkc"; 245 compatible = "xlnx,ps7-clkc";
246 ps-clk-frequency = <33333333>;
247 fclk-enable = <0>; 246 fclk-enable = <0>;
248 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 247 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
249 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 248 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
index 0429bbd89fba..ab1dc0a56cdd 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -36,6 +36,7 @@
36 36
37&clkc { 37&clkc {
38 fclk-enable = <0xf>; 38 fclk-enable = <0xf>;
39 ps-clk-frequency = <33333333>;
39}; 40};
40 41
41&gem0 { 42&gem0 {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 94e2cda6f9b6..280f02dd4ddc 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -42,6 +42,10 @@
42 status = "okay"; 42 status = "okay";
43}; 43};
44 44
45&clkc {
46 ps-clk-frequency = <33333333>;
47};
48
45&gem0 { 49&gem0 {
46 status = "okay"; 50 status = "okay";
47 phy-mode = "rgmii-id"; 51 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index a8bbdfbc7093..34f7812d2ee8 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -29,6 +29,10 @@
29 29
30}; 30};
31 31
32&clkc {
33 ps-clk-frequency = <33333333>;
34};
35
32&gem0 { 36&gem0 {
33 status = "okay"; 37 status = "okay";
34 phy-mode = "rgmii-id"; 38 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
index 697779a353ed..1c7cc990b47a 100644
--- a/arch/arm/boot/dts/zynq-zed.dts
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -29,6 +29,10 @@
29 29
30}; 30};
31 31
32&clkc {
33 ps-clk-frequency = <33333333>;
34};
35
32&gem0 { 36&gem0 {
33 status = "okay"; 37 status = "okay";
34 phy-mode = "rgmii-id"; 38 phy-mode = "rgmii-id";
diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts
new file mode 100644
index 000000000000..a9a12ce5023b
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zybo.dts
@@ -0,0 +1,52 @@
1/*
2 * Copyright (C) 2011 - 2014 Xilinx
3 * Copyright (C) 2012 National Instruments Corp.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14/dts-v1/;
15/include/ "zynq-7000.dtsi"
16
17/ {
18 model = "Zynq ZYBO Development Board";
19 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
20
21 memory {
22 device_type = "memory";
23 reg = <0x0 0x20000000>;
24 };
25
26 chosen {
27 bootargs = "console=ttyPS0,115200 earlyprintk";
28 };
29
30};
31
32&clkc {
33 ps-clk-frequency = <50000000>;
34};
35
36&gem0 {
37 status = "okay";
38 phy-mode = "rgmii-id";
39 phy-handle = <&ethernet_phy>;
40
41 ethernet_phy: ethernet-phy@0 {
42 reg = <0>;
43 };
44};
45
46&sdhci0 {
47 status = "okay";
48};
49
50&uart1 {
51 status = "okay";
52};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 11:43:37 -0500