aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts')
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi22
-rw-r--r--arch/arm/boot/dts/exynos4212.dtsi22
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi24
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi22
-rw-r--r--arch/arm/boot/dts/integratorcp.dts6
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts71
-rw-r--r--arch/arm/boot/dts/omap3.dtsi31
-rw-r--r--arch/arm/boot/dts/omap4.dtsi30
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi98
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts14
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts14
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts17
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts15
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts15
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts15
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts15
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts14
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi4
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts15
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi15
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi6
-rw-r--r--arch/arm/boot/dts/versatile-ab.dts12
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts1
-rw-r--r--arch/arm/boot/dts/vt8500.dtsi10
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi10
-rw-r--r--arch/arm/boot/dts/wm8650.dtsi10
-rw-r--r--arch/arm/boot/dts/wm8850.dtsi10
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi45
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts10
33 files changed, 554 insertions, 83 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 234e78f7014e..e35b0a7ac77b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -170,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
170 tegra30-cardhu-a04.dtb \ 170 tegra30-cardhu-a04.dtb \
171 tegra114-dalmore.dtb \ 171 tegra114-dalmore.dtb \
172 tegra114-pluto.dtb 172 tegra114-pluto.dtb
173dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
174 versatile-pb.dtb
173dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ 175dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
174 vexpress-v2p-ca9.dtb \ 176 vexpress-v2p-ca9.dtb \
175 vexpress-v2p-ca15-tc1.dtb \ 177 vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 2feffc70814c..49a2786e00b9 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,6 +47,28 @@
47 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; 47 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
48 }; 48 };
49 49
50 mct@10050000 {
51 compatible = "samsung,exynos4210-mct";
52 reg = <0x10050000 0x800>;
53 interrupt-controller;
54 #interrups-cells = <2>;
55 interrupt-parent = <&mct_map>;
56 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
57 <4 0>, <5 0>;
58
59 mct_map: mct-map {
60 #interrupt-cells = <2>;
61 #address-cells = <0>;
62 #size-cells = <0>;
63 interrupt-map = <0x0 0 &gic 0 57 0>,
64 <0x1 0 &gic 0 69 0>,
65 <0x2 0 &combiner 12 6>,
66 <0x3 0 &combiner 12 7>,
67 <0x4 0 &gic 0 42 0>,
68 <0x5 0 &gic 0 48 0>;
69 };
70 };
71
50 pinctrl_0: pinctrl@11400000 { 72 pinctrl_0: pinctrl@11400000 {
51 compatible = "samsung,exynos4210-pinctrl"; 73 compatible = "samsung,exynos4210-pinctrl";
52 reg = <0x11400000 0x1000>; 74 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c6ae2005961f..36d4299789ef 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,4 +25,26 @@
25 gic:interrupt-controller@10490000 { 25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x8000>; 26 cpu-offset = <0x8000>;
27 }; 27 };
28
29 mct@10050000 {
30 compatible = "samsung,exynos4412-mct";
31 reg = <0x10050000 0x800>;
32 interrupt-controller;
33 #interrups-cells = <2>;
34 interrupt-parent = <&mct_map>;
35 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
36 <4 0>, <5 0>;
37
38 mct_map: mct-map {
39 #interrupt-cells = <2>;
40 #address-cells = <0>;
41 #size-cells = <0>;
42 interrupt-map = <0x0 0 &gic 0 57 0>,
43 <0x1 0 &combiner 12 5>,
44 <0x2 0 &combiner 12 6>,
45 <0x3 0 &combiner 12 7>,
46 <0x4 0 &gic 1 12 0>,
47 <0x5 0 &gic 1 12 0>;
48 };
49 };
28}; 50};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index d7dfe312772a..821c9fdd1e3b 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,4 +25,28 @@
25 gic:interrupt-controller@10490000 { 25 gic:interrupt-controller@10490000 {
26 cpu-offset = <0x4000>; 26 cpu-offset = <0x4000>;
27 }; 27 };
28
29 mct@10050000 {
30 compatible = "samsung,exynos4412-mct";
31 reg = <0x10050000 0x800>;
32 interrupt-controller;
33 #interrups-cells = <2>;
34 interrupt-parent = <&mct_map>;
35 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
36 <4 0>, <5 0>, <6 0>, <7 0>;
37
38 mct_map: mct-map {
39 #interrupt-cells = <2>;
40 #address-cells = <0>;
41 #size-cells = <0>;
42 interrupt-map = <0x0 0 &gic 0 57 0>,
43 <0x1 0 &combiner 12 5>,
44 <0x2 0 &combiner 12 6>,
45 <0x3 0 &combiner 12 7>,
46 <0x4 0 &gic 1 12 0>,
47 <0x5 0 &gic 1 12 0>,
48 <0x6 0 &gic 1 12 0>,
49 <0x7 0 &gic 1 12 0>;
50 };
51 };
28}; 52};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b1ac73e21c80..c60108e0d27e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -69,6 +69,28 @@
69 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; 69 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
70 }; 70 };
71 71
72 mct@101C0000 {
73 compatible = "samsung,exynos4210-mct";
74 reg = <0x101C0000 0x800>;
75 interrupt-controller;
76 #interrups-cells = <2>;
77 interrupt-parent = <&mct_map>;
78 interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
79 <4 0>, <5 0>;
80
81 mct_map: mct-map {
82 #interrupt-cells = <2>;
83 #address-cells = <0>;
84 #size-cells = <0>;
85 interrupt-map = <0x0 0 &combiner 23 3>,
86 <0x1 0 &combiner 23 4>,
87 <0x2 0 &combiner 25 2>,
88 <0x3 0 &combiner 25 3>,
89 <0x4 0 &gic 0 120 0>,
90 <0x5 0 &gic 0 121 0>;
91 };
92 };
93
72 watchdog { 94 watchdog {
73 compatible = "samsung,s3c2410-wdt"; 95 compatible = "samsung,s3c2410-wdt";
74 reg = <0x101D0000 0x100>; 96 reg = <0x101D0000 0x100>;
diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts
index 8b119399025a..ff1aea0ee043 100644
--- a/arch/arm/boot/dts/integratorcp.dts
+++ b/arch/arm/boot/dts/integratorcp.dts
@@ -24,15 +24,15 @@
24 }; 24 };
25 25
26 timer0: timer@13000000 { 26 timer0: timer@13000000 {
27 compatible = "arm,sp804", "arm,primecell"; 27 compatible = "arm,integrator-cp-timer";
28 }; 28 };
29 29
30 timer1: timer@13000100 { 30 timer1: timer@13000100 {
31 compatible = "arm,sp804", "arm,primecell"; 31 compatible = "arm,integrator-cp-timer";
32 }; 32 };
33 33
34 timer2: timer@13000200 { 34 timer2: timer@13000200 {
35 compatible = "arm,sp804", "arm,primecell"; 35 compatible = "arm,integrator-cp-timer";
36 }; 36 };
37 37
38 pic: pic@14000000 { 38 pic: pic@14000000 {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index f624dc85d441..02d23f15fd86 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,6 +38,57 @@
38 }; 38 };
39 }; 39 };
40 40
41 /* HS USB Port 2 RESET */
42 hsusb2_reset: hsusb2_reset_reg {
43 compatible = "regulator-fixed";
44 regulator-name = "hsusb2_reset";
45 regulator-min-microvolt = <3300000>;
46 regulator-max-microvolt = <3300000>;
47 gpio = <&gpio5 19 0>; /* gpio_147 */
48 startup-delay-us = <70000>;
49 enable-active-high;
50 };
51
52 /* HS USB Port 2 Power */
53 hsusb2_power: hsusb2_power_reg {
54 compatible = "regulator-fixed";
55 regulator-name = "hsusb2_vbus";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
59 startup-delay-us = <70000>;
60 };
61
62 /* HS USB Host PHY on PORT 2 */
63 hsusb2_phy: hsusb2_phy {
64 compatible = "usb-nop-xceiv";
65 reset-supply = <&hsusb2_reset>;
66 vcc-supply = <&hsusb2_power>;
67 };
68};
69
70&omap3_pmx_core {
71 pinctrl-names = "default";
72 pinctrl-0 = <
73 &hsusbb2_pins
74 >;
75
76 hsusbb2_pins: pinmux_hsusbb2_pins {
77 pinctrl-single,pins = <
78 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
79 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
80 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
81 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
82 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
83 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
84 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
85 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
86 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
87 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
88 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
89 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
90 >;
91 };
41}; 92};
42 93
43&i2c1 { 94&i2c1 {
@@ -65,3 +116,23 @@
65&mmc3 { 116&mmc3 {
66 status = "disabled"; 117 status = "disabled";
67}; 118};
119
120&usbhshost {
121 port2-mode = "ehci-phy";
122};
123
124&usbhsehci {
125 phys = <0 &hsusb2_phy>;
126};
127
128&twl_gpio {
129 ti,use-leds;
130 /* pullups: BIT(1) */
131 ti,pullups = <0x000002>;
132 /*
133 * pulldowns:
134 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
135 * BIT(15), BIT(16), BIT(17)
136 */
137 ti,pulldowns = <0x03a1c4>;
138};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 1acc26148ffc..a14f74bbce7c 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -397,5 +397,36 @@
397 ti,timer-alwon; 397 ti,timer-alwon;
398 ti,timer-secure; 398 ti,timer-secure;
399 }; 399 };
400
401 usbhstll: usbhstll@48062000 {
402 compatible = "ti,usbhs-tll";
403 reg = <0x48062000 0x1000>;
404 interrupts = <78>;
405 ti,hwmods = "usb_tll_hs";
406 };
407
408 usbhshost: usbhshost@48064000 {
409 compatible = "ti,usbhs-host";
410 reg = <0x48064000 0x400>;
411 ti,hwmods = "usb_host_hs";
412 #address-cells = <1>;
413 #size-cells = <1>;
414 ranges;
415
416 usbhsohci: ohci@48064400 {
417 compatible = "ti,ohci-omap3", "usb-ohci";
418 reg = <0x48064400 0x400>;
419 interrupt-parent = <&intc>;
420 interrupts = <76>;
421 };
422
423 usbhsehci: ehci@48064800 {
424 compatible = "ti,ehci-omap", "usb-ehci";
425 reg = <0x48064800 0x400>;
426 interrupt-parent = <&intc>;
427 interrupts = <77>;
428 };
429 };
430
400 }; 431 };
401}; 432};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 739bb79e410e..b7db1a2b6ca7 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -529,5 +529,35 @@
529 ti,hwmods = "timer11"; 529 ti,hwmods = "timer11";
530 ti,timer-pwm; 530 ti,timer-pwm;
531 }; 531 };
532
533 usbhstll: usbhstll@4a062000 {
534 compatible = "ti,usbhs-tll";
535 reg = <0x4a062000 0x1000>;
536 interrupts = <0 78 0x4>;
537 ti,hwmods = "usb_tll_hs";
538 };
539
540 usbhshost: usbhshost@4a064000 {
541 compatible = "ti,usbhs-host";
542 reg = <0x4a064000 0x800>;
543 ti,hwmods = "usb_host_hs";
544 #address-cells = <1>;
545 #size-cells = <1>;
546 ranges;
547
548 usbhsohci: ohci@4a064800 {
549 compatible = "ti,ohci-omap3", "usb-ohci";
550 reg = <0x4a064800 0x400>;
551 interrupt-parent = <&gic>;
552 interrupts = <0 76 0x4>;
553 };
554
555 usbhsehci: ehci@4a064c00 {
556 compatible = "ti,ehci-omap", "usb-ehci";
557 reg = <0x4a064c00 0x400>;
558 interrupt-parent = <&gic>;
559 interrupts = <0 77 0x4>;
560 };
561 };
532 }; 562 };
533}; 563};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
new file mode 100644
index 000000000000..fe5c6f213271
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -0,0 +1,98 @@
1/*
2 * Device Tree Source for Renesas r8a7779
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "renesas,r8a7779";
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <0>;
25 };
26 cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a9";
29 reg = <1>;
30 };
31 cpu@2 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 reg = <2>;
35 };
36 cpu@3 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <3>;
40 };
41 };
42
43 gic: interrupt-controller@f0001000 {
44 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>;
46 interrupt-controller;
47 reg = <0xf0001000 0x1000>,
48 <0xf0000100 0x100>;
49 };
50
51 i2c0: i2c@0xffc70000 {
52 #address-cells = <1>;
53 #size-cells = <0>;
54 compatible = "renesas,rmobile-iic";
55 reg = <0xffc70000 0x1000>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 79 0x4>;
58 };
59
60 i2c1: i2c@0xffc71000 {
61 #address-cells = <1>;
62 #size-cells = <0>;
63 compatible = "renesas,rmobile-iic";
64 reg = <0xffc71000 0x1000>;
65 interrupt-parent = <&gic>;
66 interrupts = <0 82 0x4>;
67 };
68
69 i2c2: i2c@0xffc72000 {
70 #address-cells = <1>;
71 #size-cells = <0>;
72 compatible = "renesas,rmobile-iic";
73 reg = <0xffc72000 0x1000>;
74 interrupt-parent = <&gic>;
75 interrupts = <0 80 0x4>;
76 };
77
78 i2c3: i2c@0xffc73000 {
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "renesas,rmobile-iic";
82 reg = <0xffc73000 0x1000>;
83 interrupt-parent = <&gic>;
84 interrupts = <0 81 0x4>;
85 };
86
87 thermal@ffc48000 {
88 compatible = "renesas,rcar-thermal";
89 reg = <0xffc48000 0x38>;
90 };
91
92 sata: sata@fc600000 {
93 compatible = "renesas,rcar-sata";
94 reg = <0xfc600000 0x2000>;
95 interrupt-parent = <&gic>;
96 interrupts = <0 100 0x4>;
97 };
98};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a30aca62658a..616990dc92db 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,10 +12,22 @@
12 12
13 serial@70006300 { 13 serial@70006300 {
14 status = "okay"; 14 status = "okay";
15 clock-frequency = <408000000>;
16 }; 15 };
17 16
18 pmc { 17 pmc {
19 nvidia,invert-interrupt; 18 nvidia,invert-interrupt;
20 }; 19 };
20
21 clocks {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 clk32k_in: clock {
27 compatible = "fixed-clock";
28 reg=<0>;
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 };
32 };
21}; 33};
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 9bea8f57aa47..6bbc8efae9c0 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,10 +12,22 @@
12 12
13 serial@70006300 { 13 serial@70006300 {
14 status = "okay"; 14 status = "okay";
15 clock-frequency = <408000000>;
16 }; 15 };
17 16
18 pmc { 17 pmc {
19 nvidia,invert-interrupt; 18 nvidia,invert-interrupt;
20 }; 19 };
20
21 clocks {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 clk32k_in: clock {
27 compatible = "fixed-clock";
28 reg=<0>;
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 };
32 };
21}; 33};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 1dfaf2874c57..c1110a9b2a91 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -24,10 +24,11 @@
24 0 42 0x04 24 0 42 0x04
25 0 121 0x04 25 0 121 0x04
26 0 122 0x04>; 26 0 122 0x04>;
27 clocks = <&tegra_car 5>;
27 }; 28 };
28 29
29 tegra_car: clock { 30 tegra_car: clock {
30 compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; 31 compatible = "nvidia,tegra114-car";
31 reg = <0x60006000 0x1000>; 32 reg = <0x60006000 0x1000>;
32 #clock-cells = <1>; 33 #clock-cells = <1>;
33 }; 34 };
@@ -66,6 +67,7 @@
66 reg-shift = <2>; 67 reg-shift = <2>;
67 interrupts = <0 36 0x04>; 68 interrupts = <0 36 0x04>;
68 status = "disabled"; 69 status = "disabled";
70 clocks = <&tegra_car 6>;
69 }; 71 };
70 72
71 serial@70006040 { 73 serial@70006040 {
@@ -74,6 +76,7 @@
74 reg-shift = <2>; 76 reg-shift = <2>;
75 interrupts = <0 37 0x04>; 77 interrupts = <0 37 0x04>;
76 status = "disabled"; 78 status = "disabled";
79 clocks = <&tegra_car 192>;
77 }; 80 };
78 81
79 serial@70006200 { 82 serial@70006200 {
@@ -82,6 +85,7 @@
82 reg-shift = <2>; 85 reg-shift = <2>;
83 interrupts = <0 46 0x04>; 86 interrupts = <0 46 0x04>;
84 status = "disabled"; 87 status = "disabled";
88 clocks = <&tegra_car 55>;
85 }; 89 };
86 90
87 serial@70006300 { 91 serial@70006300 {
@@ -90,17 +94,21 @@
90 reg-shift = <2>; 94 reg-shift = <2>;
91 interrupts = <0 90 0x04>; 95 interrupts = <0 90 0x04>;
92 status = "disabled"; 96 status = "disabled";
97 clocks = <&tegra_car 65>;
93 }; 98 };
94 99
95 rtc { 100 rtc {
96 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 101 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
97 reg = <0x7000e000 0x100>; 102 reg = <0x7000e000 0x100>;
98 interrupts = <0 2 0x04>; 103 interrupts = <0 2 0x04>;
104 clocks = <&tegra_car 4>;
99 }; 105 };
100 106
101 pmc { 107 pmc {
102 compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; 108 compatible = "nvidia,tegra114-pmc";
103 reg = <0x7000e400 0x400>; 109 reg = <0x7000e400 0x400>;
110 clocks = <&tegra_car 261>, <&clk32k_in>;
111 clock-names = "pclk", "clk32k_in";
104 }; 112 };
105 113
106 iommu { 114 iommu {
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 444162090042..4e3afdef28a8 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -444,7 +444,20 @@
444 }; 444 };
445 445
446 sdhci@c8000600 { 446 sdhci@c8000600 {
447 cd-gpios = <&gpio 23 0>; /* gpio PC7 */ 447 cd-gpios = <&gpio 23 1>; /* gpio PC7 */
448 };
449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
448 }; 461 };
449 462
450 sound { 463 sound {
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 61d027f03617..ae9d5a20834e 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -437,7 +437,7 @@
437 437
438 sdhci@c8000200 { 438 sdhci@c8000200 {
439 status = "okay"; 439 status = "okay";
440 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 440 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
441 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 441 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
442 power-gpios = <&gpio 155 0>; /* gpio PT3 */ 442 power-gpios = <&gpio 155 0>; /* gpio PT3 */
443 bus-width = <4>; 443 bus-width = <4>;
@@ -445,12 +445,25 @@
445 445
446 sdhci@c8000600 { 446 sdhci@c8000600 {
447 status = "okay"; 447 status = "okay";
448 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 448 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
449 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 449 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
450 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 450 power-gpios = <&gpio 70 0>; /* gpio PI6 */
451 bus-width = <8>; 451 bus-width = <8>;
452 }; 452 };
453 453
454 clocks {
455 compatible = "simple-bus";
456 #address-cells = <1>;
457 #size-cells = <0>;
458
459 clk32k_in: clock {
460 compatible = "fixed-clock";
461 reg=<0>;
462 #clock-cells = <0>;
463 clock-frequency = <32768>;
464 };
465 };
466
454 kbc { 467 kbc {
455 status = "okay"; 468 status = "okay";
456 nvidia,debounce-delay-ms = <2>; 469 nvidia,debounce-delay-ms = <2>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 54d6fce00a59..fd60940e4063 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -436,7 +436,7 @@
436 436
437 sdhci@c8000000 { 437 sdhci@c8000000 {
438 status = "okay"; 438 status = "okay";
439 cd-gpios = <&gpio 173 0>; /* gpio PV5 */ 439 cd-gpios = <&gpio 173 1>; /* gpio PV5 */
440 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 440 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
441 power-gpios = <&gpio 169 0>; /* gpio PV1 */ 441 power-gpios = <&gpio 169 0>; /* gpio PV1 */
442 bus-width = <4>; 442 bus-width = <4>;
@@ -447,6 +447,19 @@
447 bus-width = <8>; 447 bus-width = <8>;
448 }; 448 };
449 449
450 clocks {
451 compatible = "simple-bus";
452 #address-cells = <1>;
453 #size-cells = <0>;
454
455 clk32k_in: clock {
456 compatible = "fixed-clock";
457 reg=<0>;
458 #clock-cells = <0>;
459 clock-frequency = <32768>;
460 };
461 };
462
450 gpio-keys { 463 gpio-keys {
451 compatible = "gpio-keys"; 464 compatible = "gpio-keys";
452 465
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 37b3a57ec0f1..4ee700a33ca5 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -584,7 +584,7 @@
584 584
585 sdhci@c8000400 { 585 sdhci@c8000400 {
586 status = "okay"; 586 status = "okay";
587 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 587 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
588 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 588 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
589 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 589 power-gpios = <&gpio 70 0>; /* gpio PI6 */
590 bus-width = <4>; 590 bus-width = <4>;
@@ -595,6 +595,19 @@
595 bus-width = <8>; 595 bus-width = <8>;
596 }; 596 };
597 597
598 clocks {
599 compatible = "simple-bus";
600 #address-cells = <1>;
601 #size-cells = <0>;
602
603 clk32k_in: clock {
604 compatible = "fixed-clock";
605 reg=<0>;
606 #clock-cells = <0>;
607 clock-frequency = <32768>;
608 };
609 };
610
598 gpio-keys { 611 gpio-keys {
599 compatible = "gpio-keys"; 612 compatible = "gpio-keys";
600 613
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 4766abae7a72..c19025725918 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -465,12 +465,25 @@
465 }; 465 };
466 466
467 sdhci@c8000600 { 467 sdhci@c8000600 {
468 cd-gpios = <&gpio 58 0>; /* gpio PH2 */ 468 cd-gpios = <&gpio 58 1>; /* gpio PH2 */
469 wp-gpios = <&gpio 59 0>; /* gpio PH3 */ 469 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
470 bus-width = <4>; 470 bus-width = <4>;
471 status = "okay"; 471 status = "okay";
472 }; 472 };
473 473
474 clocks {
475 compatible = "simple-bus";
476 #address-cells = <1>;
477 #size-cells = <0>;
478
479 clk32k_in: clock {
480 compatible = "fixed-clock";
481 reg=<0>;
482 #clock-cells = <0>;
483 clock-frequency = <32768>;
484 };
485 };
486
474 regulators { 487 regulators {
475 compatible = "simple-bus"; 488 compatible = "simple-bus";
476 489
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 5d79e4fc49a6..a9f3f06580f5 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -325,11 +325,24 @@
325 325
326 sdhci@c8000600 { 326 sdhci@c8000600 {
327 status = "okay"; 327 status = "okay";
328 cd-gpios = <&gpio 121 0>; /* gpio PP1 */ 328 cd-gpios = <&gpio 121 1>; /* gpio PP1 */
329 wp-gpios = <&gpio 122 0>; /* gpio PP2 */ 329 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
330 bus-width = <4>; 330 bus-width = <4>;
331 }; 331 };
332 332
333 clocks {
334 compatible = "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 clk32k_in: clock {
339 compatible = "fixed-clock";
340 reg=<0>;
341 #clock-cells = <0>;
342 clock-frequency = <32768>;
343 };
344 };
345
333 poweroff { 346 poweroff {
334 compatible = "gpio-poweroff"; 347 compatible = "gpio-poweroff";
335 gpios = <&gpio 191 1>; /* gpio PX7, active low */ 348 gpios = <&gpio 191 1>; /* gpio PX7, active low */
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 425c89000c20..f544806e9618 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -520,7 +520,7 @@
520 520
521 sdhci@c8000400 { 521 sdhci@c8000400 {
522 status = "okay"; 522 status = "okay";
523 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 523 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
524 wp-gpios = <&gpio 57 0>; /* gpio PH1 */ 524 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
525 power-gpios = <&gpio 70 0>; /* gpio PI6 */ 525 power-gpios = <&gpio 70 0>; /* gpio PI6 */
526 bus-width = <4>; 526 bus-width = <4>;
@@ -531,6 +531,19 @@
531 bus-width = <8>; 531 bus-width = <8>;
532 }; 532 };
533 533
534 clocks {
535 compatible = "simple-bus";
536 #address-cells = <1>;
537 #size-cells = <0>;
538
539 clk32k_in: clock {
540 compatible = "fixed-clock";
541 reg=<0>;
542 #clock-cells = <0>;
543 clock-frequency = <32768>;
544 };
545 };
546
534 regulators { 547 regulators {
535 compatible = "simple-bus"; 548 compatible = "simple-bus";
536 #address-cells = <1>; 549 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index ea57c0f6dcce..258cf945f515 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -510,6 +510,7 @@
510 510
511 sdhci@c8000400 { 511 sdhci@c8000400 {
512 status = "okay"; 512 status = "okay";
513 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
513 wp-gpios = <&gpio 173 0>; /* gpio PV5 */ 514 wp-gpios = <&gpio 173 0>; /* gpio PV5 */
514 bus-width = <8>; 515 bus-width = <8>;
515 }; 516 };
@@ -519,6 +520,19 @@
519 bus-width = <8>; 520 bus-width = <8>;
520 }; 521 };
521 522
523 clocks {
524 compatible = "simple-bus";
525 #address-cells = <1>;
526 #size-cells = <0>;
527
528 clk32k_in: clock {
529 compatible = "fixed-clock";
530 reg=<0>;
531 #clock-cells = <0>;
532 clock-frequency = <32768>;
533 };
534 };
535
522 kbc { 536 kbc {
523 status = "okay"; 537 status = "okay";
524 nvidia,debounce-delay-ms = <20>; 538 nvidia,debounce-delay-ms = <20>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d2111a..fc7febc2b386 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -145,6 +145,7 @@
145 0 1 0x04 145 0 1 0x04
146 0 41 0x04 146 0 41 0x04
147 0 42 0x04>; 147 0 42 0x04>;
148 clocks = <&tegra_car 5>;
148 }; 149 };
149 150
150 tegra_car: clock { 151 tegra_car: clock {
@@ -304,6 +305,7 @@
304 compatible = "nvidia,tegra20-rtc"; 305 compatible = "nvidia,tegra20-rtc";
305 reg = <0x7000e000 0x100>; 306 reg = <0x7000e000 0x100>;
306 interrupts = <0 2 0x04>; 307 interrupts = <0 2 0x04>;
308 clocks = <&tegra_car 4>;
307 }; 309 };
308 310
309 i2c@7000c000 { 311 i2c@7000c000 {
@@ -416,6 +418,8 @@
416 pmc { 418 pmc {
417 compatible = "nvidia,tegra20-pmc"; 419 compatible = "nvidia,tegra20-pmc";
418 reg = <0x7000e400 0x400>; 420 reg = <0x7000e400 0x400>;
421 clocks = <&tegra_car 110>, <&clk32k_in>;
422 clock-names = "pclk", "clk32k_in";
419 }; 423 };
420 424
421 memory-controller@7000f000 { 425 memory-controller@7000f000 {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 8ff2ff20e4a3..6248b2445b32 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -257,7 +257,7 @@
257 257
258 sdhci@78000000 { 258 sdhci@78000000 {
259 status = "okay"; 259 status = "okay";
260 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 260 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
261 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 261 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
262 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 262 power-gpios = <&gpio 31 0>; /* gpio PD7 */
263 bus-width = <4>; 263 bus-width = <4>;
@@ -268,6 +268,19 @@
268 bus-width = <8>; 268 bus-width = <8>;
269 }; 269 };
270 270
271 clocks {
272 compatible = "simple-bus";
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 clk32k_in: clock {
277 compatible = "fixed-clock";
278 reg=<0>;
279 #clock-cells = <0>;
280 clock-frequency = <32768>;
281 };
282 };
283
271 regulators { 284 regulators {
272 compatible = "simple-bus"; 285 compatible = "simple-bus";
273 #address-cells = <1>; 286 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 17499272a4ef..65bf2b63174e 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -311,7 +311,7 @@
311 311
312 sdhci@78000000 { 312 sdhci@78000000 {
313 status = "okay"; 313 status = "okay";
314 cd-gpios = <&gpio 69 0>; /* gpio PI5 */ 314 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
315 wp-gpios = <&gpio 155 0>; /* gpio PT3 */ 315 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
316 power-gpios = <&gpio 31 0>; /* gpio PD7 */ 316 power-gpios = <&gpio 31 0>; /* gpio PD7 */
317 bus-width = <4>; 317 bus-width = <4>;
@@ -322,6 +322,19 @@
322 bus-width = <8>; 322 bus-width = <8>;
323 }; 323 };
324 324
325 clocks {
326 compatible = "simple-bus";
327 #address-cells = <1>;
328 #size-cells = <0>;
329
330 clk32k_in: clock {
331 compatible = "fixed-clock";
332 reg=<0>;
333 #clock-cells = <0>;
334 clock-frequency = <32768>;
335 };
336 };
337
325 regulators { 338 regulators {
326 compatible = "simple-bus"; 339 compatible = "simple-bus";
327 #address-cells = <1>; 340 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dbf46c272562..9fe7a92b4c85 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -148,6 +148,7 @@
148 0 42 0x04 148 0 42 0x04
149 0 121 0x04 149 0 121 0x04
150 0 122 0x04>; 150 0 122 0x04>;
151 clocks = <&tegra_car 5>;
151 }; 152 };
152 153
153 tegra_car: clock { 154 tegra_car: clock {
@@ -291,6 +292,7 @@
291 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 292 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
292 reg = <0x7000e000 0x100>; 293 reg = <0x7000e000 0x100>;
293 interrupts = <0 2 0x04>; 294 interrupts = <0 2 0x04>;
295 clocks = <&tegra_car 4>;
294 }; 296 };
295 297
296 i2c@7000c000 { 298 i2c@7000c000 {
@@ -423,8 +425,10 @@
423 }; 425 };
424 426
425 pmc { 427 pmc {
426 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; 428 compatible = "nvidia,tegra30-pmc";
427 reg = <0x7000e400 0x400>; 429 reg = <0x7000e400 0x400>;
430 clocks = <&tegra_car 218>, <&clk32k_in>;
431 clock-names = "pclk", "clk32k_in";
428 }; 432 };
429 433
430 memory-controller { 434 memory-controller {
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index e2fe3195c0d1..dde75ae8b4b1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -121,6 +121,18 @@
121 interrupts = <0>; 121 interrupts = <0>;
122 }; 122 };
123 123
124 timer@101e2000 {
125 compatible = "arm,sp804", "arm,primecell";
126 reg = <0x101e2000 0x1000>;
127 interrupts = <4>;
128 };
129
130 timer@101e3000 {
131 compatible = "arm,sp804", "arm,primecell";
132 reg = <0x101e3000 0x1000>;
133 interrupts = <5>;
134 };
135
124 gpio0: gpio@101e4000 { 136 gpio0: gpio@101e4000 {
125 compatible = "arm,pl061", "arm,primecell"; 137 compatible = "arm,pl061", "arm,primecell";
126 reg = <0x101e4000 0x1000>; 138 reg = <0x101e4000 0x1000>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 1420bb14d95c..62d9b225dcce 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -98,6 +98,7 @@
98 <0 49 4>; 98 <0 49 4>;
99 clocks = <&oscclk2>, <&oscclk2>; 99 clocks = <&oscclk2>, <&oscclk2>;
100 clock-names = "timclk", "apb_pclk"; 100 clock-names = "timclk", "apb_pclk";
101 status = "disabled";
101 }; 102 };
102 103
103 watchdog@100e5000 { 104 watchdog@100e5000 {
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index cf31ced46602..e1c3926aca52 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -25,11 +25,13 @@
25 #interrupt-cells = <1>; 25 #interrupt-cells = <1>;
26 }; 26 };
27 27
28 gpio: gpio-controller@d8110000 { 28 pinctrl: pinctrl@d8110000 {
29 compatible = "via,vt8500-gpio"; 29 compatible = "via,vt8500-pinctrl";
30 gpio-controller;
31 reg = <0xd8110000 0x10000>; 30 reg = <0xd8110000 0x10000>;
32 #gpio-cells = <3>; 31 interrupt-controller;
32 #interrupt-cells = <2>;
33 gpio-controller;
34 #gpio-cells = <2>;
33 }; 35 };
34 36
35 pmc@d8130000 { 37 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index e74a1c0fb9a2..bb92ef8ce665 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -40,11 +40,13 @@
40 interrupts = <56 57 58 59 60 61 62 63>; 40 interrupts = <56 57 58 59 60 61 62 63>;
41 }; 41 };
42 42
43 gpio: gpio-controller@d8110000 { 43 pinctrl: pinctrl@d8110000 {
44 compatible = "wm,wm8505-gpio"; 44 compatible = "wm,wm8505-pinctrl";
45 gpio-controller;
46 reg = <0xd8110000 0x10000>; 45 reg = <0xd8110000 0x10000>;
47 #gpio-cells = <3>; 46 interrupt-controller;
47 #interrupt-cells = <2>;
48 gpio-controller;
49 #gpio-cells = <2>;
48 }; 50 };
49 51
50 pmc@d8130000 { 52 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index db3c0a12e052..bb4af580f40b 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -34,11 +34,13 @@
34 interrupts = <56 57 58 59 60 61 62 63>; 34 interrupts = <56 57 58 59 60 61 62 63>;
35 }; 35 };
36 36
37 gpio: gpio-controller@d8110000 { 37 pinctrl: pinctrl@d8110000 {
38 compatible = "wm,wm8650-gpio"; 38 compatible = "wm,wm8650-pinctrl";
39 gpio-controller;
40 reg = <0xd8110000 0x10000>; 39 reg = <0xd8110000 0x10000>;
41 #gpio-cells = <3>; 40 interrupt-controller;
41 #interrupt-cells = <2>;
42 gpio-controller;
43 #gpio-cells = <2>;
42 }; 44 };
43 45
44 pmc@d8130000 { 46 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index e8cbfdc87bba..11cd180c58d3 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -41,11 +41,13 @@
41 interrupts = <56 57 58 59 60 61 62 63>; 41 interrupts = <56 57 58 59 60 61 62 63>;
42 }; 42 };
43 43
44 gpio: gpio-controller@d8110000 { 44 pinctrl: pinctrl@d8110000 {
45 compatible = "wm,wm8650-gpio"; 45 compatible = "wm,wm8850-pinctrl";
46 gpio-controller;
47 reg = <0xd8110000 0x10000>; 46 reg = <0xd8110000 0x10000>;
48 #gpio-cells = <3>; 47 interrupt-controller;
48 #interrupt-cells = <2>;
49 gpio-controller;
50 #gpio-cells = <2>;
49 }; 51 };
50 52
51 pmc@d8130000 { 53 pmc@d8130000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 5914b5654591..51243db2e9e4 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -111,56 +111,23 @@
111 }; 111 };
112 112
113 ttc0: ttc0@f8001000 { 113 ttc0: ttc0@f8001000 {
114 #address-cells = <1>; 114 interrupt-parent = <&intc>;
115 #size-cells = <0>; 115 interrupts = < 0 10 4 0 11 4 0 12 4 >;
116 compatible = "xlnx,ttc"; 116 compatible = "cdns,ttc";
117 reg = <0xF8001000 0x1000>; 117 reg = <0xF8001000 0x1000>;
118 clocks = <&cpu_clk 3>; 118 clocks = <&cpu_clk 3>;
119 clock-names = "cpu_1x"; 119 clock-names = "cpu_1x";
120 clock-ranges; 120 clock-ranges;
121
122 ttc0_0: ttc0.0 {
123 status = "disabled";
124 reg = <0>;
125 interrupts = <0 10 4>;
126 };
127 ttc0_1: ttc0.1 {
128 status = "disabled";
129 reg = <1>;
130 interrupts = <0 11 4>;
131 };
132 ttc0_2: ttc0.2 {
133 status = "disabled";
134 reg = <2>;
135 interrupts = <0 12 4>;
136 };
137 }; 121 };
138 122
139 ttc1: ttc1@f8002000 { 123 ttc1: ttc1@f8002000 {
140 #interrupt-parent = <&intc>; 124 interrupt-parent = <&intc>;
141 #address-cells = <1>; 125 interrupts = < 0 37 4 0 38 4 0 39 4 >;
142 #size-cells = <0>; 126 compatible = "cdns,ttc";
143 compatible = "xlnx,ttc";
144 reg = <0xF8002000 0x1000>; 127 reg = <0xF8002000 0x1000>;
145 clocks = <&cpu_clk 3>; 128 clocks = <&cpu_clk 3>;
146 clock-names = "cpu_1x"; 129 clock-names = "cpu_1x";
147 clock-ranges; 130 clock-ranges;
148
149 ttc1_0: ttc1.0 {
150 status = "disabled";
151 reg = <0>;
152 interrupts = <0 37 4>;
153 };
154 ttc1_1: ttc1.1 {
155 status = "disabled";
156 reg = <1>;
157 interrupts = <0 38 4>;
158 };
159 ttc1_2: ttc1.2 {
160 status = "disabled";
161 reg = <2>;
162 interrupts = <0 39 4>;
163 };
164 }; 131 };
165 }; 132 };
166}; 133};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index c772942a399a..86f44d5b0265 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,13 +32,3 @@
32&ps_clk { 32&ps_clk {
33 clock-frequency = <33333330>; 33 clock-frequency = <33333330>;
34}; 34};
35
36&ttc0_0 {
37 status = "ok";
38 compatible = "xlnx,ttc-counter-clocksource";
39};
40
41&ttc0_1 {
42 status = "ok";
43 compatible = "xlnx,ttc-counter-clockevent";
44};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 04:00:13 -0500