diff options
Diffstat (limited to 'arch/arm/boot/dts/wm8505.dtsi')
-rw-r--r-- | arch/arm/boot/dts/wm8505.dtsi | 45 |
1 files changed, 38 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index e74a1c0fb9a2..b2bf359e852f 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi | |||
@@ -40,11 +40,13 @@ | |||
40 | interrupts = <56 57 58 59 60 61 62 63>; | 40 | interrupts = <56 57 58 59 60 61 62 63>; |
41 | }; | 41 | }; |
42 | 42 | ||
43 | gpio: gpio-controller@d8110000 { | 43 | pinctrl: pinctrl@d8110000 { |
44 | compatible = "wm,wm8505-gpio"; | 44 | compatible = "wm,wm8505-pinctrl"; |
45 | gpio-controller; | ||
46 | reg = <0xd8110000 0x10000>; | 45 | reg = <0xd8110000 0x10000>; |
47 | #gpio-cells = <3>; | 46 | interrupt-controller; |
47 | #interrupt-cells = <2>; | ||
48 | gpio-controller; | ||
49 | #gpio-cells = <2>; | ||
48 | }; | 50 | }; |
49 | 51 | ||
50 | pmc@d8130000 { | 52 | pmc@d8130000 { |
@@ -60,6 +62,19 @@ | |||
60 | clock-frequency = <24000000>; | 62 | clock-frequency = <24000000>; |
61 | }; | 63 | }; |
62 | 64 | ||
65 | ref25: ref25M { | ||
66 | #clock-cells = <0>; | ||
67 | compatible = "fixed-clock"; | ||
68 | clock-frequency = <25000000>; | ||
69 | }; | ||
70 | |||
71 | pllb: pllb { | ||
72 | #clock-cells = <0>; | ||
73 | compatible = "via,vt8500-pll-clock"; | ||
74 | clocks = <&ref25>; | ||
75 | reg = <0x204>; | ||
76 | }; | ||
77 | |||
63 | clkuart0: uart0 { | 78 | clkuart0: uart0 { |
64 | #clock-cells = <0>; | 79 | #clock-cells = <0>; |
65 | compatible = "via,vt8500-device-clock"; | 80 | compatible = "via,vt8500-device-clock"; |
@@ -107,6 +122,16 @@ | |||
107 | enable-reg = <0x250>; | 122 | enable-reg = <0x250>; |
108 | enable-bit = <23>; | 123 | enable-bit = <23>; |
109 | }; | 124 | }; |
125 | |||
126 | clksdhc: sdhc { | ||
127 | #clock-cells = <0>; | ||
128 | compatible = "via,vt8500-device-clock"; | ||
129 | clocks = <&pllb>; | ||
130 | divisor-reg = <0x328>; | ||
131 | divisor-mask = <0x3f>; | ||
132 | enable-reg = <0x254>; | ||
133 | enable-bit = <18>; | ||
134 | }; | ||
110 | }; | 135 | }; |
111 | }; | 136 | }; |
112 | 137 | ||
@@ -128,11 +153,9 @@ | |||
128 | interrupts = <0>; | 153 | interrupts = <0>; |
129 | }; | 154 | }; |
130 | 155 | ||
131 | fb@d8050800 { | 156 | fb: fb@d8050800 { |
132 | compatible = "wm,wm8505-fb"; | 157 | compatible = "wm,wm8505-fb"; |
133 | reg = <0xd8050800 0x200>; | 158 | reg = <0xd8050800 0x200>; |
134 | display = <&display>; | ||
135 | default-mode = <&mode0>; | ||
136 | }; | 159 | }; |
137 | 160 | ||
138 | ge_rops@d8050400 { | 161 | ge_rops@d8050400 { |
@@ -187,5 +210,13 @@ | |||
187 | reg = <0xd8100000 0x10000>; | 210 | reg = <0xd8100000 0x10000>; |
188 | interrupts = <48>; | 211 | interrupts = <48>; |
189 | }; | 212 | }; |
213 | |||
214 | sdhc@d800a000 { | ||
215 | compatible = "wm,wm8505-sdhc"; | ||
216 | reg = <0xd800a000 0x1000>; | ||
217 | interrupts = <20 21>; | ||
218 | clocks = <&clksdhc>; | ||
219 | bus-width = <4>; | ||
220 | }; | ||
190 | }; | 221 | }; |
191 | }; | 222 | }; |