aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts')
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 7e1091d91af8..d12b34ca0568 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -14,8 +14,8 @@
14 arm,hbi = <0x237>; 14 arm,hbi = <0x237>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <1>; 17 #address-cells = <2>;
18 #size-cells = <1>; 18 #size-cells = <2>;
19 19
20 chosen { }; 20 chosen { };
21 21
@@ -47,23 +47,23 @@
47 47
48 memory@80000000 { 48 memory@80000000 {
49 device_type = "memory"; 49 device_type = "memory";
50 reg = <0x80000000 0x40000000>; 50 reg = <0 0x80000000 0 0x40000000>;
51 }; 51 };
52 52
53 hdlcd@2b000000 { 53 hdlcd@2b000000 {
54 compatible = "arm,hdlcd"; 54 compatible = "arm,hdlcd";
55 reg = <0x2b000000 0x1000>; 55 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>; 56 interrupts = <0 85 4>;
57 }; 57 };
58 58
59 memory-controller@2b0a0000 { 59 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell"; 60 compatible = "arm,pl341", "arm,primecell";
61 reg = <0x2b0a0000 0x1000>; 61 reg = <0 0x2b0a0000 0 0x1000>;
62 }; 62 };
63 63
64 wdt@2b060000 { 64 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell"; 65 compatible = "arm,sp805", "arm,primecell";
66 reg = <0x2b060000 0x1000>; 66 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>; 67 interrupts = <98>;
68 }; 68 };
69 69
@@ -72,23 +72,23 @@
72 #interrupt-cells = <3>; 72 #interrupt-cells = <3>;
73 #address-cells = <0>; 73 #address-cells = <0>;
74 interrupt-controller; 74 interrupt-controller;
75 reg = <0x2c001000 0x1000>, 75 reg = <0 0x2c001000 0 0x1000>,
76 <0x2c002000 0x1000>, 76 <0 0x2c002000 0 0x1000>,
77 <0x2c004000 0x2000>, 77 <0 0x2c004000 0 0x2000>,
78 <0x2c006000 0x2000>; 78 <0 0x2c006000 0 0x2000>;
79 interrupts = <1 9 0xf04>; 79 interrupts = <1 9 0xf04>;
80 }; 80 };
81 81
82 memory-controller@7ffd0000 { 82 memory-controller@7ffd0000 {
83 compatible = "arm,pl354", "arm,primecell"; 83 compatible = "arm,pl354", "arm,primecell";
84 reg = <0x7ffd0000 0x1000>; 84 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>, 85 interrupts = <0 86 4>,
86 <0 87 4>; 86 <0 87 4>;
87 }; 87 };
88 88
89 dma@7ffb0000 { 89 dma@7ffb0000 {
90 compatible = "arm,pl330", "arm,primecell"; 90 compatible = "arm,pl330", "arm,primecell";
91 reg = <0x7ffb0000 0x1000>; 91 reg = <0 0x7ffb0000 0 0x1000>;
92 interrupts = <0 92 4>, 92 interrupts = <0 92 4>,
93 <0 88 4>, 93 <0 88 4>,
94 <0 89 4>, 94 <0 89 4>,
@@ -111,12 +111,12 @@
111 }; 111 };
112 112
113 motherboard { 113 motherboard {
114 ranges = <0 0 0x08000000 0x04000000>, 114 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0x14000000 0x04000000>, 115 <1 0 0 0x14000000 0x04000000>,
116 <2 0 0x18000000 0x04000000>, 116 <2 0 0 0x18000000 0x04000000>,
117 <3 0 0x1c000000 0x04000000>, 117 <3 0 0 0x1c000000 0x04000000>,
118 <4 0 0x0c000000 0x04000000>, 118 <4 0 0 0x0c000000 0x04000000>,
119 <5 0 0x10000000 0x04000000>; 119 <5 0 0 0x10000000 0x04000000>;
120 120
121 interrupt-map-mask = <0 0 63>; 121 interrupt-map-mask = <0 0 63>;
122 interrupt-map = <0 0 0 &gic 0 0 4>, 122 interrupt-map = <0 0 0 &gic 0 0 4>,