1 files changed, 154 insertions, 134 deletions

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded605142a..d8783f0fae63 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra30-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra30";
@@ -15,9 +19,9 @@
         host1x {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-                clocks = <&tegra_car 28>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -27,36 +31,36 @@
                 mpe {
                         compatible = "nvidia,tegra30-mpe";
                         reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                        clocks = <&tegra_car 60>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_MPE>;
                 };
 
                 vi {
                         compatible = "nvidia,tegra30-vi";
                         reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                        clocks = <&tegra_car 164>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_VI>;
                 };
 
                 epp {
                         compatible = "nvidia,tegra30-epp";
                         reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                        clocks = <&tegra_car 19>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_EPP>;
                 };
 
                 isp {
                         compatible = "nvidia,tegra30-isp";
                         reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                        clocks = <&tegra_car 23>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_ISP>;
                 };
 
                 gr2d {
                         compatible = "nvidia,tegra30-gr2d";
                         reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                        clocks = <&tegra_car 21>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                 };
 
                 gr3d {
@@ -69,8 +73,9 @@
                 dc@54200000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-                        clocks = <&tegra_car 27>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp1", "parent";
 
                         rgb {
@@ -81,8 +86,9 @@
                 dc@54240000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-                        clocks = <&tegra_car 26>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp2", "parent";
 
                         rgb {
@@ -93,8 +99,9 @@
                 hdmi {
                         compatible = "nvidia,tegra30-hdmi";
                         reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        clocks = <&tegra_car 51>, <&tegra_car 189>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+                                 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                         clock-names = "hdmi", "parent";
                         status = "disabled";
                 };
@@ -102,15 +109,15 @@
                 tvo {
                         compatible = "nvidia,tegra30-tvo";
                         reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        clocks = <&tegra_car 169>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_TVO>;
                         status = "disabled";
                 };
 
                 dsi {
                         compatible = "nvidia,tegra30-dsi";
                         reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA30_CLK_DSIA>;
                         status = "disabled";
                 };
         };
@@ -118,8 +125,9 @@
         timer@50004600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x50040600 0x20>;
-                interrupts = <1 13 0xf04>;
-                clocks = <&tegra_car 214>;
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA30_CLK_TWD>;
         };
 
         intc: interrupt-controller {
@@ -142,13 +150,13 @@
         timer@60005000 {
                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                 reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04
-                              0 121 0x04
-                              0 122 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -160,39 +168,39 @@
         apbdma: dma {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04
-                              0 128 0x04
-                              0 129 0x04
-                              0 130 0x04
-                              0 131 0x04
-                              0 132 0x04
-                              0 133 0x04
-                              0 134 0x04
-                              0 135 0x04
-                              0 136 0x04
-                              0 137 0x04
-                              0 138 0x04
-                              0 139 0x04
-                              0 140 0x04
-                              0 141 0x04
-                              0 142 0x04
-                              0 143 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
         };
 
         ahb: ahb {
@@ -203,14 +211,14 @@
         gpio: gpio {
                 compatible = "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04
-                              0 125 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -235,9 +243,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTA>;
                 status = "disabled";
         };
 
@@ -245,9 +253,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 160>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTB>;
                 status = "disabled";
         };
 
@@ -255,9 +263,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTC>;
                 status = "disabled";
         };
 
@@ -265,9 +273,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTD>;
                 status = "disabled";
         };
 
@@ -275,9 +283,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTE>;
                 status = "disabled";
         };
 
@@ -285,24 +293,25 @@
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA30_CLK_PWM>;
                 status = "disabled";
         };
 
         rtc {
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_RTC>;
         };
 
         i2c@7000c000 {
                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -310,10 +319,11 @@
         i2c@7000c400 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -321,10 +331,11 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -332,10 +343,11 @@
         i2c@7000c700 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 103>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -343,10 +355,11 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -354,81 +367,81 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC1>;
                 status = "disabled";
         };
 
         spi@7000d600 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC2>;
                 status = "disabled";
         };
 
         spi@7000d800 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC3>;
                 status = "disabled";
         };
 
         spi@7000da00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC4>;
                 status = "disabled";
         };
 
         spi@7000dc00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC5>;
                 status = "disabled";
         };
 
         spi@7000de00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC6>;
                 status = "disabled";
         };
 
         kbc {
                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -438,7 +451,7 @@
                        0x7000f03c 0x1b4
                        0x7000f200 0x028
                        0x7000f284 0x17c>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         iommu {
@@ -455,12 +468,19 @@
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
                        0x70080200 0x100>;
-                interrupts = <0 103 0x04>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-                         <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-                         <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-                         <&tegra_car 110>, <&tegra_car 162>;
+                clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA30_CLK_APBIF>,
+                         <&tegra_car TEGRA30_CLK_I2S0>,
+                         <&tegra_car TEGRA30_CLK_I2S1>,
+                         <&tegra_car TEGRA30_CLK_I2S2>,
+                         <&tegra_car TEGRA30_CLK_I2S3>,
+                         <&tegra_car TEGRA30_CLK_I2S4>,
+                         <&tegra_car TEGRA30_CLK_DAM0>,
+                         <&tegra_car TEGRA30_CLK_DAM1>,
+                         <&tegra_car TEGRA30_CLK_DAM2>,
+                         <&tegra_car TEGRA30_CLK_SPDIF_IN>;
                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
                               "spdif_in";
@@ -472,7 +492,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
-                        clocks = <&tegra_car 30>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S0>;
                         status = "disabled";
                 };
 
@@ -480,7 +500,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
-                        clocks = <&tegra_car 11>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S1>;
                         status = "disabled";
                 };
 
@@ -488,7 +508,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
-                        clocks = <&tegra_car 18>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S2>;
                         status = "disabled";
                 };
 
@@ -496,7 +516,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
-                        clocks = <&tegra_car 101>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S3>;
                         status = "disabled";
                 };
 
@@ -504,7 +524,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
-                        clocks = <&tegra_car 102>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S4>;
                         status = "disabled";
                 };
         };
@@ -512,32 +532,32 @@
         sdhci@78000000 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
                 status = "disabled";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
                 status = "disabled";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
                 status = "disabled";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
                 status = "disabled";
         };
 
@@ -572,9 +592,9 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 144 0x04
-                              0 145 0x04
-                              0 146 0x04
-                              0 147 0x04>;
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
         };
 };