diff options
Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra30.dtsi | 120 |
1 files changed, 60 insertions, 60 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index e9792ac03635..5dd6556fce01 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
| @@ -13,8 +13,8 @@ | |||
| 13 | compatible = "arm,cortex-a9-gic"; | 13 | compatible = "arm,cortex-a9-gic"; |
| 14 | interrupt-controller; | 14 | interrupt-controller; |
| 15 | #interrupt-cells = <3>; | 15 | #interrupt-cells = <3>; |
| 16 | reg = < 0x50041000 0x1000 >, | 16 | reg = <0x50041000 0x1000>, |
| 17 | < 0x50040100 0x0100 >; | 17 | <0x50040100 0x0100>; |
| 18 | }; | 18 | }; |
| 19 | 19 | ||
| 20 | pmu { | 20 | pmu { |
| @@ -28,38 +28,38 @@ | |||
| 28 | apbdma: dma@6000a000 { | 28 | apbdma: dma@6000a000 { |
| 29 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; | 29 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
| 30 | reg = <0x6000a000 0x1400>; | 30 | reg = <0x6000a000 0x1400>; |
| 31 | interrupts = < 0 104 0x04 | 31 | interrupts = <0 104 0x04 |
| 32 | 0 105 0x04 | 32 | 0 105 0x04 |
| 33 | 0 106 0x04 | 33 | 0 106 0x04 |
| 34 | 0 107 0x04 | 34 | 0 107 0x04 |
| 35 | 0 108 0x04 | 35 | 0 108 0x04 |
| 36 | 0 109 0x04 | 36 | 0 109 0x04 |
| 37 | 0 110 0x04 | 37 | 0 110 0x04 |
| 38 | 0 111 0x04 | 38 | 0 111 0x04 |
| 39 | 0 112 0x04 | 39 | 0 112 0x04 |
| 40 | 0 113 0x04 | 40 | 0 113 0x04 |
| 41 | 0 114 0x04 | 41 | 0 114 0x04 |
| 42 | 0 115 0x04 | 42 | 0 115 0x04 |
| 43 | 0 116 0x04 | 43 | 0 116 0x04 |
| 44 | 0 117 0x04 | 44 | 0 117 0x04 |
| 45 | 0 118 0x04 | 45 | 0 118 0x04 |
| 46 | 0 119 0x04 | 46 | 0 119 0x04 |
| 47 | 0 128 0x04 | 47 | 0 128 0x04 |
| 48 | 0 129 0x04 | 48 | 0 129 0x04 |
| 49 | 0 130 0x04 | 49 | 0 130 0x04 |
| 50 | 0 131 0x04 | 50 | 0 131 0x04 |
| 51 | 0 132 0x04 | 51 | 0 132 0x04 |
| 52 | 0 133 0x04 | 52 | 0 133 0x04 |
| 53 | 0 134 0x04 | 53 | 0 134 0x04 |
| 54 | 0 135 0x04 | 54 | 0 135 0x04 |
| 55 | 0 136 0x04 | 55 | 0 136 0x04 |
| 56 | 0 137 0x04 | 56 | 0 137 0x04 |
| 57 | 0 138 0x04 | 57 | 0 138 0x04 |
| 58 | 0 139 0x04 | 58 | 0 139 0x04 |
| 59 | 0 140 0x04 | 59 | 0 140 0x04 |
| 60 | 0 141 0x04 | 60 | 0 141 0x04 |
| 61 | 0 142 0x04 | 61 | 0 142 0x04 |
| 62 | 0 143 0x04 >; | 62 | 0 143 0x04>; |
| 63 | }; | 63 | }; |
| 64 | 64 | ||
| 65 | i2c@7000c000 { | 65 | i2c@7000c000 { |
| @@ -67,7 +67,7 @@ | |||
| 67 | #size-cells = <0>; | 67 | #size-cells = <0>; |
| 68 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 68 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 69 | reg = <0x7000C000 0x100>; | 69 | reg = <0x7000C000 0x100>; |
| 70 | interrupts = < 0 38 0x04 >; | 70 | interrupts = <0 38 0x04>; |
| 71 | }; | 71 | }; |
| 72 | 72 | ||
| 73 | i2c@7000c400 { | 73 | i2c@7000c400 { |
| @@ -75,7 +75,7 @@ | |||
| 75 | #size-cells = <0>; | 75 | #size-cells = <0>; |
| 76 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 76 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 77 | reg = <0x7000C400 0x100>; | 77 | reg = <0x7000C400 0x100>; |
| 78 | interrupts = < 0 84 0x04 >; | 78 | interrupts = <0 84 0x04>; |
| 79 | }; | 79 | }; |
| 80 | 80 | ||
| 81 | i2c@7000c500 { | 81 | i2c@7000c500 { |
| @@ -83,7 +83,7 @@ | |||
| 83 | #size-cells = <0>; | 83 | #size-cells = <0>; |
| 84 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 84 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 85 | reg = <0x7000C500 0x100>; | 85 | reg = <0x7000C500 0x100>; |
| 86 | interrupts = < 0 92 0x04 >; | 86 | interrupts = <0 92 0x04>; |
| 87 | }; | 87 | }; |
| 88 | 88 | ||
| 89 | i2c@7000c700 { | 89 | i2c@7000c700 { |
| @@ -91,7 +91,7 @@ | |||
| 91 | #size-cells = <0>; | 91 | #size-cells = <0>; |
| 92 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 92 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 93 | reg = <0x7000c700 0x100>; | 93 | reg = <0x7000c700 0x100>; |
| 94 | interrupts = < 0 120 0x04 >; | 94 | interrupts = <0 120 0x04>; |
| 95 | }; | 95 | }; |
| 96 | 96 | ||
| 97 | i2c@7000d000 { | 97 | i2c@7000d000 { |
| @@ -99,20 +99,20 @@ | |||
| 99 | #size-cells = <0>; | 99 | #size-cells = <0>; |
| 100 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; | 100 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
| 101 | reg = <0x7000D000 0x100>; | 101 | reg = <0x7000D000 0x100>; |
| 102 | interrupts = < 0 53 0x04 >; | 102 | interrupts = <0 53 0x04>; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | gpio: gpio@6000d000 { | 105 | gpio: gpio@6000d000 { |
| 106 | compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; | 106 | compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; |
| 107 | reg = < 0x6000d000 0x1000 >; | 107 | reg = <0x6000d000 0x1000>; |
| 108 | interrupts = < 0 32 0x04 | 108 | interrupts = <0 32 0x04 |
| 109 | 0 33 0x04 | 109 | 0 33 0x04 |
| 110 | 0 34 0x04 | 110 | 0 34 0x04 |
| 111 | 0 35 0x04 | 111 | 0 35 0x04 |
| 112 | 0 55 0x04 | 112 | 0 55 0x04 |
| 113 | 0 87 0x04 | 113 | 0 87 0x04 |
| 114 | 0 89 0x04 | 114 | 0 89 0x04 |
| 115 | 0 125 0x04 >; | 115 | 0 125 0x04>; |
| 116 | #gpio-cells = <2>; | 116 | #gpio-cells = <2>; |
| 117 | gpio-controller; | 117 | gpio-controller; |
| 118 | #interrupt-cells = <2>; | 118 | #interrupt-cells = <2>; |
| @@ -123,71 +123,71 @@ | |||
| 123 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 123 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 124 | reg = <0x70006000 0x40>; | 124 | reg = <0x70006000 0x40>; |
| 125 | reg-shift = <2>; | 125 | reg-shift = <2>; |
| 126 | interrupts = < 0 36 0x04 >; | 126 | interrupts = <0 36 0x04>; |
| 127 | }; | 127 | }; |
| 128 | 128 | ||
| 129 | serial@70006040 { | 129 | serial@70006040 { |
| 130 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 130 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 131 | reg = <0x70006040 0x40>; | 131 | reg = <0x70006040 0x40>; |
| 132 | reg-shift = <2>; | 132 | reg-shift = <2>; |
| 133 | interrupts = < 0 37 0x04 >; | 133 | interrupts = <0 37 0x04>; |
| 134 | }; | 134 | }; |
| 135 | 135 | ||
| 136 | serial@70006200 { | 136 | serial@70006200 { |
| 137 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 137 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 138 | reg = <0x70006200 0x100>; | 138 | reg = <0x70006200 0x100>; |
| 139 | reg-shift = <2>; | 139 | reg-shift = <2>; |
| 140 | interrupts = < 0 46 0x04 >; | 140 | interrupts = <0 46 0x04>; |
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | serial@70006300 { | 143 | serial@70006300 { |
| 144 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 144 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 145 | reg = <0x70006300 0x100>; | 145 | reg = <0x70006300 0x100>; |
| 146 | reg-shift = <2>; | 146 | reg-shift = <2>; |
| 147 | interrupts = < 0 90 0x04 >; | 147 | interrupts = <0 90 0x04>; |
| 148 | }; | 148 | }; |
| 149 | 149 | ||
| 150 | serial@70006400 { | 150 | serial@70006400 { |
| 151 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | 151 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
| 152 | reg = <0x70006400 0x100>; | 152 | reg = <0x70006400 0x100>; |
| 153 | reg-shift = <2>; | 153 | reg-shift = <2>; |
| 154 | interrupts = < 0 91 0x04 >; | 154 | interrupts = <0 91 0x04>; |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | sdhci@78000000 { | 157 | sdhci@78000000 { |
| 158 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 158 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 159 | reg = <0x78000000 0x200>; | 159 | reg = <0x78000000 0x200>; |
| 160 | interrupts = < 0 14 0x04 >; | 160 | interrupts = <0 14 0x04>; |
| 161 | }; | 161 | }; |
| 162 | 162 | ||
| 163 | sdhci@78000200 { | 163 | sdhci@78000200 { |
| 164 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 164 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 165 | reg = <0x78000200 0x200>; | 165 | reg = <0x78000200 0x200>; |
| 166 | interrupts = < 0 15 0x04 >; | 166 | interrupts = <0 15 0x04>; |
| 167 | }; | 167 | }; |
| 168 | 168 | ||
| 169 | sdhci@78000400 { | 169 | sdhci@78000400 { |
| 170 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 170 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 171 | reg = <0x78000400 0x200>; | 171 | reg = <0x78000400 0x200>; |
| 172 | interrupts = < 0 19 0x04 >; | 172 | interrupts = <0 19 0x04>; |
| 173 | }; | 173 | }; |
| 174 | 174 | ||
| 175 | sdhci@78000600 { | 175 | sdhci@78000600 { |
| 176 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 176 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
| 177 | reg = <0x78000600 0x200>; | 177 | reg = <0x78000600 0x200>; |
| 178 | interrupts = < 0 31 0x04 >; | 178 | interrupts = <0 31 0x04>; |
| 179 | }; | 179 | }; |
| 180 | 180 | ||
| 181 | pinmux: pinmux@70000000 { | 181 | pinmux: pinmux@70000000 { |
| 182 | compatible = "nvidia,tegra30-pinmux"; | 182 | compatible = "nvidia,tegra30-pinmux"; |
| 183 | reg = < 0x70000868 0xd0 /* Pad control registers */ | 183 | reg = <0x70000868 0xd0 /* Pad control registers */ |
| 184 | 0x70003000 0x3e0 >; /* Mux registers */ | 184 | 0x70003000 0x3e0>; /* Mux registers */ |
| 185 | }; | 185 | }; |
| 186 | 186 | ||
| 187 | ahub { | 187 | ahub { |
| 188 | compatible = "nvidia,tegra30-ahub"; | 188 | compatible = "nvidia,tegra30-ahub"; |
| 189 | reg = <0x70080000 0x200 0x70080200 0x100>; | 189 | reg = <0x70080000 0x200 0x70080200 0x100>; |
| 190 | interrupts = < 0 103 0x04 >; | 190 | interrupts = <0 103 0x04>; |
| 191 | nvidia,dma-request-selector = <&apbdma 1>; | 191 | nvidia,dma-request-selector = <&apbdma 1>; |
| 192 | 192 | ||
| 193 | ranges; | 193 | ranges; |