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Diffstat (limited to 'arch/arm/boot/dts/tegra30.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi292
1 files changed, 168 insertions, 124 deletions
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15200a949a81..2dcc09e784b5 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -4,190 +4,193 @@
4 compatible = "nvidia,tegra30"; 4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 144 0x04
23 0 145 0x04
24 0 146 0x04
25 0 147 0x04>;
26 };
27
28 apbdma: dma@6000a000 {
29 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
30 reg = <0x6000a000 0x1400>; 17 reg = <0x6000a000 0x1400>;
31 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
32 0 105 0x04 19 0 105 0x04
33 0 106 0x04 20 0 106 0x04
34 0 107 0x04 21 0 107 0x04
35 0 108 0x04 22 0 108 0x04
36 0 109 0x04 23 0 109 0x04
37 0 110 0x04 24 0 110 0x04
38 0 111 0x04 25 0 111 0x04
39 0 112 0x04 26 0 112 0x04
40 0 113 0x04 27 0 113 0x04
41 0 114 0x04 28 0 114 0x04
42 0 115 0x04 29 0 115 0x04
43 0 116 0x04 30 0 116 0x04
44 0 117 0x04 31 0 117 0x04
45 0 118 0x04 32 0 118 0x04
46 0 119 0x04 33 0 119 0x04
47 0 128 0x04 34 0 128 0x04
48 0 129 0x04 35 0 129 0x04
49 0 130 0x04 36 0 130 0x04
50 0 131 0x04 37 0 131 0x04
51 0 132 0x04 38 0 132 0x04
52 0 133 0x04 39 0 133 0x04
53 0 134 0x04 40 0 134 0x04
54 0 135 0x04 41 0 135 0x04
55 0 136 0x04 42 0 136 0x04
56 0 137 0x04 43 0 137 0x04
57 0 138 0x04 44 0 138 0x04
58 0 139 0x04 45 0 139 0x04
59 0 140 0x04 46 0 140 0x04
60 0 141 0x04 47 0 141 0x04
61 0 142 0x04 48 0 142 0x04
62 0 143 0x04 >; 49 0 143 0x04>;
63 }; 50 };
64 51
65 i2c@7000c000 { 52 ahb: ahb {
66 #address-cells = <1>; 53 compatible = "nvidia,tegra30-ahb";
67 #size-cells = <0>; 54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
68 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69 reg = <0x7000C000 0x100>;
70 interrupts = < 0 38 0x04 >;
71 };
72
73 i2c@7000c400 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
77 reg = <0x7000C400 0x100>;
78 interrupts = < 0 84 0x04 >;
79 }; 55 };
80 56
81 i2c@7000c500 { 57 gpio: gpio {
82 #address-cells = <1>;
83 #size-cells = <0>;
84 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
85 reg = <0x7000C500 0x100>;
86 interrupts = < 0 92 0x04 >;
87 };
88
89 i2c@7000c700 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
93 reg = <0x7000c700 0x100>;
94 interrupts = < 0 120 0x04 >;
95 };
96
97 i2c@7000d000 {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
101 reg = <0x7000D000 0x100>;
102 interrupts = < 0 53 0x04 >;
103 };
104
105 gpio: gpio@6000d000 {
106 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; 58 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
107 reg = < 0x6000d000 0x1000 >; 59 reg = <0x6000d000 0x1000>;
108 interrupts = < 0 32 0x04 60 interrupts = <0 32 0x04
109 0 33 0x04 61 0 33 0x04
110 0 34 0x04 62 0 34 0x04
111 0 35 0x04 63 0 35 0x04
112 0 55 0x04 64 0 55 0x04
113 0 87 0x04 65 0 87 0x04
114 0 89 0x04 66 0 89 0x04
115 0 125 0x04 >; 67 0 125 0x04>;
116 #gpio-cells = <2>; 68 #gpio-cells = <2>;
117 gpio-controller; 69 gpio-controller;
118 #interrupt-cells = <2>; 70 #interrupt-cells = <2>;
119 interrupt-controller; 71 interrupt-controller;
120 }; 72 };
121 73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
122 serial@70006000 { 80 serial@70006000 {
123 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 82 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 83 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 84 interrupts = <0 36 0x04>;
85 status = "disable";
127 }; 86 };
128 87
129 serial@70006040 { 88 serial@70006040 {
130 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 89 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 90 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 91 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 92 interrupts = <0 37 0x04>;
93 status = "disable";
134 }; 94 };
135 95
136 serial@70006200 { 96 serial@70006200 {
137 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 97 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 98 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 99 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 100 interrupts = <0 46 0x04>;
101 status = "disable";
141 }; 102 };
142 103
143 serial@70006300 { 104 serial@70006300 {
144 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 105 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 106 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 107 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 108 interrupts = <0 90 0x04>;
109 status = "disable";
148 }; 110 };
149 111
150 serial@70006400 { 112 serial@70006400 {
151 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 113 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 114 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 115 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 116 interrupts = <0 91 0x04>;
117 status = "disable";
155 }; 118 };
156 119
157 sdhci@78000000 { 120 i2c@7000c000 {
158 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 121 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
159 reg = <0x78000000 0x200>; 122 reg = <0x7000c000 0x100>;
160 interrupts = < 0 14 0x04 >; 123 interrupts = <0 38 0x04>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 status = "disable";
161 }; 127 };
162 128
163 sdhci@78000200 { 129 i2c@7000c400 {
164 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 130 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
165 reg = <0x78000200 0x200>; 131 reg = <0x7000c400 0x100>;
166 interrupts = < 0 15 0x04 >; 132 interrupts = <0 84 0x04>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 status = "disable";
167 }; 136 };
168 137
169 sdhci@78000400 { 138 i2c@7000c500 {
170 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 139 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
171 reg = <0x78000400 0x200>; 140 reg = <0x7000c500 0x100>;
172 interrupts = < 0 19 0x04 >; 141 interrupts = <0 92 0x04>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disable";
173 }; 145 };
174 146
175 sdhci@78000600 { 147 i2c@7000c700 {
176 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; 148 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
177 reg = <0x78000600 0x200>; 149 reg = <0x7000c700 0x100>;
178 interrupts = < 0 31 0x04 >; 150 interrupts = <0 120 0x04>;
151 #address-cells = <1>;
152 #size-cells = <0>;
153 status = "disable";
179 }; 154 };
180 155
181 pinmux: pinmux@70000000 { 156 i2c@7000d000 {
182 compatible = "nvidia,tegra30-pinmux"; 157 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
183 reg = < 0x70000868 0xd0 /* Pad control registers */ 158 reg = <0x7000d000 0x100>;
184 0x70003000 0x3e0 >; /* Mux registers */ 159 interrupts = <0 53 0x04>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 status = "disable";
163 };
164
165 pmc {
166 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
167 reg = <0x7000e400 0x400>;
168 };
169
170 mc {
171 compatible = "nvidia,tegra30-mc";
172 reg = <0x7000f000 0x010
173 0x7000f03c 0x1b4
174 0x7000f200 0x028
175 0x7000f284 0x17c>;
176 interrupts = <0 77 0x04>;
177 };
178
179 smmu {
180 compatible = "nvidia,tegra30-smmu";
181 reg = <0x7000f010 0x02c
182 0x7000f1f0 0x010
183 0x7000f228 0x05c>;
184 nvidia,#asids = <4>; /* # of ASIDs */
185 dma-window = <0 0x40000000>; /* IOVA start & length */
186 nvidia,ahb = <&ahb>;
185 }; 187 };
186 188
187 ahub { 189 ahub {
188 compatible = "nvidia,tegra30-ahub"; 190 compatible = "nvidia,tegra30-ahub";
189 reg = <0x70080000 0x200 0x70080200 0x100>; 191 reg = <0x70080000 0x200
190 interrupts = < 0 103 0x04 >; 192 0x70080200 0x100>;
193 interrupts = <0 103 0x04>;
191 nvidia,dma-request-selector = <&apbdma 1>; 194 nvidia,dma-request-selector = <&apbdma 1>;
192 195
193 ranges; 196 ranges;
@@ -198,30 +201,71 @@
198 compatible = "nvidia,tegra30-i2s"; 201 compatible = "nvidia,tegra30-i2s";
199 reg = <0x70080300 0x100>; 202 reg = <0x70080300 0x100>;
200 nvidia,ahub-cif-ids = <4 4>; 203 nvidia,ahub-cif-ids = <4 4>;
204 status = "disable";
201 }; 205 };
202 206
203 tegra_i2s1: i2s@70080400 { 207 tegra_i2s1: i2s@70080400 {
204 compatible = "nvidia,tegra30-i2s"; 208 compatible = "nvidia,tegra30-i2s";
205 reg = <0x70080400 0x100>; 209 reg = <0x70080400 0x100>;
206 nvidia,ahub-cif-ids = <5 5>; 210 nvidia,ahub-cif-ids = <5 5>;
211 status = "disable";
207 }; 212 };
208 213
209 tegra_i2s2: i2s@70080500 { 214 tegra_i2s2: i2s@70080500 {
210 compatible = "nvidia,tegra30-i2s"; 215 compatible = "nvidia,tegra30-i2s";
211 reg = <0x70080500 0x100>; 216 reg = <0x70080500 0x100>;
212 nvidia,ahub-cif-ids = <6 6>; 217 nvidia,ahub-cif-ids = <6 6>;
218 status = "disable";
213 }; 219 };
214 220
215 tegra_i2s3: i2s@70080600 { 221 tegra_i2s3: i2s@70080600 {
216 compatible = "nvidia,tegra30-i2s"; 222 compatible = "nvidia,tegra30-i2s";
217 reg = <0x70080600 0x100>; 223 reg = <0x70080600 0x100>;
218 nvidia,ahub-cif-ids = <7 7>; 224 nvidia,ahub-cif-ids = <7 7>;
225 status = "disable";
219 }; 226 };
220 227
221 tegra_i2s4: i2s@70080700 { 228 tegra_i2s4: i2s@70080700 {
222 compatible = "nvidia,tegra30-i2s"; 229 compatible = "nvidia,tegra30-i2s";
223 reg = <0x70080700 0x100>; 230 reg = <0x70080700 0x100>;
224 nvidia,ahub-cif-ids = <8 8>; 231 nvidia,ahub-cif-ids = <8 8>;
232 status = "disable";
225 }; 233 };
226 }; 234 };
235
236 sdhci@78000000 {
237 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
238 reg = <0x78000000 0x200>;
239 interrupts = <0 14 0x04>;
240 status = "disable";
241 };
242
243 sdhci@78000200 {
244 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
245 reg = <0x78000200 0x200>;
246 interrupts = <0 15 0x04>;
247 status = "disable";
248 };
249
250 sdhci@78000400 {
251 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
252 reg = <0x78000400 0x200>;
253 interrupts = <0 19 0x04>;
254 status = "disable";
255 };
256
257 sdhci@78000600 {
258 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
259 reg = <0x78000600 0x200>;
260 interrupts = <0 31 0x04>;
261 status = "disable";
262 };
263
264 pmu {
265 compatible = "arm,cortex-a9-pmu";
266 interrupts = <0 144 0x04
267 0 145 0x04
268 0 146 0x04
269 0 147 0x04>;
270 };
227}; 271};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 05:57:35 -0500