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Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi136
1 files changed, 119 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index df40b54fd8bc..c90d0aac3afe 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -22,6 +22,8 @@
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
25 27
26 #address-cells = <1>; 28 #address-cells = <1>;
27 #size-cells = <1>; 29 #size-cells = <1>;
@@ -33,6 +35,8 @@
33 reg = <0x54040000 0x00040000>; 35 reg = <0x54040000 0x00040000>;
34 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 36 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
35 clocks = <&tegra_car TEGRA20_CLK_MPE>; 37 clocks = <&tegra_car TEGRA20_CLK_MPE>;
38 resets = <&tegra_car 60>;
39 reset-names = "mpe";
36 }; 40 };
37 41
38 vi { 42 vi {
@@ -40,6 +44,8 @@
40 reg = <0x54080000 0x00040000>; 44 reg = <0x54080000 0x00040000>;
41 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 45 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
42 clocks = <&tegra_car TEGRA20_CLK_VI>; 46 clocks = <&tegra_car TEGRA20_CLK_VI>;
47 resets = <&tegra_car 20>;
48 reset-names = "vi";
43 }; 49 };
44 50
45 epp { 51 epp {
@@ -47,6 +53,8 @@
47 reg = <0x540c0000 0x00040000>; 53 reg = <0x540c0000 0x00040000>;
48 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 54 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
49 clocks = <&tegra_car TEGRA20_CLK_EPP>; 55 clocks = <&tegra_car TEGRA20_CLK_EPP>;
56 resets = <&tegra_car 19>;
57 reset-names = "epp";
50 }; 58 };
51 59
52 isp { 60 isp {
@@ -54,6 +62,8 @@
54 reg = <0x54100000 0x00040000>; 62 reg = <0x54100000 0x00040000>;
55 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA20_CLK_ISP>; 64 clocks = <&tegra_car TEGRA20_CLK_ISP>;
65 resets = <&tegra_car 23>;
66 reset-names = "isp";
57 }; 67 };
58 68
59 gr2d { 69 gr2d {
@@ -61,12 +71,16 @@
61 reg = <0x54140000 0x00040000>; 71 reg = <0x54140000 0x00040000>;
62 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 72 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 73 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
74 resets = <&tegra_car 21>;
75 reset-names = "2d";
64 }; 76 };
65 77
66 gr3d { 78 gr3d {
67 compatible = "nvidia,tegra20-gr3d"; 79 compatible = "nvidia,tegra20-gr3d";
68 reg = <0x54180000 0x00040000>; 80 reg = <0x54180000 0x00040000>;
69 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 81 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
82 resets = <&tegra_car 24>;
83 reset-names = "3d";
70 }; 84 };
71 85
72 dc@54200000 { 86 dc@54200000 {
@@ -75,7 +89,9 @@
75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 89 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 90 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
77 <&tegra_car TEGRA20_CLK_PLL_P>; 91 <&tegra_car TEGRA20_CLK_PLL_P>;
78 clock-names = "disp1", "parent"; 92 clock-names = "dc", "parent";
93 resets = <&tegra_car 27>;
94 reset-names = "dc";
79 95
80 rgb { 96 rgb {
81 status = "disabled"; 97 status = "disabled";
@@ -88,7 +104,9 @@
88 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 104 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
89 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 105 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
90 <&tegra_car TEGRA20_CLK_PLL_P>; 106 <&tegra_car TEGRA20_CLK_PLL_P>;
91 clock-names = "disp2", "parent"; 107 clock-names = "dc", "parent";
108 resets = <&tegra_car 26>;
109 reset-names = "dc";
92 110
93 rgb { 111 rgb {
94 status = "disabled"; 112 status = "disabled";
@@ -102,6 +120,8 @@
102 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 120 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
103 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 121 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
104 clock-names = "hdmi", "parent"; 122 clock-names = "hdmi", "parent";
123 resets = <&tegra_car 51>;
124 reset-names = "hdmi";
105 status = "disabled"; 125 status = "disabled";
106 }; 126 };
107 127
@@ -117,6 +137,8 @@
117 compatible = "nvidia,tegra20-dsi"; 137 compatible = "nvidia,tegra20-dsi";
118 reg = <0x54300000 0x00040000>; 138 reg = <0x54300000 0x00040000>;
119 clocks = <&tegra_car TEGRA20_CLK_DSI>; 139 clocks = <&tegra_car TEGRA20_CLK_DSI>;
140 resets = <&tegra_car 48>;
141 reset-names = "dsi";
120 status = "disabled"; 142 status = "disabled";
121 }; 143 };
122 }; 144 };
@@ -160,6 +182,7 @@
160 compatible = "nvidia,tegra20-car"; 182 compatible = "nvidia,tegra20-car";
161 reg = <0x60006000 0x1000>; 183 reg = <0x60006000 0x1000>;
162 #clock-cells = <1>; 184 #clock-cells = <1>;
185 #reset-cells = <1>;
163 }; 186 };
164 187
165 apbdma: dma { 188 apbdma: dma {
@@ -182,6 +205,9 @@
182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 206 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 207 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
208 resets = <&tegra_car 34>;
209 reset-names = "dma";
210 #dma-cells = <1>;
185 }; 211 };
186 212
187 ahb { 213 ahb {
@@ -222,8 +248,11 @@
222 compatible = "nvidia,tegra20-ac97"; 248 compatible = "nvidia,tegra20-ac97";
223 reg = <0x70002000 0x200>; 249 reg = <0x70002000 0x200>;
224 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
225 nvidia,dma-request-selector = <&apbdma 12>;
226 clocks = <&tegra_car TEGRA20_CLK_AC97>; 251 clocks = <&tegra_car TEGRA20_CLK_AC97>;
252 resets = <&tegra_car 3>;
253 reset-names = "ac97";
254 dmas = <&apbdma 12>, <&apbdma 12>;
255 dma-names = "rx", "tx";
227 status = "disabled"; 256 status = "disabled";
228 }; 257 };
229 258
@@ -231,8 +260,11 @@
231 compatible = "nvidia,tegra20-i2s"; 260 compatible = "nvidia,tegra20-i2s";
232 reg = <0x70002800 0x200>; 261 reg = <0x70002800 0x200>;
233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
234 nvidia,dma-request-selector = <&apbdma 2>;
235 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 263 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
264 resets = <&tegra_car 11>;
265 reset-names = "i2s";
266 dmas = <&apbdma 2>, <&apbdma 2>;
267 dma-names = "rx", "tx";
236 status = "disabled"; 268 status = "disabled";
237 }; 269 };
238 270
@@ -240,8 +272,11 @@
240 compatible = "nvidia,tegra20-i2s"; 272 compatible = "nvidia,tegra20-i2s";
241 reg = <0x70002a00 0x200>; 273 reg = <0x70002a00 0x200>;
242 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 nvidia,dma-request-selector = <&apbdma 1>;
244 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 275 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
276 resets = <&tegra_car 18>;
277 reset-names = "i2s";
278 dmas = <&apbdma 1>, <&apbdma 1>;
279 dma-names = "rx", "tx";
245 status = "disabled"; 280 status = "disabled";
246 }; 281 };
247 282
@@ -257,8 +292,11 @@
257 reg = <0x70006000 0x40>; 292 reg = <0x70006000 0x40>;
258 reg-shift = <2>; 293 reg-shift = <2>;
259 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
260 nvidia,dma-request-selector = <&apbdma 8>;
261 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 295 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
296 resets = <&tegra_car 6>;
297 reset-names = "serial";
298 dmas = <&apbdma 8>, <&apbdma 8>;
299 dma-names = "rx", "tx";
262 status = "disabled"; 300 status = "disabled";
263 }; 301 };
264 302
@@ -267,8 +305,11 @@
267 reg = <0x70006040 0x40>; 305 reg = <0x70006040 0x40>;
268 reg-shift = <2>; 306 reg-shift = <2>;
269 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
270 nvidia,dma-request-selector = <&apbdma 9>;
271 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 308 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
309 resets = <&tegra_car 7>;
310 reset-names = "serial";
311 dmas = <&apbdma 9>, <&apbdma 9>;
312 dma-names = "rx", "tx";
272 status = "disabled"; 313 status = "disabled";
273 }; 314 };
274 315
@@ -277,8 +318,11 @@
277 reg = <0x70006200 0x100>; 318 reg = <0x70006200 0x100>;
278 reg-shift = <2>; 319 reg-shift = <2>;
279 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
280 nvidia,dma-request-selector = <&apbdma 10>;
281 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 321 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
322 resets = <&tegra_car 55>;
323 reset-names = "serial";
324 dmas = <&apbdma 10>, <&apbdma 10>;
325 dma-names = "rx", "tx";
282 status = "disabled"; 326 status = "disabled";
283 }; 327 };
284 328
@@ -287,8 +331,11 @@
287 reg = <0x70006300 0x100>; 331 reg = <0x70006300 0x100>;
288 reg-shift = <2>; 332 reg-shift = <2>;
289 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
290 nvidia,dma-request-selector = <&apbdma 19>;
291 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 334 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
335 resets = <&tegra_car 65>;
336 reset-names = "serial";
337 dmas = <&apbdma 19>, <&apbdma 19>;
338 dma-names = "rx", "tx";
292 status = "disabled"; 339 status = "disabled";
293 }; 340 };
294 341
@@ -297,8 +344,11 @@
297 reg = <0x70006400 0x100>; 344 reg = <0x70006400 0x100>;
298 reg-shift = <2>; 345 reg-shift = <2>;
299 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 346 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
300 nvidia,dma-request-selector = <&apbdma 20>;
301 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 347 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
348 resets = <&tegra_car 66>;
349 reset-names = "serial";
350 dmas = <&apbdma 20>, <&apbdma 20>;
351 dma-names = "rx", "tx";
302 status = "disabled"; 352 status = "disabled";
303 }; 353 };
304 354
@@ -307,6 +357,8 @@
307 reg = <0x7000a000 0x100>; 357 reg = <0x7000a000 0x100>;
308 #pwm-cells = <2>; 358 #pwm-cells = <2>;
309 clocks = <&tegra_car TEGRA20_CLK_PWM>; 359 clocks = <&tegra_car TEGRA20_CLK_PWM>;
360 resets = <&tegra_car 17>;
361 reset-names = "pwm";
310 status = "disabled"; 362 status = "disabled";
311 }; 363 };
312 364
@@ -326,6 +378,10 @@
326 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 378 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
327 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 379 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
328 clock-names = "div-clk", "fast-clk"; 380 clock-names = "div-clk", "fast-clk";
381 resets = <&tegra_car 12>;
382 reset-names = "i2c";
383 dmas = <&apbdma 21>, <&apbdma 21>;
384 dma-names = "rx", "tx";
329 status = "disabled"; 385 status = "disabled";
330 }; 386 };
331 387
@@ -333,10 +389,13 @@
333 compatible = "nvidia,tegra20-sflash"; 389 compatible = "nvidia,tegra20-sflash";
334 reg = <0x7000c380 0x80>; 390 reg = <0x7000c380 0x80>;
335 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
336 nvidia,dma-request-selector = <&apbdma 11>;
337 #address-cells = <1>; 392 #address-cells = <1>;
338 #size-cells = <0>; 393 #size-cells = <0>;
339 clocks = <&tegra_car TEGRA20_CLK_SPI>; 394 clocks = <&tegra_car TEGRA20_CLK_SPI>;
395 resets = <&tegra_car 43>;
396 reset-names = "spi";
397 dmas = <&apbdma 11>, <&apbdma 11>;
398 dma-names = "rx", "tx";
340 status = "disabled"; 399 status = "disabled";
341 }; 400 };
342 401
@@ -349,6 +408,10 @@
349 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 408 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
350 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 409 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
351 clock-names = "div-clk", "fast-clk"; 410 clock-names = "div-clk", "fast-clk";
411 resets = <&tegra_car 54>;
412 reset-names = "i2c";
413 dmas = <&apbdma 22>, <&apbdma 22>;
414 dma-names = "rx", "tx";
352 status = "disabled"; 415 status = "disabled";
353 }; 416 };
354 417
@@ -361,6 +424,10 @@
361 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 424 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
362 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 425 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
363 clock-names = "div-clk", "fast-clk"; 426 clock-names = "div-clk", "fast-clk";
427 resets = <&tegra_car 67>;
428 reset-names = "i2c";
429 dmas = <&apbdma 23>, <&apbdma 23>;
430 dma-names = "rx", "tx";
364 status = "disabled"; 431 status = "disabled";
365 }; 432 };
366 433
@@ -373,6 +440,10 @@
373 clocks = <&tegra_car TEGRA20_CLK_DVC>, 440 clocks = <&tegra_car TEGRA20_CLK_DVC>,
374 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 441 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
375 clock-names = "div-clk", "fast-clk"; 442 clock-names = "div-clk", "fast-clk";
443 resets = <&tegra_car 47>;
444 reset-names = "i2c";
445 dmas = <&apbdma 24>, <&apbdma 24>;
446 dma-names = "rx", "tx";
376 status = "disabled"; 447 status = "disabled";
377 }; 448 };
378 449
@@ -380,10 +451,13 @@
380 compatible = "nvidia,tegra20-slink"; 451 compatible = "nvidia,tegra20-slink";
381 reg = <0x7000d400 0x200>; 452 reg = <0x7000d400 0x200>;
382 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 453 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
383 nvidia,dma-request-selector = <&apbdma 15>;
384 #address-cells = <1>; 454 #address-cells = <1>;
385 #size-cells = <0>; 455 #size-cells = <0>;
386 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 456 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
457 resets = <&tegra_car 41>;
458 reset-names = "spi";
459 dmas = <&apbdma 15>, <&apbdma 15>;
460 dma-names = "rx", "tx";
387 status = "disabled"; 461 status = "disabled";
388 }; 462 };
389 463
@@ -391,10 +465,13 @@
391 compatible = "nvidia,tegra20-slink"; 465 compatible = "nvidia,tegra20-slink";
392 reg = <0x7000d600 0x200>; 466 reg = <0x7000d600 0x200>;
393 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 467 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
394 nvidia,dma-request-selector = <&apbdma 16>;
395 #address-cells = <1>; 468 #address-cells = <1>;
396 #size-cells = <0>; 469 #size-cells = <0>;
397 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 470 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
471 resets = <&tegra_car 44>;
472 reset-names = "spi";
473 dmas = <&apbdma 16>, <&apbdma 16>;
474 dma-names = "rx", "tx";
398 status = "disabled"; 475 status = "disabled";
399 }; 476 };
400 477
@@ -402,10 +479,13 @@
402 compatible = "nvidia,tegra20-slink"; 479 compatible = "nvidia,tegra20-slink";
403 reg = <0x7000d800 0x200>; 480 reg = <0x7000d800 0x200>;
404 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
405 nvidia,dma-request-selector = <&apbdma 17>;
406 #address-cells = <1>; 482 #address-cells = <1>;
407 #size-cells = <0>; 483 #size-cells = <0>;
408 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 484 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
485 resets = <&tegra_car 46>;
486 reset-names = "spi";
487 dmas = <&apbdma 17>, <&apbdma 17>;
488 dma-names = "rx", "tx";
409 status = "disabled"; 489 status = "disabled";
410 }; 490 };
411 491
@@ -413,10 +493,13 @@
413 compatible = "nvidia,tegra20-slink"; 493 compatible = "nvidia,tegra20-slink";
414 reg = <0x7000da00 0x200>; 494 reg = <0x7000da00 0x200>;
415 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 495 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
416 nvidia,dma-request-selector = <&apbdma 18>;
417 #address-cells = <1>; 496 #address-cells = <1>;
418 #size-cells = <0>; 497 #size-cells = <0>;
419 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 498 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
499 resets = <&tegra_car 68>;
500 reset-names = "spi";
501 dmas = <&apbdma 18>, <&apbdma 18>;
502 dma-names = "rx", "tx";
420 status = "disabled"; 503 status = "disabled";
421 }; 504 };
422 505
@@ -425,6 +508,8 @@
425 reg = <0x7000e200 0x100>; 508 reg = <0x7000e200 0x100>;
426 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&tegra_car TEGRA20_CLK_KBC>; 510 clocks = <&tegra_car TEGRA20_CLK_KBC>;
511 resets = <&tegra_car 36>;
512 reset-names = "kbc";
428 status = "disabled"; 513 status = "disabled";
429 }; 514 };
430 515
@@ -478,9 +563,12 @@
478 563
479 clocks = <&tegra_car TEGRA20_CLK_PEX>, 564 clocks = <&tegra_car TEGRA20_CLK_PEX>,
480 <&tegra_car TEGRA20_CLK_AFI>, 565 <&tegra_car TEGRA20_CLK_AFI>,
481 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
482 <&tegra_car TEGRA20_CLK_PLL_E>; 566 <&tegra_car TEGRA20_CLK_PLL_E>;
483 clock-names = "pex", "afi", "pcie_xclk", "pll_e"; 567 clock-names = "pex", "afi", "pll_e";
568 resets = <&tegra_car 70>,
569 <&tegra_car 72>,
570 <&tegra_car 74>;
571 reset-names = "pex", "afi", "pcie_x";
484 status = "disabled"; 572 status = "disabled";
485 573
486 pci@1,0 { 574 pci@1,0 {
@@ -517,6 +605,8 @@
517 phy_type = "utmi"; 605 phy_type = "utmi";
518 nvidia,has-legacy-mode; 606 nvidia,has-legacy-mode;
519 clocks = <&tegra_car TEGRA20_CLK_USBD>; 607 clocks = <&tegra_car TEGRA20_CLK_USBD>;
608 resets = <&tegra_car 22>;
609 reset-names = "usb";
520 nvidia,needs-double-reset; 610 nvidia,needs-double-reset;
521 nvidia,phy = <&phy1>; 611 nvidia,phy = <&phy1>;
522 status = "disabled"; 612 status = "disabled";
@@ -548,6 +638,8 @@
548 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 638 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
549 phy_type = "ulpi"; 639 phy_type = "ulpi";
550 clocks = <&tegra_car TEGRA20_CLK_USB2>; 640 clocks = <&tegra_car TEGRA20_CLK_USB2>;
641 resets = <&tegra_car 58>;
642 reset-names = "usb";
551 nvidia,phy = <&phy2>; 643 nvidia,phy = <&phy2>;
552 status = "disabled"; 644 status = "disabled";
553 }; 645 };
@@ -569,6 +661,8 @@
569 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 661 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
570 phy_type = "utmi"; 662 phy_type = "utmi";
571 clocks = <&tegra_car TEGRA20_CLK_USB3>; 663 clocks = <&tegra_car TEGRA20_CLK_USB3>;
664 resets = <&tegra_car 59>;
665 reset-names = "usb";
572 nvidia,phy = <&phy3>; 666 nvidia,phy = <&phy3>;
573 status = "disabled"; 667 status = "disabled";
574 }; 668 };
@@ -597,6 +691,8 @@
597 reg = <0xc8000000 0x200>; 691 reg = <0xc8000000 0x200>;
598 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 692 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 693 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
694 resets = <&tegra_car 14>;
695 reset-names = "sdhci";
600 status = "disabled"; 696 status = "disabled";
601 }; 697 };
602 698
@@ -605,6 +701,8 @@
605 reg = <0xc8000200 0x200>; 701 reg = <0xc8000200 0x200>;
606 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 702 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 703 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
704 resets = <&tegra_car 9>;
705 reset-names = "sdhci";
608 status = "disabled"; 706 status = "disabled";
609 }; 707 };
610 708
@@ -613,6 +711,8 @@
613 reg = <0xc8000400 0x200>; 711 reg = <0xc8000400 0x200>;
614 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 712 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 713 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
714 resets = <&tegra_car 69>;
715 reset-names = "sdhci";
616 status = "disabled"; 716 status = "disabled";
617 }; 717 };
618 718
@@ -621,6 +721,8 @@
621 reg = <0xc8000600 0x200>; 721 reg = <0xc8000600 0x200>;
622 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 722 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 723 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
724 resets = <&tegra_car 15>;
725 reset-names = "sdhci";
624 status = "disabled"; 726 status = "disabled";
625 }; 727 };
626 728
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 02:55:17 -0500