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Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi275
1 files changed, 155 insertions, 120 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 108e894a8926..c417d67e9027 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -4,207 +4,242 @@
4 compatible = "nvidia,tegra20"; 4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>; 5 interrupt-parent = <&intc>;
6 6
7 pmc@7000f400 { 7 intc: interrupt-controller {
8 compatible = "nvidia,tegra20-pmc";
9 reg = <0x7000e400 0x400>;
10 };
11
12 intc: interrupt-controller@50041000 {
13 compatible = "arm,cortex-a9-gic"; 8 compatible = "arm,cortex-a9-gic";
9 reg = <0x50041000 0x1000
10 0x50040100 0x0100>;
14 interrupt-controller; 11 interrupt-controller;
15 #interrupt-cells = <3>; 12 #interrupt-cells = <3>;
16 reg = < 0x50041000 0x1000 >,
17 < 0x50040100 0x0100 >;
18 }; 13 };
19 14
20 pmu { 15 apbdma: dma {
21 compatible = "arm,cortex-a9-pmu";
22 interrupts = <0 56 0x04
23 0 57 0x04>;
24 };
25
26 apbdma: dma@6000a000 {
27 compatible = "nvidia,tegra20-apbdma"; 16 compatible = "nvidia,tegra20-apbdma";
28 reg = <0x6000a000 0x1200>; 17 reg = <0x6000a000 0x1200>;
29 interrupts = < 0 104 0x04 18 interrupts = <0 104 0x04
30 0 105 0x04 19 0 105 0x04
31 0 106 0x04 20 0 106 0x04
32 0 107 0x04 21 0 107 0x04
33 0 108 0x04 22 0 108 0x04
34 0 109 0x04 23 0 109 0x04
35 0 110 0x04 24 0 110 0x04
36 0 111 0x04 25 0 111 0x04
37 0 112 0x04 26 0 112 0x04
38 0 113 0x04 27 0 113 0x04
39 0 114 0x04 28 0 114 0x04
40 0 115 0x04 29 0 115 0x04
41 0 116 0x04 30 0 116 0x04
42 0 117 0x04 31 0 117 0x04
43 0 118 0x04 32 0 118 0x04
44 0 119 0x04 >; 33 0 119 0x04>;
45 }; 34 };
46 35
47 i2c@7000c000 { 36 ahb {
48 #address-cells = <1>; 37 compatible = "nvidia,tegra20-ahb";
49 #size-cells = <0>; 38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
50 compatible = "nvidia,tegra20-i2c"; 39 };
51 reg = <0x7000C000 0x100>; 40
52 interrupts = < 0 38 0x04 >; 41 gpio: gpio {
53 }; 42 compatible = "nvidia,tegra20-gpio";
54 43 reg = <0x6000d000 0x1000>;
55 i2c@7000c400 { 44 interrupts = <0 32 0x04
56 #address-cells = <1>; 45 0 33 0x04
57 #size-cells = <0>; 46 0 34 0x04
58 compatible = "nvidia,tegra20-i2c"; 47 0 35 0x04
59 reg = <0x7000C400 0x100>; 48 0 55 0x04
60 interrupts = < 0 84 0x04 >; 49 0 87 0x04
50 0 89 0x04>;
51 #gpio-cells = <2>;
52 gpio-controller;
53 #interrupt-cells = <2>;
54 interrupt-controller;
61 }; 55 };
62 56
63 i2c@7000c500 { 57 pinmux: pinmux {
64 #address-cells = <1>; 58 compatible = "nvidia,tegra20-pinmux";
65 #size-cells = <0>; 59 reg = <0x70000014 0x10 /* Tri-state registers */
66 compatible = "nvidia,tegra20-i2c"; 60 0x70000080 0x20 /* Mux registers */
67 reg = <0x7000C500 0x100>; 61 0x700000a0 0x14 /* Pull-up/down registers */
68 interrupts = < 0 92 0x04 >; 62 0x70000868 0xa8>; /* Pad control registers */
69 }; 63 };
70 64
71 i2c@7000d000 { 65 das {
72 #address-cells = <1>; 66 compatible = "nvidia,tegra20-das";
73 #size-cells = <0>; 67 reg = <0x70000c00 0x80>;
74 compatible = "nvidia,tegra20-i2c-dvc";
75 reg = <0x7000D000 0x200>;
76 interrupts = < 0 53 0x04 >;
77 }; 68 };
78 69
79 tegra_i2s1: i2s@70002800 { 70 tegra_i2s1: i2s@70002800 {
80 compatible = "nvidia,tegra20-i2s"; 71 compatible = "nvidia,tegra20-i2s";
81 reg = <0x70002800 0x200>; 72 reg = <0x70002800 0x200>;
82 interrupts = < 0 13 0x04 >; 73 interrupts = <0 13 0x04>;
83 nvidia,dma-request-selector = < &apbdma 2 >; 74 nvidia,dma-request-selector = <&apbdma 2>;
75 status = "disable";
84 }; 76 };
85 77
86 tegra_i2s2: i2s@70002a00 { 78 tegra_i2s2: i2s@70002a00 {
87 compatible = "nvidia,tegra20-i2s"; 79 compatible = "nvidia,tegra20-i2s";
88 reg = <0x70002a00 0x200>; 80 reg = <0x70002a00 0x200>;
89 interrupts = < 0 3 0x04 >; 81 interrupts = <0 3 0x04>;
90 nvidia,dma-request-selector = < &apbdma 1 >; 82 nvidia,dma-request-selector = <&apbdma 1>;
91 }; 83 status = "disable";
92
93 das@70000c00 {
94 compatible = "nvidia,tegra20-das";
95 reg = <0x70000c00 0x80>;
96 };
97
98 gpio: gpio@6000d000 {
99 compatible = "nvidia,tegra20-gpio";
100 reg = < 0x6000d000 0x1000 >;
101 interrupts = < 0 32 0x04
102 0 33 0x04
103 0 34 0x04
104 0 35 0x04
105 0 55 0x04
106 0 87 0x04
107 0 89 0x04 >;
108 #gpio-cells = <2>;
109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 };
113
114 pinmux: pinmux@70000000 {
115 compatible = "nvidia,tegra20-pinmux";
116 reg = < 0x70000014 0x10 /* Tri-state registers */
117 0x70000080 0x20 /* Mux registers */
118 0x700000a0 0x14 /* Pull-up/down registers */
119 0x70000868 0xa8 >; /* Pad control registers */
120 }; 84 };
121 85
122 serial@70006000 { 86 serial@70006000 {
123 compatible = "nvidia,tegra20-uart"; 87 compatible = "nvidia,tegra20-uart";
124 reg = <0x70006000 0x40>; 88 reg = <0x70006000 0x40>;
125 reg-shift = <2>; 89 reg-shift = <2>;
126 interrupts = < 0 36 0x04 >; 90 interrupts = <0 36 0x04>;
91 status = "disable";
127 }; 92 };
128 93
129 serial@70006040 { 94 serial@70006040 {
130 compatible = "nvidia,tegra20-uart"; 95 compatible = "nvidia,tegra20-uart";
131 reg = <0x70006040 0x40>; 96 reg = <0x70006040 0x40>;
132 reg-shift = <2>; 97 reg-shift = <2>;
133 interrupts = < 0 37 0x04 >; 98 interrupts = <0 37 0x04>;
99 status = "disable";
134 }; 100 };
135 101
136 serial@70006200 { 102 serial@70006200 {
137 compatible = "nvidia,tegra20-uart"; 103 compatible = "nvidia,tegra20-uart";
138 reg = <0x70006200 0x100>; 104 reg = <0x70006200 0x100>;
139 reg-shift = <2>; 105 reg-shift = <2>;
140 interrupts = < 0 46 0x04 >; 106 interrupts = <0 46 0x04>;
107 status = "disable";
141 }; 108 };
142 109
143 serial@70006300 { 110 serial@70006300 {
144 compatible = "nvidia,tegra20-uart"; 111 compatible = "nvidia,tegra20-uart";
145 reg = <0x70006300 0x100>; 112 reg = <0x70006300 0x100>;
146 reg-shift = <2>; 113 reg-shift = <2>;
147 interrupts = < 0 90 0x04 >; 114 interrupts = <0 90 0x04>;
115 status = "disable";
148 }; 116 };
149 117
150 serial@70006400 { 118 serial@70006400 {
151 compatible = "nvidia,tegra20-uart"; 119 compatible = "nvidia,tegra20-uart";
152 reg = <0x70006400 0x100>; 120 reg = <0x70006400 0x100>;
153 reg-shift = <2>; 121 reg-shift = <2>;
154 interrupts = < 0 91 0x04 >; 122 interrupts = <0 91 0x04>;
123 status = "disable";
155 }; 124 };
156 125
157 emc@7000f400 { 126 i2c@7000c000 {
127 compatible = "nvidia,tegra20-i2c";
128 reg = <0x7000c000 0x100>;
129 interrupts = <0 38 0x04>;
158 #address-cells = <1>; 130 #address-cells = <1>;
159 #size-cells = <0>; 131 #size-cells = <0>;
160 compatible = "nvidia,tegra20-emc"; 132 status = "disable";
161 reg = <0x7000f400 0x200>;
162 }; 133 };
163 134
164 sdhci@c8000000 { 135 i2c@7000c400 {
165 compatible = "nvidia,tegra20-sdhci"; 136 compatible = "nvidia,tegra20-i2c";
166 reg = <0xc8000000 0x200>; 137 reg = <0x7000c400 0x100>;
167 interrupts = < 0 14 0x04 >; 138 interrupts = <0 84 0x04>;
139 #address-cells = <1>;
140 #size-cells = <0>;
141 status = "disable";
168 }; 142 };
169 143
170 sdhci@c8000200 { 144 i2c@7000c500 {
171 compatible = "nvidia,tegra20-sdhci"; 145 compatible = "nvidia,tegra20-i2c";
172 reg = <0xc8000200 0x200>; 146 reg = <0x7000c500 0x100>;
173 interrupts = < 0 15 0x04 >; 147 interrupts = <0 92 0x04>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 status = "disable";
174 }; 151 };
175 152
176 sdhci@c8000400 { 153 i2c@7000d000 {
177 compatible = "nvidia,tegra20-sdhci"; 154 compatible = "nvidia,tegra20-i2c-dvc";
178 reg = <0xc8000400 0x200>; 155 reg = <0x7000d000 0x200>;
179 interrupts = < 0 19 0x04 >; 156 interrupts = <0 53 0x04>;
157 #address-cells = <1>;
158 #size-cells = <0>;
159 status = "disable";
180 }; 160 };
181 161
182 sdhci@c8000600 { 162 pmc {
183 compatible = "nvidia,tegra20-sdhci"; 163 compatible = "nvidia,tegra20-pmc";
184 reg = <0xc8000600 0x200>; 164 reg = <0x7000e400 0x400>;
185 interrupts = < 0 31 0x04 >; 165 };
166
167 mc {
168 compatible = "nvidia,tegra20-mc";
169 reg = <0x7000f000 0x024
170 0x7000f03c 0x3c4>;
171 interrupts = <0 77 0x04>;
172 };
173
174 gart {
175 compatible = "nvidia,tegra20-gart";
176 reg = <0x7000f024 0x00000018 /* controller registers */
177 0x58000000 0x02000000>; /* GART aperture */
178 };
179
180 emc {
181 compatible = "nvidia,tegra20-emc";
182 reg = <0x7000f400 0x200>;
183 #address-cells = <1>;
184 #size-cells = <0>;
186 }; 185 };
187 186
188 usb@c5000000 { 187 usb@c5000000 {
189 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 188 compatible = "nvidia,tegra20-ehci", "usb-ehci";
190 reg = <0xc5000000 0x4000>; 189 reg = <0xc5000000 0x4000>;
191 interrupts = < 0 20 0x04 >; 190 interrupts = <0 20 0x04>;
192 phy_type = "utmi"; 191 phy_type = "utmi";
193 nvidia,has-legacy-mode; 192 nvidia,has-legacy-mode;
193 status = "disable";
194 }; 194 };
195 195
196 usb@c5004000 { 196 usb@c5004000 {
197 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 197 compatible = "nvidia,tegra20-ehci", "usb-ehci";
198 reg = <0xc5004000 0x4000>; 198 reg = <0xc5004000 0x4000>;
199 interrupts = < 0 21 0x04 >; 199 interrupts = <0 21 0x04>;
200 phy_type = "ulpi"; 200 phy_type = "ulpi";
201 status = "disable";
201 }; 202 };
202 203
203 usb@c5008000 { 204 usb@c5008000 {
204 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 205 compatible = "nvidia,tegra20-ehci", "usb-ehci";
205 reg = <0xc5008000 0x4000>; 206 reg = <0xc5008000 0x4000>;
206 interrupts = < 0 97 0x04 >; 207 interrupts = <0 97 0x04>;
207 phy_type = "utmi"; 208 phy_type = "utmi";
209 status = "disable";
210 };
211
212 sdhci@c8000000 {
213 compatible = "nvidia,tegra20-sdhci";
214 reg = <0xc8000000 0x200>;
215 interrupts = <0 14 0x04>;
216 status = "disable";
208 }; 217 };
209};
210 218
219 sdhci@c8000200 {
220 compatible = "nvidia,tegra20-sdhci";
221 reg = <0xc8000200 0x200>;
222 interrupts = <0 15 0x04>;
223 status = "disable";
224 };
225
226 sdhci@c8000400 {
227 compatible = "nvidia,tegra20-sdhci";
228 reg = <0xc8000400 0x200>;
229 interrupts = <0 19 0x04>;
230 status = "disable";
231 };
232
233 sdhci@c8000600 {
234 compatible = "nvidia,tegra20-sdhci";
235 reg = <0xc8000600 0x200>;
236 interrupts = <0 31 0x04>;
237 status = "disable";
238 };
239
240 pmu {
241 compatible = "arm,cortex-a9-pmu";
242 interrupts = <0 56 0x04
243 0 57 0x04>;
244 };
245};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:34:49 -0500