diff options
Diffstat (limited to 'arch/arm/boot/dts/tegra20.dtsi')
-rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index b8effa1cbda7..2e7c83c7253b 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -9,6 +9,7 @@ | |||
9 | reg = <0x50000000 0x00024000>; | 9 | reg = <0x50000000 0x00024000>; |
10 | interrupts = <0 65 0x04 /* mpcore syncpt */ | 10 | interrupts = <0 65 0x04 /* mpcore syncpt */ |
11 | 0 67 0x04>; /* mpcore general */ | 11 | 0 67 0x04>; /* mpcore general */ |
12 | clocks = <&tegra_car 28>; | ||
12 | 13 | ||
13 | #address-cells = <1>; | 14 | #address-cells = <1>; |
14 | #size-cells = <1>; | 15 | #size-cells = <1>; |
@@ -19,41 +20,49 @@ | |||
19 | compatible = "nvidia,tegra20-mpe"; | 20 | compatible = "nvidia,tegra20-mpe"; |
20 | reg = <0x54040000 0x00040000>; | 21 | reg = <0x54040000 0x00040000>; |
21 | interrupts = <0 68 0x04>; | 22 | interrupts = <0 68 0x04>; |
23 | clocks = <&tegra_car 60>; | ||
22 | }; | 24 | }; |
23 | 25 | ||
24 | vi { | 26 | vi { |
25 | compatible = "nvidia,tegra20-vi"; | 27 | compatible = "nvidia,tegra20-vi"; |
26 | reg = <0x54080000 0x00040000>; | 28 | reg = <0x54080000 0x00040000>; |
27 | interrupts = <0 69 0x04>; | 29 | interrupts = <0 69 0x04>; |
30 | clocks = <&tegra_car 100>; | ||
28 | }; | 31 | }; |
29 | 32 | ||
30 | epp { | 33 | epp { |
31 | compatible = "nvidia,tegra20-epp"; | 34 | compatible = "nvidia,tegra20-epp"; |
32 | reg = <0x540c0000 0x00040000>; | 35 | reg = <0x540c0000 0x00040000>; |
33 | interrupts = <0 70 0x04>; | 36 | interrupts = <0 70 0x04>; |
37 | clocks = <&tegra_car 19>; | ||
34 | }; | 38 | }; |
35 | 39 | ||
36 | isp { | 40 | isp { |
37 | compatible = "nvidia,tegra20-isp"; | 41 | compatible = "nvidia,tegra20-isp"; |
38 | reg = <0x54100000 0x00040000>; | 42 | reg = <0x54100000 0x00040000>; |
39 | interrupts = <0 71 0x04>; | 43 | interrupts = <0 71 0x04>; |
44 | clocks = <&tegra_car 23>; | ||
40 | }; | 45 | }; |
41 | 46 | ||
42 | gr2d { | 47 | gr2d { |
43 | compatible = "nvidia,tegra20-gr2d"; | 48 | compatible = "nvidia,tegra20-gr2d"; |
44 | reg = <0x54140000 0x00040000>; | 49 | reg = <0x54140000 0x00040000>; |
45 | interrupts = <0 72 0x04>; | 50 | interrupts = <0 72 0x04>; |
51 | clocks = <&tegra_car 21>; | ||
46 | }; | 52 | }; |
47 | 53 | ||
48 | gr3d { | 54 | gr3d { |
49 | compatible = "nvidia,tegra20-gr3d"; | 55 | compatible = "nvidia,tegra20-gr3d"; |
50 | reg = <0x54180000 0x00040000>; | 56 | reg = <0x54180000 0x00040000>; |
57 | clocks = <&tegra_car 24>; | ||
51 | }; | 58 | }; |
52 | 59 | ||
53 | dc@54200000 { | 60 | dc@54200000 { |
54 | compatible = "nvidia,tegra20-dc"; | 61 | compatible = "nvidia,tegra20-dc"; |
55 | reg = <0x54200000 0x00040000>; | 62 | reg = <0x54200000 0x00040000>; |
56 | interrupts = <0 73 0x04>; | 63 | interrupts = <0 73 0x04>; |
64 | clocks = <&tegra_car 27>, <&tegra_car 121>; | ||
65 | clock-names = "disp1", "parent"; | ||
57 | 66 | ||
58 | rgb { | 67 | rgb { |
59 | status = "disabled"; | 68 | status = "disabled"; |
@@ -64,6 +73,8 @@ | |||
64 | compatible = "nvidia,tegra20-dc"; | 73 | compatible = "nvidia,tegra20-dc"; |
65 | reg = <0x54240000 0x00040000>; | 74 | reg = <0x54240000 0x00040000>; |
66 | interrupts = <0 74 0x04>; | 75 | interrupts = <0 74 0x04>; |
76 | clocks = <&tegra_car 26>, <&tegra_car 121>; | ||
77 | clock-names = "disp2", "parent"; | ||
67 | 78 | ||
68 | rgb { | 79 | rgb { |
69 | status = "disabled"; | 80 | status = "disabled"; |
@@ -74,6 +85,8 @@ | |||
74 | compatible = "nvidia,tegra20-hdmi"; | 85 | compatible = "nvidia,tegra20-hdmi"; |
75 | reg = <0x54280000 0x00040000>; | 86 | reg = <0x54280000 0x00040000>; |
76 | interrupts = <0 75 0x04>; | 87 | interrupts = <0 75 0x04>; |
88 | clocks = <&tegra_car 51>, <&tegra_car 117>; | ||
89 | clock-names = "hdmi", "parent"; | ||
77 | status = "disabled"; | 90 | status = "disabled"; |
78 | }; | 91 | }; |
79 | 92 | ||
@@ -81,12 +94,14 @@ | |||
81 | compatible = "nvidia,tegra20-tvo"; | 94 | compatible = "nvidia,tegra20-tvo"; |
82 | reg = <0x542c0000 0x00040000>; | 95 | reg = <0x542c0000 0x00040000>; |
83 | interrupts = <0 76 0x04>; | 96 | interrupts = <0 76 0x04>; |
97 | clocks = <&tegra_car 102>; | ||
84 | status = "disabled"; | 98 | status = "disabled"; |
85 | }; | 99 | }; |
86 | 100 | ||
87 | dsi { | 101 | dsi { |
88 | compatible = "nvidia,tegra20-dsi"; | 102 | compatible = "nvidia,tegra20-dsi"; |
89 | reg = <0x54300000 0x00040000>; | 103 | reg = <0x54300000 0x00040000>; |
104 | clocks = <&tegra_car 48>; | ||
90 | status = "disabled"; | 105 | status = "disabled"; |
91 | }; | 106 | }; |
92 | }; | 107 | }; |
@@ -123,6 +138,12 @@ | |||
123 | 0 42 0x04>; | 138 | 0 42 0x04>; |
124 | }; | 139 | }; |
125 | 140 | ||
141 | tegra_car: clock { | ||
142 | compatible = "nvidia,tegra20-car"; | ||
143 | reg = <0x60006000 0x1000>; | ||
144 | #clock-cells = <1>; | ||
145 | }; | ||
146 | |||
126 | apbdma: dma { | 147 | apbdma: dma { |
127 | compatible = "nvidia,tegra20-apbdma"; | 148 | compatible = "nvidia,tegra20-apbdma"; |
128 | reg = <0x6000a000 0x1200>; | 149 | reg = <0x6000a000 0x1200>; |
@@ -142,6 +163,7 @@ | |||
142 | 0 117 0x04 | 163 | 0 117 0x04 |
143 | 0 118 0x04 | 164 | 0 118 0x04 |
144 | 0 119 0x04>; | 165 | 0 119 0x04>; |
166 | clocks = <&tegra_car 34>; | ||
145 | }; | 167 | }; |
146 | 168 | ||
147 | ahb { | 169 | ahb { |
@@ -183,6 +205,7 @@ | |||
183 | reg = <0x70002800 0x200>; | 205 | reg = <0x70002800 0x200>; |
184 | interrupts = <0 13 0x04>; | 206 | interrupts = <0 13 0x04>; |
185 | nvidia,dma-request-selector = <&apbdma 2>; | 207 | nvidia,dma-request-selector = <&apbdma 2>; |
208 | clocks = <&tegra_car 11>; | ||
186 | status = "disabled"; | 209 | status = "disabled"; |
187 | }; | 210 | }; |
188 | 211 | ||
@@ -191,6 +214,7 @@ | |||
191 | reg = <0x70002a00 0x200>; | 214 | reg = <0x70002a00 0x200>; |
192 | interrupts = <0 3 0x04>; | 215 | interrupts = <0 3 0x04>; |
193 | nvidia,dma-request-selector = <&apbdma 1>; | 216 | nvidia,dma-request-selector = <&apbdma 1>; |
217 | clocks = <&tegra_car 18>; | ||
194 | status = "disabled"; | 218 | status = "disabled"; |
195 | }; | 219 | }; |
196 | 220 | ||
@@ -199,6 +223,7 @@ | |||
199 | reg = <0x70006000 0x40>; | 223 | reg = <0x70006000 0x40>; |
200 | reg-shift = <2>; | 224 | reg-shift = <2>; |
201 | interrupts = <0 36 0x04>; | 225 | interrupts = <0 36 0x04>; |
226 | clocks = <&tegra_car 6>; | ||
202 | status = "disabled"; | 227 | status = "disabled"; |
203 | }; | 228 | }; |
204 | 229 | ||
@@ -207,6 +232,7 @@ | |||
207 | reg = <0x70006040 0x40>; | 232 | reg = <0x70006040 0x40>; |
208 | reg-shift = <2>; | 233 | reg-shift = <2>; |
209 | interrupts = <0 37 0x04>; | 234 | interrupts = <0 37 0x04>; |
235 | clocks = <&tegra_car 96>; | ||
210 | status = "disabled"; | 236 | status = "disabled"; |
211 | }; | 237 | }; |
212 | 238 | ||
@@ -215,6 +241,7 @@ | |||
215 | reg = <0x70006200 0x100>; | 241 | reg = <0x70006200 0x100>; |
216 | reg-shift = <2>; | 242 | reg-shift = <2>; |
217 | interrupts = <0 46 0x04>; | 243 | interrupts = <0 46 0x04>; |
244 | clocks = <&tegra_car 55>; | ||
218 | status = "disabled"; | 245 | status = "disabled"; |
219 | }; | 246 | }; |
220 | 247 | ||
@@ -223,6 +250,7 @@ | |||
223 | reg = <0x70006300 0x100>; | 250 | reg = <0x70006300 0x100>; |
224 | reg-shift = <2>; | 251 | reg-shift = <2>; |
225 | interrupts = <0 90 0x04>; | 252 | interrupts = <0 90 0x04>; |
253 | clocks = <&tegra_car 65>; | ||
226 | status = "disabled"; | 254 | status = "disabled"; |
227 | }; | 255 | }; |
228 | 256 | ||
@@ -231,6 +259,7 @@ | |||
231 | reg = <0x70006400 0x100>; | 259 | reg = <0x70006400 0x100>; |
232 | reg-shift = <2>; | 260 | reg-shift = <2>; |
233 | interrupts = <0 91 0x04>; | 261 | interrupts = <0 91 0x04>; |
262 | clocks = <&tegra_car 66>; | ||
234 | status = "disabled"; | 263 | status = "disabled"; |
235 | }; | 264 | }; |
236 | 265 | ||
@@ -238,6 +267,7 @@ | |||
238 | compatible = "nvidia,tegra20-pwm"; | 267 | compatible = "nvidia,tegra20-pwm"; |
239 | reg = <0x7000a000 0x100>; | 268 | reg = <0x7000a000 0x100>; |
240 | #pwm-cells = <2>; | 269 | #pwm-cells = <2>; |
270 | clocks = <&tegra_car 17>; | ||
241 | }; | 271 | }; |
242 | 272 | ||
243 | rtc { | 273 | rtc { |
@@ -252,6 +282,8 @@ | |||
252 | interrupts = <0 38 0x04>; | 282 | interrupts = <0 38 0x04>; |
253 | #address-cells = <1>; | 283 | #address-cells = <1>; |
254 | #size-cells = <0>; | 284 | #size-cells = <0>; |
285 | clocks = <&tegra_car 12>, <&tegra_car 124>; | ||
286 | clock-names = "div-clk", "fast-clk"; | ||
255 | status = "disabled"; | 287 | status = "disabled"; |
256 | }; | 288 | }; |
257 | 289 | ||
@@ -262,6 +294,7 @@ | |||
262 | nvidia,dma-request-selector = <&apbdma 11>; | 294 | nvidia,dma-request-selector = <&apbdma 11>; |
263 | #address-cells = <1>; | 295 | #address-cells = <1>; |
264 | #size-cells = <0>; | 296 | #size-cells = <0>; |
297 | clocks = <&tegra_car 43>; | ||
265 | status = "disabled"; | 298 | status = "disabled"; |
266 | }; | 299 | }; |
267 | 300 | ||
@@ -271,6 +304,8 @@ | |||
271 | interrupts = <0 84 0x04>; | 304 | interrupts = <0 84 0x04>; |
272 | #address-cells = <1>; | 305 | #address-cells = <1>; |
273 | #size-cells = <0>; | 306 | #size-cells = <0>; |
307 | clocks = <&tegra_car 54>, <&tegra_car 124>; | ||
308 | clock-names = "div-clk", "fast-clk"; | ||
274 | status = "disabled"; | 309 | status = "disabled"; |
275 | }; | 310 | }; |
276 | 311 | ||
@@ -280,6 +315,8 @@ | |||
280 | interrupts = <0 92 0x04>; | 315 | interrupts = <0 92 0x04>; |
281 | #address-cells = <1>; | 316 | #address-cells = <1>; |
282 | #size-cells = <0>; | 317 | #size-cells = <0>; |
318 | clocks = <&tegra_car 67>, <&tegra_car 124>; | ||
319 | clock-names = "div-clk", "fast-clk"; | ||
283 | status = "disabled"; | 320 | status = "disabled"; |
284 | }; | 321 | }; |
285 | 322 | ||
@@ -289,6 +326,8 @@ | |||
289 | interrupts = <0 53 0x04>; | 326 | interrupts = <0 53 0x04>; |
290 | #address-cells = <1>; | 327 | #address-cells = <1>; |
291 | #size-cells = <0>; | 328 | #size-cells = <0>; |
329 | clocks = <&tegra_car 47>, <&tegra_car 124>; | ||
330 | clock-names = "div-clk", "fast-clk"; | ||
292 | status = "disabled"; | 331 | status = "disabled"; |
293 | }; | 332 | }; |
294 | 333 | ||
@@ -299,6 +338,7 @@ | |||
299 | nvidia,dma-request-selector = <&apbdma 15>; | 338 | nvidia,dma-request-selector = <&apbdma 15>; |
300 | #address-cells = <1>; | 339 | #address-cells = <1>; |
301 | #size-cells = <0>; | 340 | #size-cells = <0>; |
341 | clocks = <&tegra_car 41>; | ||
302 | status = "disabled"; | 342 | status = "disabled"; |
303 | }; | 343 | }; |
304 | 344 | ||
@@ -309,6 +349,7 @@ | |||
309 | nvidia,dma-request-selector = <&apbdma 16>; | 349 | nvidia,dma-request-selector = <&apbdma 16>; |
310 | #address-cells = <1>; | 350 | #address-cells = <1>; |
311 | #size-cells = <0>; | 351 | #size-cells = <0>; |
352 | clocks = <&tegra_car 44>; | ||
312 | status = "disabled"; | 353 | status = "disabled"; |
313 | }; | 354 | }; |
314 | 355 | ||
@@ -319,6 +360,7 @@ | |||
319 | nvidia,dma-request-selector = <&apbdma 17>; | 360 | nvidia,dma-request-selector = <&apbdma 17>; |
320 | #address-cells = <1>; | 361 | #address-cells = <1>; |
321 | #size-cells = <0>; | 362 | #size-cells = <0>; |
363 | clocks = <&tegra_car 46>; | ||
322 | status = "disabled"; | 364 | status = "disabled"; |
323 | }; | 365 | }; |
324 | 366 | ||
@@ -329,6 +371,7 @@ | |||
329 | nvidia,dma-request-selector = <&apbdma 18>; | 371 | nvidia,dma-request-selector = <&apbdma 18>; |
330 | #address-cells = <1>; | 372 | #address-cells = <1>; |
331 | #size-cells = <0>; | 373 | #size-cells = <0>; |
374 | clocks = <&tegra_car 68>; | ||
332 | status = "disabled"; | 375 | status = "disabled"; |
333 | }; | 376 | }; |
334 | 377 | ||
@@ -357,12 +400,40 @@ | |||
357 | #size-cells = <0>; | 400 | #size-cells = <0>; |
358 | }; | 401 | }; |
359 | 402 | ||
403 | phy1: usb-phy@c5000400 { | ||
404 | compatible = "nvidia,tegra20-usb-phy"; | ||
405 | reg = <0xc5000400 0x3c00>; | ||
406 | phy_type = "utmi"; | ||
407 | nvidia,has-legacy-mode; | ||
408 | clocks = <&tegra_car 22>, <&tegra_car 127>; | ||
409 | clock-names = "phy", "pll_u"; | ||
410 | }; | ||
411 | |||
412 | phy2: usb-phy@c5004400 { | ||
413 | compatible = "nvidia,tegra20-usb-phy"; | ||
414 | reg = <0xc5004400 0x3c00>; | ||
415 | phy_type = "ulpi"; | ||
416 | clocks = <&tegra_car 94>, <&tegra_car 127>; | ||
417 | clock-names = "phy", "pll_u"; | ||
418 | }; | ||
419 | |||
420 | phy3: usb-phy@c5008400 { | ||
421 | compatible = "nvidia,tegra20-usb-phy"; | ||
422 | reg = <0xc5008400 0x3C00>; | ||
423 | phy_type = "utmi"; | ||
424 | clocks = <&tegra_car 22>, <&tegra_car 127>; | ||
425 | clock-names = "phy", "pll_u"; | ||
426 | }; | ||
427 | |||
360 | usb@c5000000 { | 428 | usb@c5000000 { |
361 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | 429 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
362 | reg = <0xc5000000 0x4000>; | 430 | reg = <0xc5000000 0x4000>; |
363 | interrupts = <0 20 0x04>; | 431 | interrupts = <0 20 0x04>; |
364 | phy_type = "utmi"; | 432 | phy_type = "utmi"; |
365 | nvidia,has-legacy-mode; | 433 | nvidia,has-legacy-mode; |
434 | clocks = <&tegra_car 22>; | ||
435 | nvidia,needs-double-reset; | ||
436 | nvidia,phy = <&phy1>; | ||
366 | status = "disabled"; | 437 | status = "disabled"; |
367 | }; | 438 | }; |
368 | 439 | ||
@@ -371,6 +442,8 @@ | |||
371 | reg = <0xc5004000 0x4000>; | 442 | reg = <0xc5004000 0x4000>; |
372 | interrupts = <0 21 0x04>; | 443 | interrupts = <0 21 0x04>; |
373 | phy_type = "ulpi"; | 444 | phy_type = "ulpi"; |
445 | clocks = <&tegra_car 58>; | ||
446 | nvidia,phy = <&phy2>; | ||
374 | status = "disabled"; | 447 | status = "disabled"; |
375 | }; | 448 | }; |
376 | 449 | ||
@@ -379,6 +452,8 @@ | |||
379 | reg = <0xc5008000 0x4000>; | 452 | reg = <0xc5008000 0x4000>; |
380 | interrupts = <0 97 0x04>; | 453 | interrupts = <0 97 0x04>; |
381 | phy_type = "utmi"; | 454 | phy_type = "utmi"; |
455 | clocks = <&tegra_car 59>; | ||
456 | nvidia,phy = <&phy3>; | ||
382 | status = "disabled"; | 457 | status = "disabled"; |
383 | }; | 458 | }; |
384 | 459 | ||
@@ -386,6 +461,7 @@ | |||
386 | compatible = "nvidia,tegra20-sdhci"; | 461 | compatible = "nvidia,tegra20-sdhci"; |
387 | reg = <0xc8000000 0x200>; | 462 | reg = <0xc8000000 0x200>; |
388 | interrupts = <0 14 0x04>; | 463 | interrupts = <0 14 0x04>; |
464 | clocks = <&tegra_car 14>; | ||
389 | status = "disabled"; | 465 | status = "disabled"; |
390 | }; | 466 | }; |
391 | 467 | ||
@@ -393,6 +469,7 @@ | |||
393 | compatible = "nvidia,tegra20-sdhci"; | 469 | compatible = "nvidia,tegra20-sdhci"; |
394 | reg = <0xc8000200 0x200>; | 470 | reg = <0xc8000200 0x200>; |
395 | interrupts = <0 15 0x04>; | 471 | interrupts = <0 15 0x04>; |
472 | clocks = <&tegra_car 9>; | ||
396 | status = "disabled"; | 473 | status = "disabled"; |
397 | }; | 474 | }; |
398 | 475 | ||
@@ -400,6 +477,7 @@ | |||
400 | compatible = "nvidia,tegra20-sdhci"; | 477 | compatible = "nvidia,tegra20-sdhci"; |
401 | reg = <0xc8000400 0x200>; | 478 | reg = <0xc8000400 0x200>; |
402 | interrupts = <0 19 0x04>; | 479 | interrupts = <0 19 0x04>; |
480 | clocks = <&tegra_car 69>; | ||
403 | status = "disabled"; | 481 | status = "disabled"; |
404 | }; | 482 | }; |
405 | 483 | ||
@@ -407,9 +485,27 @@ | |||
407 | compatible = "nvidia,tegra20-sdhci"; | 485 | compatible = "nvidia,tegra20-sdhci"; |
408 | reg = <0xc8000600 0x200>; | 486 | reg = <0xc8000600 0x200>; |
409 | interrupts = <0 31 0x04>; | 487 | interrupts = <0 31 0x04>; |
488 | clocks = <&tegra_car 15>; | ||
410 | status = "disabled"; | 489 | status = "disabled"; |
411 | }; | 490 | }; |
412 | 491 | ||
492 | cpus { | ||
493 | #address-cells = <1>; | ||
494 | #size-cells = <0>; | ||
495 | |||
496 | cpu@0 { | ||
497 | device_type = "cpu"; | ||
498 | compatible = "arm,cortex-a9"; | ||
499 | reg = <0>; | ||
500 | }; | ||
501 | |||
502 | cpu@1 { | ||
503 | device_type = "cpu"; | ||
504 | compatible = "arm,cortex-a9"; | ||
505 | reg = <1>; | ||
506 | }; | ||
507 | }; | ||
508 | |||
413 | pmu { | 509 | pmu { |
414 | compatible = "arm,cortex-a9-pmu"; | 510 | compatible = "arm,cortex-a9-pmu"; |
415 | interrupts = <0 56 0x04 | 511 | interrupts = <0 56 0x04 |