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Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi339
1 files changed, 255 insertions, 84 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index ec0698a8354a..cf45a1a39483 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -8,22 +8,91 @@
8/ { 8/ {
9 compatible = "nvidia,tegra124"; 9 compatible = "nvidia,tegra124";
10 interrupt-parent = <&gic>; 10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 host1x@0,50000000 {
15 compatible = "nvidia,tegra124-host1x", "simple-bus";
16 reg = <0x0 0x50000000 0x0 0x00034000>;
17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
19 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
20 resets = <&tegra_car 28>;
21 reset-names = "host1x";
22
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
27
28 dc@0,54200000 {
29 compatible = "nvidia,tegra124-dc";
30 reg = <0x0 0x54200000 0x0 0x00040000>;
31 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
32 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
33 <&tegra_car TEGRA124_CLK_PLL_P>;
34 clock-names = "dc", "parent";
35 resets = <&tegra_car 27>;
36 reset-names = "dc";
37
38 nvidia,head = <0>;
39 };
40
41 dc@0,54240000 {
42 compatible = "nvidia,tegra124-dc";
43 reg = <0x0 0x54240000 0x0 0x00040000>;
44 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
45 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
46 <&tegra_car TEGRA124_CLK_PLL_P>;
47 clock-names = "dc", "parent";
48 resets = <&tegra_car 26>;
49 reset-names = "dc";
50
51 nvidia,head = <1>;
52 };
11 53
12 gic: interrupt-controller@50041000 { 54 sor@0,54540000 {
55 compatible = "nvidia,tegra124-sor";
56 reg = <0x0 0x54540000 0x0 0x00040000>;
57 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
58 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
59 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
60 <&tegra_car TEGRA124_CLK_PLL_DP>,
61 <&tegra_car TEGRA124_CLK_CLK_M>;
62 clock-names = "sor", "parent", "dp", "safe";
63 resets = <&tegra_car 182>;
64 reset-names = "sor";
65 status = "disabled";
66 };
67
68 dpaux@0,545c0000 {
69 compatible = "nvidia,tegra124-dpaux";
70 reg = <0x0 0x545c0000 0x0 0x00040000>;
71 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
72 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
73 <&tegra_car TEGRA124_CLK_PLL_DP>;
74 clock-names = "dpaux", "parent";
75 resets = <&tegra_car 181>;
76 reset-names = "dpaux";
77 status = "disabled";
78 };
79 };
80
81 gic: interrupt-controller@0,50041000 {
13 compatible = "arm,cortex-a15-gic"; 82 compatible = "arm,cortex-a15-gic";
14 #interrupt-cells = <3>; 83 #interrupt-cells = <3>;
15 interrupt-controller; 84 interrupt-controller;
16 reg = <0x50041000 0x1000>, 85 reg = <0x0 0x50041000 0x0 0x1000>,
17 <0x50042000 0x1000>, 86 <0x0 0x50042000 0x0 0x1000>,
18 <0x50044000 0x2000>, 87 <0x0 0x50044000 0x0 0x2000>,
19 <0x50046000 0x2000>; 88 <0x0 0x50046000 0x0 0x2000>;
20 interrupts = <GIC_PPI 9 89 interrupts = <GIC_PPI 9
21 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
22 }; 91 };
23 92
24 timer@60005000 { 93 timer@0,60005000 {
25 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 94 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
26 reg = <0x60005000 0x400>; 95 reg = <0x0 0x60005000 0x0 0x400>;
27 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 96 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
28 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -33,16 +102,16 @@
33 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 102 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
34 }; 103 };
35 104
36 tegra_car: clock@60006000 { 105 tegra_car: clock@0,60006000 {
37 compatible = "nvidia,tegra124-car"; 106 compatible = "nvidia,tegra124-car";
38 reg = <0x60006000 0x1000>; 107 reg = <0x0 0x60006000 0x0 0x1000>;
39 #clock-cells = <1>; 108 #clock-cells = <1>;
40 #reset-cells = <1>; 109 #reset-cells = <1>;
41 }; 110 };
42 111
43 gpio: gpio@6000d000 { 112 gpio: gpio@0,6000d000 {
44 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 113 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
45 reg = <0x6000d000 0x1000>; 114 reg = <0x0 0x6000d000 0x0 0x1000>;
46 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -57,9 +126,9 @@
57 interrupt-controller; 126 interrupt-controller;
58 }; 127 };
59 128
60 apbdma: dma@60020000 { 129 apbdma: dma@0,60020000 {
61 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 130 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
62 reg = <0x60020000 0x1400>; 131 reg = <0x0 0x60020000 0x0 0x1400>;
63 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 132 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@@ -98,10 +167,10 @@
98 #dma-cells = <1>; 167 #dma-cells = <1>;
99 }; 168 };
100 169
101 pinmux: pinmux@70000868 { 170 pinmux: pinmux@0,70000868 {
102 compatible = "nvidia,tegra124-pinmux"; 171 compatible = "nvidia,tegra124-pinmux";
103 reg = <0x70000868 0x164>, /* Pad control registers */ 172 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
104 <0x70003000 0x434>; /* Mux registers */ 173 <0x0 0x70003000 0x0 0x434>; /* Mux registers */
105 }; 174 };
106 175
107 /* 176 /*
@@ -112,9 +181,9 @@
112 * the APB DMA based serial driver, the comptible is 181 * the APB DMA based serial driver, the comptible is
113 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 182 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
114 */ 183 */
115 serial@70006000 { 184 serial@0,70006000 {
116 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 185 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
117 reg = <0x70006000 0x40>; 186 reg = <0x0 0x70006000 0x0 0x40>;
118 reg-shift = <2>; 187 reg-shift = <2>;
119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 189 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
@@ -125,9 +194,9 @@
125 status = "disabled"; 194 status = "disabled";
126 }; 195 };
127 196
128 serial@70006040 { 197 serial@0,70006040 {
129 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 198 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
130 reg = <0x70006040 0x40>; 199 reg = <0x0 0x70006040 0x0 0x40>;
131 reg-shift = <2>; 200 reg-shift = <2>;
132 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 202 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
@@ -138,9 +207,9 @@
138 status = "disabled"; 207 status = "disabled";
139 }; 208 };
140 209
141 serial@70006200 { 210 serial@0,70006200 {
142 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 211 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
143 reg = <0x70006200 0x40>; 212 reg = <0x0 0x70006200 0x0 0x40>;
144 reg-shift = <2>; 213 reg-shift = <2>;
145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 215 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
@@ -151,9 +220,9 @@
151 status = "disabled"; 220 status = "disabled";
152 }; 221 };
153 222
154 serial@70006300 { 223 serial@0,70006300 {
155 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 224 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
156 reg = <0x70006300 0x40>; 225 reg = <0x0 0x70006300 0x0 0x40>;
157 reg-shift = <2>; 226 reg-shift = <2>;
158 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 228 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
@@ -164,9 +233,9 @@
164 status = "disabled"; 233 status = "disabled";
165 }; 234 };
166 235
167 serial@70006400 { 236 serial@0,70006400 {
168 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 237 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
169 reg = <0x70006400 0x40>; 238 reg = <0x0 0x70006400 0x0 0x40>;
170 reg-shift = <2>; 239 reg-shift = <2>;
171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 241 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
@@ -177,9 +246,9 @@
177 status = "disabled"; 246 status = "disabled";
178 }; 247 };
179 248
180 pwm@7000a000 { 249 pwm@0,7000a000 {
181 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 250 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
182 reg = <0x7000a000 0x100>; 251 reg = <0x0 0x7000a000 0x0 0x100>;
183 #pwm-cells = <2>; 252 #pwm-cells = <2>;
184 clocks = <&tegra_car TEGRA124_CLK_PWM>; 253 clocks = <&tegra_car TEGRA124_CLK_PWM>;
185 resets = <&tegra_car 17>; 254 resets = <&tegra_car 17>;
@@ -187,9 +256,9 @@
187 status = "disabled"; 256 status = "disabled";
188 }; 257 };
189 258
190 i2c@7000c000 { 259 i2c@0,7000c000 {
191 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 260 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
192 reg = <0x7000c000 0x100>; 261 reg = <0x0 0x7000c000 0x0 0x100>;
193 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>; 263 #address-cells = <1>;
195 #size-cells = <0>; 264 #size-cells = <0>;
@@ -202,9 +271,9 @@
202 status = "disabled"; 271 status = "disabled";
203 }; 272 };
204 273
205 i2c@7000c400 { 274 i2c@0,7000c400 {
206 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 275 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
207 reg = <0x7000c400 0x100>; 276 reg = <0x0 0x7000c400 0x0 0x100>;
208 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 277 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>; 278 #address-cells = <1>;
210 #size-cells = <0>; 279 #size-cells = <0>;
@@ -217,9 +286,9 @@
217 status = "disabled"; 286 status = "disabled";
218 }; 287 };
219 288
220 i2c@7000c500 { 289 i2c@0,7000c500 {
221 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 290 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
222 reg = <0x7000c500 0x100>; 291 reg = <0x0 0x7000c500 0x0 0x100>;
223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>; 293 #address-cells = <1>;
225 #size-cells = <0>; 294 #size-cells = <0>;
@@ -232,9 +301,9 @@
232 status = "disabled"; 301 status = "disabled";
233 }; 302 };
234 303
235 i2c@7000c700 { 304 i2c@0,7000c700 {
236 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 305 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
237 reg = <0x7000c700 0x100>; 306 reg = <0x0 0x7000c700 0x0 0x100>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>; 308 #address-cells = <1>;
240 #size-cells = <0>; 309 #size-cells = <0>;
@@ -247,9 +316,9 @@
247 status = "disabled"; 316 status = "disabled";
248 }; 317 };
249 318
250 i2c@7000d000 { 319 i2c@0,7000d000 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 320 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000d000 0x100>; 321 reg = <0x0 0x7000d000 0x0 0x100>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>; 323 #address-cells = <1>;
255 #size-cells = <0>; 324 #size-cells = <0>;
@@ -262,9 +331,9 @@
262 status = "disabled"; 331 status = "disabled";
263 }; 332 };
264 333
265 i2c@7000d100 { 334 i2c@0,7000d100 {
266 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 335 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
267 reg = <0x7000d100 0x100>; 336 reg = <0x0 0x7000d100 0x0 0x100>;
268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>; 338 #address-cells = <1>;
270 #size-cells = <0>; 339 #size-cells = <0>;
@@ -277,9 +346,9 @@
277 status = "disabled"; 346 status = "disabled";
278 }; 347 };
279 348
280 spi@7000d400 { 349 spi@0,7000d400 {
281 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 350 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
282 reg = <0x7000d400 0x200>; 351 reg = <0x0 0x7000d400 0x0 0x200>;
283 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>; 353 #address-cells = <1>;
285 #size-cells = <0>; 354 #size-cells = <0>;
@@ -292,9 +361,9 @@
292 status = "disabled"; 361 status = "disabled";
293 }; 362 };
294 363
295 spi@7000d600 { 364 spi@0,7000d600 {
296 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 365 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
297 reg = <0x7000d600 0x200>; 366 reg = <0x0 0x7000d600 0x0 0x200>;
298 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>; 368 #address-cells = <1>;
300 #size-cells = <0>; 369 #size-cells = <0>;
@@ -307,9 +376,9 @@
307 status = "disabled"; 376 status = "disabled";
308 }; 377 };
309 378
310 spi@7000d800 { 379 spi@0,7000d800 {
311 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 380 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
312 reg = <0x7000d800 0x200>; 381 reg = <0x0 0x7000d800 0x0 0x200>;
313 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>; 383 #address-cells = <1>;
315 #size-cells = <0>; 384 #size-cells = <0>;
@@ -322,9 +391,9 @@
322 status = "disabled"; 391 status = "disabled";
323 }; 392 };
324 393
325 spi@7000da00 { 394 spi@0,7000da00 {
326 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 395 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
327 reg = <0x7000da00 0x200>; 396 reg = <0x0 0x7000da00 0x0 0x200>;
328 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>; 398 #address-cells = <1>;
330 #size-cells = <0>; 399 #size-cells = <0>;
@@ -337,9 +406,9 @@
337 status = "disabled"; 406 status = "disabled";
338 }; 407 };
339 408
340 spi@7000dc00 { 409 spi@0,7000dc00 {
341 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 410 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
342 reg = <0x7000dc00 0x200>; 411 reg = <0x0 0x7000dc00 0x0 0x200>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>; 413 #address-cells = <1>;
345 #size-cells = <0>; 414 #size-cells = <0>;
@@ -352,9 +421,9 @@
352 status = "disabled"; 421 status = "disabled";
353 }; 422 };
354 423
355 spi@7000de00 { 424 spi@0,7000de00 {
356 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 425 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
357 reg = <0x7000de00 0x200>; 426 reg = <0x0 0x7000de00 0x0 0x200>;
358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>; 428 #address-cells = <1>;
360 #size-cells = <0>; 429 #size-cells = <0>;
@@ -367,65 +436,65 @@
367 status = "disabled"; 436 status = "disabled";
368 }; 437 };
369 438
370 rtc@7000e000 { 439 rtc@0,7000e000 {
371 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 440 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
372 reg = <0x7000e000 0x100>; 441 reg = <0x0 0x7000e000 0x0 0x100>;
373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 442 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&tegra_car TEGRA124_CLK_RTC>; 443 clocks = <&tegra_car TEGRA124_CLK_RTC>;
375 }; 444 };
376 445
377 pmc@7000e400 { 446 pmc@0,7000e400 {
378 compatible = "nvidia,tegra124-pmc"; 447 compatible = "nvidia,tegra124-pmc";
379 reg = <0x7000e400 0x400>; 448 reg = <0x0 0x7000e400 0x0 0x400>;
380 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 449 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
381 clock-names = "pclk", "clk32k_in"; 450 clock-names = "pclk", "clk32k_in";
382 }; 451 };
383 452
384 sdhci@700b0000 { 453 sdhci@0,700b0000 {
385 compatible = "nvidia,tegra124-sdhci"; 454 compatible = "nvidia,tegra124-sdhci";
386 reg = <0x700b0000 0x200>; 455 reg = <0x0 0x700b0000 0x0 0x200>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 456 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 457 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
389 resets = <&tegra_car 14>; 458 resets = <&tegra_car 14>;
390 reset-names = "sdhci"; 459 reset-names = "sdhci";
391 status = "disable"; 460 status = "disabled";
392 }; 461 };
393 462
394 sdhci@700b0200 { 463 sdhci@0,700b0200 {
395 compatible = "nvidia,tegra124-sdhci"; 464 compatible = "nvidia,tegra124-sdhci";
396 reg = <0x700b0200 0x200>; 465 reg = <0x0 0x700b0200 0x0 0x200>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 466 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 467 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
399 resets = <&tegra_car 9>; 468 resets = <&tegra_car 9>;
400 reset-names = "sdhci"; 469 reset-names = "sdhci";
401 status = "disable"; 470 status = "disabled";
402 }; 471 };
403 472
404 sdhci@700b0400 { 473 sdhci@0,700b0400 {
405 compatible = "nvidia,tegra124-sdhci"; 474 compatible = "nvidia,tegra124-sdhci";
406 reg = <0x700b0400 0x200>; 475 reg = <0x0 0x700b0400 0x0 0x200>;
407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 476 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 477 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
409 resets = <&tegra_car 69>; 478 resets = <&tegra_car 69>;
410 reset-names = "sdhci"; 479 reset-names = "sdhci";
411 status = "disable"; 480 status = "disabled";
412 }; 481 };
413 482
414 sdhci@700b0600 { 483 sdhci@0,700b0600 {
415 compatible = "nvidia,tegra124-sdhci"; 484 compatible = "nvidia,tegra124-sdhci";
416 reg = <0x700b0600 0x200>; 485 reg = <0x0 0x700b0600 0x0 0x200>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 486 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 487 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
419 resets = <&tegra_car 15>; 488 resets = <&tegra_car 15>;
420 reset-names = "sdhci"; 489 reset-names = "sdhci";
421 status = "disable"; 490 status = "disabled";
422 }; 491 };
423 492
424 ahub@70300000 { 493 ahub@0,70300000 {
425 compatible = "nvidia,tegra124-ahub"; 494 compatible = "nvidia,tegra124-ahub";
426 reg = <0x70300000 0x200>, 495 reg = <0x0 0x70300000 0x0 0x200>,
427 <0x70300800 0x800>, 496 <0x0 0x70300800 0x0 0x800>,
428 <0x70300200 0x600>; 497 <0x0 0x70300200 0x0 0x600>;
429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 498 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 499 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
431 <&tegra_car TEGRA124_CLK_APBIF>; 500 <&tegra_car TEGRA124_CLK_APBIF>;
@@ -470,12 +539,12 @@
470 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 539 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
471 "rx9", "tx9"; 540 "rx9", "tx9";
472 ranges; 541 ranges;
473 #address-cells = <1>; 542 #address-cells = <2>;
474 #size-cells = <1>; 543 #size-cells = <2>;
475 544
476 tegra_i2s0: i2s@70301000 { 545 tegra_i2s0: i2s@0,70301000 {
477 compatible = "nvidia,tegra124-i2s"; 546 compatible = "nvidia,tegra124-i2s";
478 reg = <0x70301000 0x100>; 547 reg = <0x0 0x70301000 0x0 0x100>;
479 nvidia,ahub-cif-ids = <4 4>; 548 nvidia,ahub-cif-ids = <4 4>;
480 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 549 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
481 resets = <&tegra_car 30>; 550 resets = <&tegra_car 30>;
@@ -483,9 +552,9 @@
483 status = "disabled"; 552 status = "disabled";
484 }; 553 };
485 554
486 tegra_i2s1: i2s@70301100 { 555 tegra_i2s1: i2s@0,70301100 {
487 compatible = "nvidia,tegra124-i2s"; 556 compatible = "nvidia,tegra124-i2s";
488 reg = <0x70301100 0x100>; 557 reg = <0x0 0x70301100 0x0 0x100>;
489 nvidia,ahub-cif-ids = <5 5>; 558 nvidia,ahub-cif-ids = <5 5>;
490 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 559 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
491 resets = <&tegra_car 11>; 560 resets = <&tegra_car 11>;
@@ -493,9 +562,9 @@
493 status = "disabled"; 562 status = "disabled";
494 }; 563 };
495 564
496 tegra_i2s2: i2s@70301200 { 565 tegra_i2s2: i2s@0,70301200 {
497 compatible = "nvidia,tegra124-i2s"; 566 compatible = "nvidia,tegra124-i2s";
498 reg = <0x70301200 0x100>; 567 reg = <0x0 0x70301200 0x0 0x100>;
499 nvidia,ahub-cif-ids = <6 6>; 568 nvidia,ahub-cif-ids = <6 6>;
500 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 569 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
501 resets = <&tegra_car 18>; 570 resets = <&tegra_car 18>;
@@ -503,9 +572,9 @@
503 status = "disabled"; 572 status = "disabled";
504 }; 573 };
505 574
506 tegra_i2s3: i2s@70301300 { 575 tegra_i2s3: i2s@0,70301300 {
507 compatible = "nvidia,tegra124-i2s"; 576 compatible = "nvidia,tegra124-i2s";
508 reg = <0x70301300 0x100>; 577 reg = <0x0 0x70301300 0x0 0x100>;
509 nvidia,ahub-cif-ids = <7 7>; 578 nvidia,ahub-cif-ids = <7 7>;
510 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 579 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
511 resets = <&tegra_car 101>; 580 resets = <&tegra_car 101>;
@@ -513,9 +582,9 @@
513 status = "disabled"; 582 status = "disabled";
514 }; 583 };
515 584
516 tegra_i2s4: i2s@70301400 { 585 tegra_i2s4: i2s@0,70301400 {
517 compatible = "nvidia,tegra124-i2s"; 586 compatible = "nvidia,tegra124-i2s";
518 reg = <0x70301400 0x100>; 587 reg = <0x0 0x70301400 0x0 0x100>;
519 nvidia,ahub-cif-ids = <8 8>; 588 nvidia,ahub-cif-ids = <8 8>;
520 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 589 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
521 resets = <&tegra_car 102>; 590 resets = <&tegra_car 102>;
@@ -524,6 +593,108 @@
524 }; 593 };
525 }; 594 };
526 595
596 usb@0,7d000000 {
597 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
598 reg = <0x0 0x7d000000 0x0 0x4000>;
599 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
600 phy_type = "utmi";
601 clocks = <&tegra_car TEGRA124_CLK_USBD>;
602 resets = <&tegra_car 22>;
603 reset-names = "usb";
604 nvidia,phy = <&phy1>;
605 status = "disabled";
606 };
607
608 phy1: usb-phy@0,7d000000 {
609 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
610 reg = <0x0 0x7d000000 0x0 0x4000>,
611 <0x0 0x7d000000 0x0 0x4000>;
612 phy_type = "utmi";
613 clocks = <&tegra_car TEGRA124_CLK_USBD>,
614 <&tegra_car TEGRA124_CLK_PLL_U>,
615 <&tegra_car TEGRA124_CLK_USBD>;
616 clock-names = "reg", "pll_u", "utmi-pads";
617 nvidia,hssync-start-delay = <0>;
618 nvidia,idle-wait-delay = <17>;
619 nvidia,elastic-limit = <16>;
620 nvidia,term-range-adj = <6>;
621 nvidia,xcvr-setup = <9>;
622 nvidia,xcvr-lsfslew = <0>;
623 nvidia,xcvr-lsrslew = <3>;
624 nvidia,hssquelch-level = <2>;
625 nvidia,hsdiscon-level = <5>;
626 nvidia,xcvr-hsslew = <12>;
627 status = "disabled";
628 };
629
630 usb@0,7d004000 {
631 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
632 reg = <0x0 0x7d004000 0x0 0x4000>;
633 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
634 phy_type = "utmi";
635 clocks = <&tegra_car TEGRA124_CLK_USB2>;
636 resets = <&tegra_car 58>;
637 reset-names = "usb";
638 nvidia,phy = <&phy2>;
639 status = "disabled";
640 };
641
642 phy2: usb-phy@0,7d004000 {
643 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
644 reg = <0x0 0x7d004000 0x0 0x4000>,
645 <0x0 0x7d000000 0x0 0x4000>;
646 phy_type = "utmi";
647 clocks = <&tegra_car TEGRA124_CLK_USB2>,
648 <&tegra_car TEGRA124_CLK_PLL_U>,
649 <&tegra_car TEGRA124_CLK_USBD>;
650 clock-names = "reg", "pll_u", "utmi-pads";
651 nvidia,hssync-start-delay = <0>;
652 nvidia,idle-wait-delay = <17>;
653 nvidia,elastic-limit = <16>;
654 nvidia,term-range-adj = <6>;
655 nvidia,xcvr-setup = <9>;
656 nvidia,xcvr-lsfslew = <0>;
657 nvidia,xcvr-lsrslew = <3>;
658 nvidia,hssquelch-level = <2>;
659 nvidia,hsdiscon-level = <5>;
660 nvidia,xcvr-hsslew = <12>;
661 status = "disabled";
662 };
663
664 usb@0,7d008000 {
665 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
666 reg = <0x0 0x7d008000 0x0 0x4000>;
667 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
668 phy_type = "utmi";
669 clocks = <&tegra_car TEGRA124_CLK_USB3>;
670 resets = <&tegra_car 59>;
671 reset-names = "usb";
672 nvidia,phy = <&phy3>;
673 status = "disabled";
674 };
675
676 phy3: usb-phy@0,7d008000 {
677 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
678 reg = <0x0 0x7d008000 0x0 0x4000>,
679 <0x0 0x7d000000 0x0 0x4000>;
680 phy_type = "utmi";
681 clocks = <&tegra_car TEGRA124_CLK_USB3>,
682 <&tegra_car TEGRA124_CLK_PLL_U>,
683 <&tegra_car TEGRA124_CLK_USBD>;
684 clock-names = "reg", "pll_u", "utmi-pads";
685 nvidia,hssync-start-delay = <0>;
686 nvidia,idle-wait-delay = <17>;
687 nvidia,elastic-limit = <16>;
688 nvidia,term-range-adj = <6>;
689 nvidia,xcvr-setup = <9>;
690 nvidia,xcvr-lsfslew = <0>;
691 nvidia,xcvr-lsrslew = <3>;
692 nvidia,hssquelch-level = <2>;
693 nvidia,hsdiscon-level = <5>;
694 nvidia,xcvr-hsslew = <12>;
695 status = "disabled";
696 };
697
527 cpus { 698 cpus {
528 #address-cells = <1>; 699 #address-cells = <1>;
529 #size-cells = <0>; 700 #size-cells = <0>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 06:50:12 -0500