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-rw-r--r--arch/arm/boot/dts/tegra124.dtsi418
1 files changed, 418 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b7413004ee77..ec0698a8354a 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,4 +1,6 @@
1#include <dt-bindings/clock/tegra124-car.h>
1#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h>
3 5
4#include "skeleton.dtsi" 6#include "skeleton.dtsi"
@@ -28,6 +30,14 @@
28 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
29 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 32 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
33 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
34 };
35
36 tegra_car: clock@60006000 {
37 compatible = "nvidia,tegra124-car";
38 reg = <0x60006000 0x1000>;
39 #clock-cells = <1>;
40 #reset-cells = <1>;
31 }; 41 };
32 42
33 gpio: gpio@6000d000 { 43 gpio: gpio@6000d000 {
@@ -47,6 +57,53 @@
47 interrupt-controller; 57 interrupt-controller;
48 }; 58 };
49 59
60 apbdma: dma@60020000 {
61 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
62 reg = <0x60020000 0x1400>;
63 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
96 resets = <&tegra_car 34>;
97 reset-names = "dma";
98 #dma-cells = <1>;
99 };
100
101 pinmux: pinmux@70000868 {
102 compatible = "nvidia,tegra124-pinmux";
103 reg = <0x70000868 0x164>, /* Pad control registers */
104 <0x70003000 0x434>; /* Mux registers */
105 };
106
50 /* 107 /*
51 * There are two serial driver i.e. 8250 based simple serial 108 * There are two serial driver i.e. 8250 based simple serial
52 * driver and APB DMA based serial driver for higher baudrate 109 * driver and APB DMA based serial driver for higher baudrate
@@ -60,6 +117,11 @@
60 reg = <0x70006000 0x40>; 117 reg = <0x70006000 0x40>;
61 reg-shift = <2>; 118 reg-shift = <2>;
62 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
121 resets = <&tegra_car 6>;
122 reset-names = "serial";
123 dmas = <&apbdma 8>, <&apbdma 8>;
124 dma-names = "rx", "tx";
63 status = "disabled"; 125 status = "disabled";
64 }; 126 };
65 127
@@ -68,6 +130,11 @@
68 reg = <0x70006040 0x40>; 130 reg = <0x70006040 0x40>;
69 reg-shift = <2>; 131 reg-shift = <2>;
70 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 132 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
134 resets = <&tegra_car 7>;
135 reset-names = "serial";
136 dmas = <&apbdma 9>, <&apbdma 9>;
137 dma-names = "rx", "tx";
71 status = "disabled"; 138 status = "disabled";
72 }; 139 };
73 140
@@ -76,6 +143,11 @@
76 reg = <0x70006200 0x40>; 143 reg = <0x70006200 0x40>;
77 reg-shift = <2>; 144 reg-shift = <2>;
78 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
147 resets = <&tegra_car 55>;
148 reset-names = "serial";
149 dmas = <&apbdma 10>, <&apbdma 10>;
150 dma-names = "rx", "tx";
79 status = "disabled"; 151 status = "disabled";
80 }; 152 };
81 153
@@ -84,6 +156,11 @@
84 reg = <0x70006300 0x40>; 156 reg = <0x70006300 0x40>;
85 reg-shift = <2>; 157 reg-shift = <2>;
86 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 158 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
160 resets = <&tegra_car 65>;
161 reset-names = "serial";
162 dmas = <&apbdma 19>, <&apbdma 19>;
163 dma-names = "rx", "tx";
87 status = "disabled"; 164 status = "disabled";
88 }; 165 };
89 166
@@ -92,6 +169,201 @@
92 reg = <0x70006400 0x40>; 169 reg = <0x70006400 0x40>;
93 reg-shift = <2>; 170 reg-shift = <2>;
94 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 171 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
173 resets = <&tegra_car 66>;
174 reset-names = "serial";
175 dmas = <&apbdma 20>, <&apbdma 20>;
176 dma-names = "rx", "tx";
177 status = "disabled";
178 };
179
180 pwm@7000a000 {
181 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
182 reg = <0x7000a000 0x100>;
183 #pwm-cells = <2>;
184 clocks = <&tegra_car TEGRA124_CLK_PWM>;
185 resets = <&tegra_car 17>;
186 reset-names = "pwm";
187 status = "disabled";
188 };
189
190 i2c@7000c000 {
191 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
192 reg = <0x7000c000 0x100>;
193 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
194 #address-cells = <1>;
195 #size-cells = <0>;
196 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
197 clock-names = "div-clk";
198 resets = <&tegra_car 12>;
199 reset-names = "i2c";
200 dmas = <&apbdma 21>, <&apbdma 21>;
201 dma-names = "rx", "tx";
202 status = "disabled";
203 };
204
205 i2c@7000c400 {
206 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
207 reg = <0x7000c400 0x100>;
208 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
212 clock-names = "div-clk";
213 resets = <&tegra_car 54>;
214 reset-names = "i2c";
215 dmas = <&apbdma 22>, <&apbdma 22>;
216 dma-names = "rx", "tx";
217 status = "disabled";
218 };
219
220 i2c@7000c500 {
221 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
222 reg = <0x7000c500 0x100>;
223 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
227 clock-names = "div-clk";
228 resets = <&tegra_car 67>;
229 reset-names = "i2c";
230 dmas = <&apbdma 23>, <&apbdma 23>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 i2c@7000c700 {
236 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
237 reg = <0x7000c700 0x100>;
238 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
242 clock-names = "div-clk";
243 resets = <&tegra_car 103>;
244 reset-names = "i2c";
245 dmas = <&apbdma 26>, <&apbdma 26>;
246 dma-names = "rx", "tx";
247 status = "disabled";
248 };
249
250 i2c@7000d000 {
251 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
252 reg = <0x7000d000 0x100>;
253 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
257 clock-names = "div-clk";
258 resets = <&tegra_car 47>;
259 reset-names = "i2c";
260 dmas = <&apbdma 24>, <&apbdma 24>;
261 dma-names = "rx", "tx";
262 status = "disabled";
263 };
264
265 i2c@7000d100 {
266 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
267 reg = <0x7000d100 0x100>;
268 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
272 clock-names = "div-clk";
273 resets = <&tegra_car 166>;
274 reset-names = "i2c";
275 dmas = <&apbdma 30>, <&apbdma 30>;
276 dma-names = "rx", "tx";
277 status = "disabled";
278 };
279
280 spi@7000d400 {
281 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
282 reg = <0x7000d400 0x200>;
283 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
287 clock-names = "spi";
288 resets = <&tegra_car 41>;
289 reset-names = "spi";
290 dmas = <&apbdma 15>, <&apbdma 15>;
291 dma-names = "rx", "tx";
292 status = "disabled";
293 };
294
295 spi@7000d600 {
296 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
297 reg = <0x7000d600 0x200>;
298 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
299 #address-cells = <1>;
300 #size-cells = <0>;
301 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
302 clock-names = "spi";
303 resets = <&tegra_car 44>;
304 reset-names = "spi";
305 dmas = <&apbdma 16>, <&apbdma 16>;
306 dma-names = "rx", "tx";
307 status = "disabled";
308 };
309
310 spi@7000d800 {
311 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
312 reg = <0x7000d800 0x200>;
313 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
317 clock-names = "spi";
318 resets = <&tegra_car 46>;
319 reset-names = "spi";
320 dmas = <&apbdma 17>, <&apbdma 17>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 spi@7000da00 {
326 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
327 reg = <0x7000da00 0x200>;
328 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
332 clock-names = "spi";
333 resets = <&tegra_car 68>;
334 reset-names = "spi";
335 dmas = <&apbdma 18>, <&apbdma 18>;
336 dma-names = "rx", "tx";
337 status = "disabled";
338 };
339
340 spi@7000dc00 {
341 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
342 reg = <0x7000dc00 0x200>;
343 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
345 #size-cells = <0>;
346 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
347 clock-names = "spi";
348 resets = <&tegra_car 104>;
349 reset-names = "spi";
350 dmas = <&apbdma 27>, <&apbdma 27>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
354
355 spi@7000de00 {
356 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
357 reg = <0x7000de00 0x200>;
358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
362 clock-names = "spi";
363 resets = <&tegra_car 105>;
364 reset-names = "spi";
365 dmas = <&apbdma 28>, <&apbdma 28>;
366 dma-names = "rx", "tx";
95 status = "disabled"; 367 status = "disabled";
96 }; 368 };
97 369
@@ -99,11 +371,157 @@
99 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 371 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
100 reg = <0x7000e000 0x100>; 372 reg = <0x7000e000 0x100>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&tegra_car TEGRA124_CLK_RTC>;
102 }; 375 };
103 376
104 pmc@7000e400 { 377 pmc@7000e400 {
105 compatible = "nvidia,tegra124-pmc"; 378 compatible = "nvidia,tegra124-pmc";
106 reg = <0x7000e400 0x400>; 379 reg = <0x7000e400 0x400>;
380 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
381 clock-names = "pclk", "clk32k_in";
382 };
383
384 sdhci@700b0000 {
385 compatible = "nvidia,tegra124-sdhci";
386 reg = <0x700b0000 0x200>;
387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
389 resets = <&tegra_car 14>;
390 reset-names = "sdhci";
391 status = "disable";
392 };
393
394 sdhci@700b0200 {
395 compatible = "nvidia,tegra124-sdhci";
396 reg = <0x700b0200 0x200>;
397 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
399 resets = <&tegra_car 9>;
400 reset-names = "sdhci";
401 status = "disable";
402 };
403
404 sdhci@700b0400 {
405 compatible = "nvidia,tegra124-sdhci";
406 reg = <0x700b0400 0x200>;
407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
409 resets = <&tegra_car 69>;
410 reset-names = "sdhci";
411 status = "disable";
412 };
413
414 sdhci@700b0600 {
415 compatible = "nvidia,tegra124-sdhci";
416 reg = <0x700b0600 0x200>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
419 resets = <&tegra_car 15>;
420 reset-names = "sdhci";
421 status = "disable";
422 };
423
424 ahub@70300000 {
425 compatible = "nvidia,tegra124-ahub";
426 reg = <0x70300000 0x200>,
427 <0x70300800 0x800>,
428 <0x70300200 0x600>;
429 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
431 <&tegra_car TEGRA124_CLK_APBIF>;
432 clock-names = "d_audio", "apbif";
433 resets = <&tegra_car 106>, /* d_audio */
434 <&tegra_car 107>, /* apbif */
435 <&tegra_car 30>, /* i2s0 */
436 <&tegra_car 11>, /* i2s1 */
437 <&tegra_car 18>, /* i2s2 */
438 <&tegra_car 101>, /* i2s3 */
439 <&tegra_car 102>, /* i2s4 */
440 <&tegra_car 108>, /* dam0 */
441 <&tegra_car 109>, /* dam1 */
442 <&tegra_car 110>, /* dam2 */
443 <&tegra_car 10>, /* spdif */
444 <&tegra_car 153>, /* amx */
445 <&tegra_car 185>, /* amx1 */
446 <&tegra_car 154>, /* adx */
447 <&tegra_car 180>, /* adx1 */
448 <&tegra_car 186>, /* afc0 */
449 <&tegra_car 187>, /* afc1 */
450 <&tegra_car 188>, /* afc2 */
451 <&tegra_car 189>, /* afc3 */
452 <&tegra_car 190>, /* afc4 */
453 <&tegra_car 191>; /* afc5 */
454 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
455 "i2s3", "i2s4", "dam0", "dam1", "dam2",
456 "spdif", "amx", "amx1", "adx", "adx1",
457 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
458 dmas = <&apbdma 1>, <&apbdma 1>,
459 <&apbdma 2>, <&apbdma 2>,
460 <&apbdma 3>, <&apbdma 3>,
461 <&apbdma 4>, <&apbdma 4>,
462 <&apbdma 6>, <&apbdma 6>,
463 <&apbdma 7>, <&apbdma 7>,
464 <&apbdma 12>, <&apbdma 12>,
465 <&apbdma 13>, <&apbdma 13>,
466 <&apbdma 14>, <&apbdma 14>,
467 <&apbdma 29>, <&apbdma 29>;
468 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
469 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
470 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
471 "rx9", "tx9";
472 ranges;
473 #address-cells = <1>;
474 #size-cells = <1>;
475
476 tegra_i2s0: i2s@70301000 {
477 compatible = "nvidia,tegra124-i2s";
478 reg = <0x70301000 0x100>;
479 nvidia,ahub-cif-ids = <4 4>;
480 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
481 resets = <&tegra_car 30>;
482 reset-names = "i2s";
483 status = "disabled";
484 };
485
486 tegra_i2s1: i2s@70301100 {
487 compatible = "nvidia,tegra124-i2s";
488 reg = <0x70301100 0x100>;
489 nvidia,ahub-cif-ids = <5 5>;
490 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
491 resets = <&tegra_car 11>;
492 reset-names = "i2s";
493 status = "disabled";
494 };
495
496 tegra_i2s2: i2s@70301200 {
497 compatible = "nvidia,tegra124-i2s";
498 reg = <0x70301200 0x100>;
499 nvidia,ahub-cif-ids = <6 6>;
500 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
501 resets = <&tegra_car 18>;
502 reset-names = "i2s";
503 status = "disabled";
504 };
505
506 tegra_i2s3: i2s@70301300 {
507 compatible = "nvidia,tegra124-i2s";
508 reg = <0x70301300 0x100>;
509 nvidia,ahub-cif-ids = <7 7>;
510 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
511 resets = <&tegra_car 101>;
512 reset-names = "i2s";
513 status = "disabled";
514 };
515
516 tegra_i2s4: i2s@70301400 {
517 compatible = "nvidia,tegra124-i2s";
518 reg = <0x70301400 0x100>;
519 nvidia,ahub-cif-ids = <8 8>;
520 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
521 resets = <&tegra_car 102>;
522 reset-names = "i2s";
523 status = "disabled";
524 };
107 }; 525 };
108 526
109 cpus { 527 cpus {
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 04:36:40 -0500