diff options
Diffstat (limited to 'arch/arm/boot/dts/tegra124-nyan-big.dts')
-rw-r--r-- | arch/arm/boot/dts/tegra124-nyan-big.dts | 2005 |
1 files changed, 1102 insertions, 903 deletions
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 004e8e4e1c04..2d21253ea4e3 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts | |||
@@ -1,46 +1,29 @@ | |||
1 | /dts-v1/; | 1 | /dts-v1/; |
2 | 2 | ||
3 | #include <dt-bindings/input/input.h> | 3 | #include "tegra124-nyan.dtsi" |
4 | #include "tegra124.dtsi" | 4 | |
5 | #include "tegra124-nyan-big-emc.dtsi" | ||
5 | 6 | ||
6 | / { | 7 | / { |
7 | model = "Acer Chromebook 13 CB5-311"; | 8 | model = "Acer Chromebook 13 CB5-311"; |
8 | compatible = "google,nyan-big", "nvidia,tegra124"; | 9 | compatible = "google,nyan-big", "nvidia,tegra124"; |
9 | 10 | ||
10 | aliases { | 11 | panel: panel { |
11 | rtc0 = "/i2c@0,7000d000/pmic@40"; | 12 | compatible = "auo,b133xtn01"; |
12 | rtc1 = "/rtc@0,7000e000"; | ||
13 | serial0 = &uarta; | ||
14 | }; | ||
15 | 13 | ||
16 | memory { | 14 | backlight = <&backlight>; |
17 | reg = <0x0 0x80000000 0x0 0x80000000>; | 15 | ddc-i2c-bus = <&dpaux>; |
18 | }; | 16 | }; |
19 | 17 | ||
20 | host1x@0,50000000 { | 18 | sdhci@0,700b0400 { /* SD Card on this bus */ |
21 | hdmi@0,54280000 { | 19 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; |
22 | status = "okay"; | 20 | }; |
23 | |||
24 | vdd-supply = <&vdd_3v3_hdmi>; | ||
25 | pll-supply = <&vdd_hdmi_pll>; | ||
26 | hdmi-supply = <&vdd_5v0_hdmi>; | ||
27 | |||
28 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | ||
29 | nvidia,hpd-gpio = | ||
30 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | ||
31 | }; | ||
32 | |||
33 | sor@0,54540000 { | ||
34 | status = "okay"; | ||
35 | |||
36 | nvidia,dpaux = <&dpaux>; | ||
37 | nvidia,panel = <&panel>; | ||
38 | }; | ||
39 | 21 | ||
40 | dpaux@0,545c0000 { | 22 | sound { |
41 | vdd-supply = <&vdd_3v3_panel>; | 23 | compatible = "nvidia,tegra-audio-max98090-nyan-big", |
42 | status = "okay"; | 24 | "nvidia,tegra-audio-max98090-nyan", |
43 | }; | 25 | "nvidia,tegra-audio-max98090"; |
26 | nvidia,model = "GoogleNyanBig"; | ||
44 | }; | 27 | }; |
45 | 28 | ||
46 | pinmux@0,70000868 { | 29 | pinmux@0,70000868 { |
@@ -48,1092 +31,1308 @@ | |||
48 | pinctrl-0 = <&pinmux_default>; | 31 | pinctrl-0 = <&pinmux_default>; |
49 | 32 | ||
50 | pinmux_default: common { | 33 | pinmux_default: common { |
51 | dap_mclk1_pw4 { | 34 | clk_32k_out_pa0 { |
52 | nvidia,pins = "dap_mclk1_pw4"; | 35 | nvidia,pins = "clk_32k_out_pa0"; |
53 | nvidia,function = "extperiph1"; | 36 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
37 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
38 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
39 | }; | ||
40 | uart3_cts_n_pa1 { | ||
41 | nvidia,pins = "uart3_cts_n_pa1"; | ||
42 | nvidia,function = "gmi"; | ||
43 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
44 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
54 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 45 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
46 | }; | ||
47 | dap2_fs_pa2 { | ||
48 | nvidia,pins = "dap2_fs_pa2"; | ||
49 | nvidia,function = "i2s1"; | ||
55 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 50 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
56 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 51 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
52 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
53 | }; | ||
54 | dap2_sclk_pa3 { | ||
55 | nvidia,pins = "dap2_sclk_pa3"; | ||
56 | nvidia,function = "i2s1"; | ||
57 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
58 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
59 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
57 | }; | 60 | }; |
58 | dap2_din_pa4 { | 61 | dap2_din_pa4 { |
59 | nvidia,pins = "dap2_din_pa4"; | 62 | nvidia,pins = "dap2_din_pa4"; |
60 | nvidia,function = "i2s1"; | 63 | nvidia,function = "i2s1"; |
61 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
62 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 64 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
63 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 65 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
66 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
64 | }; | 67 | }; |
65 | dap2_dout_pa5 { | 68 | dap2_dout_pa5 { |
66 | nvidia,pins = "dap2_dout_pa5", | 69 | nvidia,pins = "dap2_dout_pa5"; |
67 | "dap2_fs_pa2", | ||
68 | "dap2_sclk_pa3"; | ||
69 | nvidia,function = "i2s1"; | 70 | nvidia,function = "i2s1"; |
70 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
71 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 71 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
72 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 72 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
73 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
73 | }; | 74 | }; |
74 | dvfs_pwm_px0 { | 75 | sdmmc3_clk_pa6 { |
75 | nvidia,pins = "dvfs_pwm_px0", | 76 | nvidia,pins = "sdmmc3_clk_pa6"; |
76 | "dvfs_clk_px2"; | 77 | nvidia,function = "sdmmc3"; |
77 | nvidia,function = "cldvfs"; | ||
78 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
79 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 78 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
80 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 79 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
80 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
81 | }; | 81 | }; |
82 | ulpi_clk_py0 { | 82 | sdmmc3_cmd_pa7 { |
83 | nvidia,pins = "ulpi_clk_py0", | 83 | nvidia,pins = "sdmmc3_cmd_pa7"; |
84 | "ulpi_nxt_py2", | 84 | nvidia,function = "sdmmc3"; |
85 | "ulpi_stp_py3"; | 85 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
86 | nvidia,function = "spi1"; | 86 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
87 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
88 | }; | ||
89 | pb0 { | ||
90 | nvidia,pins = "pb0"; | ||
91 | nvidia,function = "rsvd2"; | ||
92 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
93 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
94 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
95 | }; | ||
96 | pb1 { | ||
97 | nvidia,pins = "pb1"; | ||
98 | nvidia,function = "rsvd2"; | ||
99 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
100 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 101 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
102 | }; | ||
103 | sdmmc3_dat3_pb4 { | ||
104 | nvidia,pins = "sdmmc3_dat3_pb4"; | ||
105 | nvidia,function = "sdmmc3"; | ||
106 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
107 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
108 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
109 | }; | ||
110 | sdmmc3_dat2_pb5 { | ||
111 | nvidia,pins = "sdmmc3_dat2_pb5"; | ||
112 | nvidia,function = "sdmmc3"; | ||
113 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
115 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
116 | }; | ||
117 | sdmmc3_dat1_pb6 { | ||
118 | nvidia,pins = "sdmmc3_dat1_pb6"; | ||
119 | nvidia,function = "sdmmc3"; | ||
120 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
121 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
122 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
123 | }; | ||
124 | sdmmc3_dat0_pb7 { | ||
125 | nvidia,pins = "sdmmc3_dat0_pb7"; | ||
126 | nvidia,function = "sdmmc3"; | ||
127 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
128 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
129 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
130 | }; | ||
131 | uart3_rts_n_pc0 { | ||
132 | nvidia,pins = "uart3_rts_n_pc0"; | ||
133 | nvidia,function = "gmi"; | ||
134 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
135 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
136 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
137 | }; | ||
138 | uart2_txd_pc2 { | ||
139 | nvidia,pins = "uart2_txd_pc2"; | ||
140 | nvidia,function = "irda"; | ||
141 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
142 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
143 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
144 | }; | ||
145 | uart2_rxd_pc3 { | ||
146 | nvidia,pins = "uart2_rxd_pc3"; | ||
147 | nvidia,function = "irda"; | ||
148 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
149 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
150 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
151 | }; | ||
152 | gen1_i2c_scl_pc4 { | ||
153 | nvidia,pins = "gen1_i2c_scl_pc4"; | ||
154 | nvidia,function = "i2c1"; | ||
88 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 155 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
89 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 156 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
157 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
158 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
90 | }; | 159 | }; |
91 | ulpi_dir_py1 { | 160 | gen1_i2c_sda_pc5 { |
92 | nvidia,pins = "ulpi_dir_py1"; | 161 | nvidia,pins = "gen1_i2c_sda_pc5"; |
93 | nvidia,function = "spi1"; | 162 | nvidia,function = "i2c1"; |
163 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
164 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
94 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
166 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
167 | }; | ||
168 | pc7 { | ||
169 | nvidia,pins = "pc7"; | ||
95 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 170 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
96 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 171 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
97 | }; | 173 | }; |
98 | cam_i2c_scl_pbb1 { | 174 | pg0 { |
99 | nvidia,pins = "cam_i2c_scl_pbb1", | 175 | nvidia,pins = "pg0"; |
100 | "cam_i2c_sda_pbb2"; | 176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
101 | nvidia,function = "i2c3"; | 177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
102 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 178 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
179 | }; | ||
180 | pg1 { | ||
181 | nvidia,pins = "pg1"; | ||
103 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
104 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
105 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 184 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
106 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
107 | }; | 185 | }; |
108 | gen2_i2c_scl_pt5 { | 186 | pg2 { |
109 | nvidia,pins = "gen2_i2c_scl_pt5", | 187 | nvidia,pins = "pg2"; |
110 | "gen2_i2c_sda_pt6"; | 188 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
111 | nvidia,function = "i2c2"; | 189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
112 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 190 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
191 | }; | ||
192 | pg3 { | ||
193 | nvidia,pins = "pg3"; | ||
113 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 194 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 195 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
115 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 196 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
116 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
117 | }; | 197 | }; |
118 | pg4 { | 198 | pg4 { |
119 | nvidia,pins = "pg4", | 199 | nvidia,pins = "pg4"; |
120 | "pg5", | 200 | nvidia,function = "spi4"; |
121 | "pg6", | 201 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
122 | "pi3"; | 202 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
203 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
204 | }; | ||
205 | pg5 { | ||
206 | nvidia,pins = "pg5"; | ||
123 | nvidia,function = "spi4"; | 207 | nvidia,function = "spi4"; |
208 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
124 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 210 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
211 | }; | ||
212 | pg6 { | ||
213 | nvidia,pins = "pg6"; | ||
214 | nvidia,function = "spi4"; | ||
125 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 215 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
126 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
217 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
127 | }; | 218 | }; |
128 | pg7 { | 219 | pg7 { |
129 | nvidia,pins = "pg7"; | 220 | nvidia,pins = "pg7"; |
130 | nvidia,function = "spi4"; | 221 | nvidia,function = "spi4"; |
131 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
132 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 222 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
133 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 223 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
224 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
225 | }; | ||
226 | ph0 { | ||
227 | nvidia,pins = "ph0"; | ||
228 | nvidia,function = "gmi"; | ||
229 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
230 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
231 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
134 | }; | 232 | }; |
135 | ph1 { | 233 | ph1 { |
136 | nvidia,pins = "ph1"; | 234 | nvidia,pins = "ph1"; |
137 | nvidia,function = "pwm1"; | 235 | nvidia,function = "pwm1"; |
236 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
138 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 238 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
239 | }; | ||
240 | ph2 { | ||
241 | nvidia,pins = "ph2"; | ||
139 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 242 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
140 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
244 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
141 | }; | 245 | }; |
142 | pk0 { | 246 | ph3 { |
143 | nvidia,pins = "pk0", | 247 | nvidia,pins = "ph3"; |
144 | "kb_row15_ps7", | 248 | nvidia,function = "gmi"; |
145 | "clk_32k_out_pa0"; | 249 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
146 | nvidia,function = "soc"; | 250 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
147 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 251 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
252 | }; | ||
253 | ph4 { | ||
254 | nvidia,pins = "ph4"; | ||
255 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 257 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
150 | }; | 258 | }; |
151 | sdmmc1_clk_pz0 { | 259 | ph5 { |
152 | nvidia,pins = "sdmmc1_clk_pz0"; | 260 | nvidia,pins = "ph5"; |
153 | nvidia,function = "sdmmc1"; | 261 | nvidia,function = "rsvd2"; |
262 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
263 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
154 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 264 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
265 | }; | ||
266 | ph6 { | ||
267 | nvidia,pins = "ph6"; | ||
155 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 268 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
156 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 269 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
270 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
157 | }; | 271 | }; |
158 | sdmmc1_cmd_pz1 { | 272 | ph7 { |
159 | nvidia,pins = "sdmmc1_cmd_pz1", | 273 | nvidia,pins = "ph7"; |
160 | "sdmmc1_dat0_py7", | 274 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
161 | "sdmmc1_dat1_py6", | 275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
162 | "sdmmc1_dat2_py5", | 276 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
163 | "sdmmc1_dat3_py4"; | 277 | }; |
164 | nvidia,function = "sdmmc1"; | 278 | pi0 { |
279 | nvidia,pins = "pi0"; | ||
280 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
281 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
282 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
283 | }; | ||
284 | pi1 { | ||
285 | nvidia,pins = "pi1"; | ||
286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
165 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 288 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
289 | }; | ||
290 | pi2 { | ||
291 | nvidia,pins = "pi2"; | ||
292 | nvidia,function = "rsvd4"; | ||
293 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
294 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
295 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
296 | }; | ||
297 | pi3 { | ||
298 | nvidia,pins = "pi3"; | ||
299 | nvidia,function = "spi4"; | ||
300 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
301 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
302 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
303 | }; | ||
304 | pi4 { | ||
305 | nvidia,pins = "pi4"; | ||
306 | nvidia,function = "gmi"; | ||
307 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
308 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
309 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
310 | }; | ||
311 | pi5 { | ||
312 | nvidia,pins = "pi5"; | ||
166 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 313 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
167 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 314 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
315 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
168 | }; | 316 | }; |
169 | sdmmc3_clk_pa6 { | 317 | pi6 { |
170 | nvidia,pins = "sdmmc3_clk_pa6"; | 318 | nvidia,pins = "pi6"; |
171 | nvidia,function = "sdmmc3"; | ||
172 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
173 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 319 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
174 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 320 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
321 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
175 | }; | 322 | }; |
176 | sdmmc3_cmd_pa7 { | 323 | pi7 { |
177 | nvidia,pins = "sdmmc3_cmd_pa7", | 324 | nvidia,pins = "pi7"; |
178 | "sdmmc3_dat0_pb7", | 325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
179 | "sdmmc3_dat1_pb6", | 326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
180 | "sdmmc3_dat2_pb5", | ||
181 | "sdmmc3_dat3_pb4", | ||
182 | "kb_col4_pq4", | ||
183 | "sdmmc3_clk_lb_out_pee4", | ||
184 | "sdmmc3_clk_lb_in_pee5", | ||
185 | "sdmmc3_cd_n_pv2"; | ||
186 | nvidia,function = "sdmmc3"; | ||
187 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
328 | }; | ||
329 | pj0 { | ||
330 | nvidia,pins = "pj0"; | ||
188 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 331 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
189 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 332 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
333 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
190 | }; | 334 | }; |
191 | sdmmc4_clk_pcc4 { | 335 | pj2 { |
192 | nvidia,pins = "sdmmc4_clk_pcc4"; | 336 | nvidia,pins = "pj2"; |
193 | nvidia,function = "sdmmc4"; | 337 | nvidia,function = "rsvd1"; |
338 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
339 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
340 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
341 | }; | ||
342 | uart2_cts_n_pj5 { | ||
343 | nvidia,pins = "uart2_cts_n_pj5"; | ||
344 | nvidia,function = "gmi"; | ||
345 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
346 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
347 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
348 | }; | ||
349 | uart2_rts_n_pj6 { | ||
350 | nvidia,pins = "uart2_rts_n_pj6"; | ||
351 | nvidia,function = "gmi"; | ||
352 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
353 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
354 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
355 | }; | ||
356 | pj7 { | ||
357 | nvidia,pins = "pj7"; | ||
358 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
194 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 360 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
361 | }; | ||
362 | pk0 { | ||
363 | nvidia,pins = "pk0"; | ||
364 | nvidia,function = "rsvd1"; | ||
365 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
366 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
367 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
368 | }; | ||
369 | pk1 { | ||
370 | nvidia,pins = "pk1"; | ||
195 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 371 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
196 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 372 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
373 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
197 | }; | 374 | }; |
198 | sdmmc4_cmd_pt7 { | 375 | pk2 { |
199 | nvidia,pins = "sdmmc4_cmd_pt7", | 376 | nvidia,pins = "pk2"; |
200 | "sdmmc4_dat0_paa0", | 377 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
201 | "sdmmc4_dat1_paa1", | 378 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
202 | "sdmmc4_dat2_paa2", | ||
203 | "sdmmc4_dat3_paa3", | ||
204 | "sdmmc4_dat4_paa4", | ||
205 | "sdmmc4_dat5_paa5", | ||
206 | "sdmmc4_dat6_paa6", | ||
207 | "sdmmc4_dat7_paa7"; | ||
208 | nvidia,function = "sdmmc4"; | ||
209 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 379 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
380 | }; | ||
381 | pk3 { | ||
382 | nvidia,pins = "pk3"; | ||
383 | nvidia,function = "gmi"; | ||
384 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
385 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
386 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
387 | }; | ||
388 | pk4 { | ||
389 | nvidia,pins = "pk4"; | ||
210 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 390 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 391 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
392 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
212 | }; | 393 | }; |
213 | pwr_i2c_scl_pz6 { | 394 | spdif_out_pk5 { |
214 | nvidia,pins = "pwr_i2c_scl_pz6", | 395 | nvidia,pins = "spdif_out_pk5"; |
215 | "pwr_i2c_sda_pz7"; | 396 | nvidia,function = "rsvd2"; |
216 | nvidia,function = "i2cpwr"; | 397 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
398 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
399 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
400 | }; | ||
401 | spdif_in_pk6 { | ||
402 | nvidia,pins = "spdif_in_pk6"; | ||
403 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
404 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
405 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
406 | }; | ||
407 | pk7 { | ||
408 | nvidia,pins = "pk7"; | ||
409 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
410 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
217 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 411 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
412 | }; | ||
413 | dap1_fs_pn0 { | ||
414 | nvidia,pins = "dap1_fs_pn0"; | ||
415 | nvidia,function = "rsvd4"; | ||
416 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
417 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
418 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
419 | }; | ||
420 | dap1_din_pn1 { | ||
421 | nvidia,pins = "dap1_din_pn1"; | ||
422 | nvidia,function = "rsvd4"; | ||
423 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
424 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
425 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
426 | }; | ||
427 | dap1_dout_pn2 { | ||
428 | nvidia,pins = "dap1_dout_pn2"; | ||
429 | nvidia,function = "i2s0"; | ||
430 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
431 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
432 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
433 | }; | ||
434 | dap1_sclk_pn3 { | ||
435 | nvidia,pins = "dap1_sclk_pn3"; | ||
436 | nvidia,function = "rsvd4"; | ||
437 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
438 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
439 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
440 | }; | ||
441 | usb_vbus_en0_pn4 { | ||
442 | nvidia,pins = "usb_vbus_en0_pn4"; | ||
443 | nvidia,function = "usb"; | ||
218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 444 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 445 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
220 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 446 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
221 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | 447 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
222 | }; | 448 | }; |
223 | jtag_rtck { | 449 | usb_vbus_en1_pn5 { |
224 | nvidia,pins = "jtag_rtck"; | 450 | nvidia,pins = "usb_vbus_en1_pn5"; |
225 | nvidia,function = "rtck"; | 451 | nvidia,function = "usb"; |
452 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
453 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
454 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
455 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
456 | }; | ||
457 | hdmi_int_pn7 { | ||
458 | nvidia,pins = "hdmi_int_pn7"; | ||
459 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
460 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
461 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
462 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
463 | }; | ||
464 | ulpi_data7_po0 { | ||
465 | nvidia,pins = "ulpi_data7_po0"; | ||
466 | nvidia,function = "ulpi"; | ||
467 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
468 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
469 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
470 | }; | ||
471 | ulpi_data0_po1 { | ||
472 | nvidia,pins = "ulpi_data0_po1"; | ||
473 | nvidia,function = "ulpi"; | ||
474 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
475 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
476 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
477 | }; | ||
478 | ulpi_data1_po2 { | ||
479 | nvidia,pins = "ulpi_data1_po2"; | ||
480 | nvidia,function = "ulpi"; | ||
481 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
482 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
483 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
484 | }; | ||
485 | ulpi_data2_po3 { | ||
486 | nvidia,pins = "ulpi_data2_po3"; | ||
487 | nvidia,function = "ulpi"; | ||
488 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
489 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
490 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
491 | }; | ||
492 | ulpi_data3_po4 { | ||
493 | nvidia,pins = "ulpi_data3_po4"; | ||
494 | nvidia,function = "ulpi"; | ||
495 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
496 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 497 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
498 | }; | ||
499 | ulpi_data4_po5 { | ||
500 | nvidia,pins = "ulpi_data4_po5"; | ||
501 | nvidia,function = "ulpi"; | ||
502 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
503 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
504 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
505 | }; | ||
506 | ulpi_data5_po6 { | ||
507 | nvidia,pins = "ulpi_data5_po6"; | ||
508 | nvidia,function = "ulpi"; | ||
509 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
510 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
511 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
512 | }; | ||
513 | ulpi_data6_po7 { | ||
514 | nvidia,pins = "ulpi_data6_po7"; | ||
515 | nvidia,function = "ulpi"; | ||
516 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
517 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
518 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
519 | }; | ||
520 | dap3_fs_pp0 { | ||
521 | nvidia,pins = "dap3_fs_pp0"; | ||
522 | nvidia,function = "i2s2"; | ||
523 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
524 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
525 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
526 | }; | ||
527 | dap3_din_pp1 { | ||
528 | nvidia,pins = "dap3_din_pp1"; | ||
529 | nvidia,function = "i2s2"; | ||
530 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
531 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
532 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
533 | }; | ||
534 | dap3_dout_pp2 { | ||
535 | nvidia,pins = "dap3_dout_pp2"; | ||
536 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
537 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
538 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
539 | }; | ||
540 | dap3_sclk_pp3 { | ||
541 | nvidia,pins = "dap3_sclk_pp3"; | ||
542 | nvidia,function = "rsvd3"; | ||
543 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
544 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
545 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
546 | }; | ||
547 | dap4_fs_pp4 { | ||
548 | nvidia,pins = "dap4_fs_pp4"; | ||
549 | nvidia,function = "rsvd4"; | ||
550 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
551 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
552 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
553 | }; | ||
554 | dap4_din_pp5 { | ||
555 | nvidia,pins = "dap4_din_pp5"; | ||
556 | nvidia,function = "rsvd3"; | ||
557 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
558 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
559 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
560 | }; | ||
561 | dap4_dout_pp6 { | ||
562 | nvidia,pins = "dap4_dout_pp6"; | ||
563 | nvidia,function = "rsvd4"; | ||
564 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
565 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
566 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
567 | }; | ||
568 | dap4_sclk_pp7 { | ||
569 | nvidia,pins = "dap4_sclk_pp7"; | ||
570 | nvidia,function = "rsvd3"; | ||
571 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
572 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
573 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
574 | }; | ||
575 | kb_col0_pq0 { | ||
576 | nvidia,pins = "kb_col0_pq0"; | ||
577 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
578 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
579 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
580 | }; | ||
581 | kb_col1_pq1 { | ||
582 | nvidia,pins = "kb_col1_pq1"; | ||
583 | nvidia,function = "rsvd2"; | ||
584 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
585 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
586 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
587 | }; | ||
588 | kb_col2_pq2 { | ||
589 | nvidia,pins = "kb_col2_pq2"; | ||
590 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
591 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
592 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
593 | }; | ||
594 | kb_col3_pq3 { | ||
595 | nvidia,pins = "kb_col3_pq3"; | ||
596 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
597 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
598 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
599 | }; | ||
600 | kb_col4_pq4 { | ||
601 | nvidia,pins = "kb_col4_pq4"; | ||
602 | nvidia,function = "sdmmc3"; | ||
227 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 603 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
228 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 604 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
605 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
229 | }; | 606 | }; |
230 | clk_32k_in { | 607 | kb_col5_pq5 { |
231 | nvidia,pins = "clk_32k_in"; | 608 | nvidia,pins = "kb_col5_pq5"; |
232 | nvidia,function = "clk"; | 609 | nvidia,function = "rsvd2"; |
610 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
611 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
612 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
613 | }; | ||
614 | kb_col6_pq6 { | ||
615 | nvidia,pins = "kb_col6_pq6"; | ||
616 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
617 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
233 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 618 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
619 | }; | ||
620 | kb_col7_pq7 { | ||
621 | nvidia,pins = "kb_col7_pq7"; | ||
234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 622 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 623 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
624 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
236 | }; | 625 | }; |
237 | core_pwr_req { | 626 | kb_row0_pr0 { |
238 | nvidia,pins = "core_pwr_req"; | 627 | nvidia,pins = "kb_row0_pr0"; |
239 | nvidia,function = "pwron"; | 628 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
629 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
240 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 630 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
631 | }; | ||
632 | kb_row1_pr1 { | ||
633 | nvidia,pins = "kb_row1_pr1"; | ||
241 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
242 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 635 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
243 | }; | 637 | }; |
244 | cpu_pwr_req { | 638 | kb_row2_pr2 { |
245 | nvidia,pins = "cpu_pwr_req"; | 639 | nvidia,pins = "kb_row2_pr2"; |
246 | nvidia,function = "cpu"; | 640 | nvidia,function = "rsvd2"; |
641 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
642 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
247 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 643 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
644 | }; | ||
645 | kb_row3_pr3 { | ||
646 | nvidia,pins = "kb_row3_pr3"; | ||
647 | nvidia,function = "kbc"; | ||
648 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
649 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
650 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
651 | }; | ||
652 | kb_row4_pr4 { | ||
653 | nvidia,pins = "kb_row4_pr4"; | ||
248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 654 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
249 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 655 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
656 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
250 | }; | 657 | }; |
251 | pwr_int_n { | 658 | kb_row5_pr5 { |
252 | nvidia,pins = "pwr_int_n"; | 659 | nvidia,pins = "kb_row5_pr5"; |
253 | nvidia,function = "pmi"; | 660 | nvidia,function = "rsvd3"; |
661 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
662 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
663 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
664 | }; | ||
665 | kb_row6_pr6 { | ||
666 | nvidia,pins = "kb_row6_pr6"; | ||
667 | nvidia,function = "kbc"; | ||
668 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
669 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
670 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
671 | }; | ||
672 | kb_row7_pr7 { | ||
673 | nvidia,pins = "kb_row7_pr7"; | ||
674 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
675 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 676 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
255 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 677 | }; |
678 | kb_row8_ps0 { | ||
679 | nvidia,pins = "kb_row8_ps0"; | ||
680 | nvidia,function = "rsvd2"; | ||
681 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
682 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
683 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
684 | }; | ||
685 | kb_row9_ps1 { | ||
686 | nvidia,pins = "kb_row9_ps1"; | ||
687 | nvidia,function = "uarta"; | ||
688 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
256 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 689 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
690 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
257 | }; | 691 | }; |
258 | reset_out_n { | 692 | kb_row10_ps2 { |
259 | nvidia,pins = "reset_out_n"; | 693 | nvidia,pins = "kb_row10_ps2"; |
260 | nvidia,function = "reset_out_n"; | 694 | nvidia,function = "uarta"; |
695 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
696 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
697 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
698 | }; | ||
699 | kb_row11_ps3 { | ||
700 | nvidia,pins = "kb_row11_ps3"; | ||
701 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
702 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
261 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 703 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
704 | }; | ||
705 | kb_row12_ps4 { | ||
706 | nvidia,pins = "kb_row12_ps4"; | ||
262 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 707 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
263 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 708 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
709 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
264 | }; | 710 | }; |
265 | clk3_out_pee0 { | 711 | kb_row13_ps5 { |
266 | nvidia,pins = "clk3_out_pee0"; | 712 | nvidia,pins = "kb_row13_ps5"; |
267 | nvidia,function = "extperiph3"; | 713 | nvidia,function = "rsvd2"; |
714 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
715 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
268 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 716 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
717 | }; | ||
718 | kb_row14_ps6 { | ||
719 | nvidia,pins = "kb_row14_ps6"; | ||
720 | nvidia,function = "rsvd2"; | ||
721 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
722 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
723 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
724 | }; | ||
725 | kb_row15_ps7 { | ||
726 | nvidia,pins = "kb_row15_ps7"; | ||
269 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 727 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
270 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 728 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
729 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
271 | }; | 730 | }; |
272 | gen1_i2c_sda_pc5 { | 731 | kb_row16_pt0 { |
273 | nvidia,pins = "gen1_i2c_sda_pc5", | 732 | nvidia,pins = "kb_row16_pt0"; |
274 | "gen1_i2c_scl_pc4"; | 733 | nvidia,function = "rsvd2"; |
275 | nvidia,function = "i2c1"; | 734 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
735 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
736 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
737 | }; | ||
738 | kb_row17_pt1 { | ||
739 | nvidia,pins = "kb_row17_pt1"; | ||
740 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
741 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
276 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 742 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
743 | }; | ||
744 | gen2_i2c_scl_pt5 { | ||
745 | nvidia,pins = "gen2_i2c_scl_pt5"; | ||
746 | nvidia,function = "i2c2"; | ||
277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 747 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
278 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 748 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
279 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 749 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
280 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | 750 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
281 | }; | 751 | }; |
282 | hdmi_cec_pee3 { | 752 | gen2_i2c_sda_pt6 { |
283 | nvidia,pins = "hdmi_cec_pee3"; | 753 | nvidia,pins = "gen2_i2c_sda_pt6"; |
284 | nvidia,function = "cec"; | 754 | nvidia,function = "i2c2"; |
755 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
756 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
285 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 757 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
758 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
759 | }; | ||
760 | sdmmc4_cmd_pt7 { | ||
761 | nvidia,pins = "sdmmc4_cmd_pt7"; | ||
762 | nvidia,function = "sdmmc4"; | ||
286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 763 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 764 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
288 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 765 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
289 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
290 | }; | 766 | }; |
291 | hdmi_int_pn7 { | 767 | pu0 { |
292 | nvidia,pins = "hdmi_int_pn7"; | 768 | nvidia,pins = "pu0"; |
769 | nvidia,function = "rsvd4"; | ||
770 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
771 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
772 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
773 | }; | ||
774 | pu1 { | ||
775 | nvidia,pins = "pu1"; | ||
776 | nvidia,function = "rsvd1"; | ||
777 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
778 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
779 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
780 | }; | ||
781 | pu2 { | ||
782 | nvidia,pins = "pu2"; | ||
293 | nvidia,function = "rsvd1"; | 783 | nvidia,function = "rsvd1"; |
784 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
785 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
786 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
787 | }; | ||
788 | pu3 { | ||
789 | nvidia,pins = "pu3"; | ||
790 | nvidia,function = "gmi"; | ||
791 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
792 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
793 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
794 | }; | ||
795 | pu4 { | ||
796 | nvidia,pins = "pu4"; | ||
797 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
798 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
799 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
800 | }; | ||
801 | pu5 { | ||
802 | nvidia,pins = "pu5"; | ||
803 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
804 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
294 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 805 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
806 | }; | ||
807 | pu6 { | ||
808 | nvidia,pins = "pu6"; | ||
809 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
810 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
811 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
812 | }; | ||
813 | pv0 { | ||
814 | nvidia,pins = "pv0"; | ||
815 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
816 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
817 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
818 | }; | ||
819 | pv1 { | ||
820 | nvidia,pins = "pv1"; | ||
821 | nvidia,function = "rsvd1"; | ||
295 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | 822 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
823 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
824 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
825 | }; | ||
826 | sdmmc3_cd_n_pv2 { | ||
827 | nvidia,pins = "sdmmc3_cd_n_pv2"; | ||
828 | nvidia,function = "sdmmc3"; | ||
829 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
296 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 830 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
831 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
832 | }; | ||
833 | sdmmc1_wp_n_pv3 { | ||
834 | nvidia,pins = "sdmmc1_wp_n_pv3"; | ||
835 | nvidia,function = "sdmmc1"; | ||
836 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
837 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
838 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
297 | }; | 839 | }; |
298 | ddc_scl_pv4 { | 840 | ddc_scl_pv4 { |
299 | nvidia,pins = "ddc_scl_pv4", | 841 | nvidia,pins = "ddc_scl_pv4"; |
300 | "ddc_sda_pv5"; | ||
301 | nvidia,function = "i2c4"; | 842 | nvidia,function = "i2c4"; |
843 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
844 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
302 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 845 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
846 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; | ||
847 | }; | ||
848 | ddc_sda_pv5 { | ||
849 | nvidia,pins = "ddc_sda_pv5"; | ||
850 | nvidia,function = "i2c4"; | ||
303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 851 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
304 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 852 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
305 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 853 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
306 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | 854 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; |
307 | }; | 855 | }; |
308 | kb_row10_ps2 { | 856 | gpio_w2_aud_pw2 { |
309 | nvidia,pins = "kb_row10_ps2"; | 857 | nvidia,pins = "gpio_w2_aud_pw2"; |
310 | nvidia,function = "uarta"; | 858 | nvidia,function = "rsvd2"; |
311 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 859 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
860 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
861 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
862 | }; | ||
863 | gpio_w3_aud_pw3 { | ||
864 | nvidia,pins = "gpio_w3_aud_pw3"; | ||
865 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 866 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
313 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 867 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
314 | }; | 868 | }; |
315 | kb_row9_ps1 { | 869 | dap_mclk1_pw4 { |
316 | nvidia,pins = "kb_row9_ps1"; | 870 | nvidia,pins = "dap_mclk1_pw4"; |
317 | nvidia,function = "uarta"; | 871 | nvidia,function = "extperiph1"; |
318 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 872 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 873 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
320 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 874 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
321 | }; | 875 | }; |
322 | usb_vbus_en0_pn4 { | 876 | clk2_out_pw5 { |
323 | nvidia,pins = "usb_vbus_en0_pn4", | 877 | nvidia,pins = "clk2_out_pw5"; |
324 | "usb_vbus_en1_pn5"; | 878 | nvidia,function = "rsvd2"; |
325 | nvidia,function = "usb"; | 879 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
880 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
881 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
882 | }; | ||
883 | uart3_txd_pw6 { | ||
884 | nvidia,pins = "uart3_txd_pw6"; | ||
885 | nvidia,function = "rsvd2"; | ||
886 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
887 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
888 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
889 | }; | ||
890 | uart3_rxd_pw7 { | ||
891 | nvidia,pins = "uart3_rxd_pw7"; | ||
892 | nvidia,function = "rsvd2"; | ||
893 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
894 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
895 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
896 | }; | ||
897 | dvfs_pwm_px0 { | ||
898 | nvidia,pins = "dvfs_pwm_px0"; | ||
899 | nvidia,function = "cldvfs"; | ||
900 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
901 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
902 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
903 | }; | ||
904 | gpio_x1_aud_px1 { | ||
905 | nvidia,pins = "gpio_x1_aud_px1"; | ||
906 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
907 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
326 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 908 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
909 | }; | ||
910 | dvfs_clk_px2 { | ||
911 | nvidia,pins = "dvfs_clk_px2"; | ||
912 | nvidia,function = "cldvfs"; | ||
327 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 913 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
328 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 914 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
329 | nvidia,lock = <TEGRA_PIN_DISABLE>; | 915 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
330 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
331 | }; | 916 | }; |
332 | drive_sdio1 { | 917 | gpio_x3_aud_px3 { |
333 | nvidia,pins = "drive_sdio1"; | 918 | nvidia,pins = "gpio_x3_aud_px3"; |
334 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | 919 | nvidia,function = "rsvd4"; |
335 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | 920 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
336 | nvidia,pull-down-strength = <36>; | 921 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
337 | nvidia,pull-up-strength = <20>; | 922 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
338 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; | 923 | }; |
339 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; | 924 | gpio_x4_aud_px4 { |
340 | }; | 925 | nvidia,pins = "gpio_x4_aud_px4"; |
341 | drive_sdio3 { | ||
342 | nvidia,pins = "drive_sdio3"; | ||
343 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | ||
344 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | ||
345 | nvidia,pull-down-strength = <22>; | ||
346 | nvidia,pull-up-strength = <36>; | ||
347 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
348 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
349 | }; | ||
350 | drive_gma { | ||
351 | nvidia,pins = "drive_gma"; | ||
352 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | ||
353 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | ||
354 | nvidia,pull-down-strength = <2>; | ||
355 | nvidia,pull-up-strength = <1>; | ||
356 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
357 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | ||
358 | nvidia,drive-type = <1>; | ||
359 | }; | ||
360 | codec_irq_l { | ||
361 | nvidia,pins = "ph4"; | ||
362 | nvidia,function = "gmi"; | ||
363 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 926 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
364 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 927 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
365 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 928 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
366 | }; | 929 | }; |
367 | lcd_bl_en { | 930 | gpio_x5_aud_px5 { |
368 | nvidia,pins = "ph2"; | 931 | nvidia,pins = "gpio_x5_aud_px5"; |
932 | nvidia,function = "rsvd4"; | ||
933 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
934 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
935 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
936 | }; | ||
937 | gpio_x6_aud_px6 { | ||
938 | nvidia,pins = "gpio_x6_aud_px6"; | ||
369 | nvidia,function = "gmi"; | 939 | nvidia,function = "gmi"; |
370 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | 940 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
941 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
942 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
943 | }; | ||
944 | gpio_x7_aud_px7 { | ||
945 | nvidia,pins = "gpio_x7_aud_px7"; | ||
946 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
371 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 947 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
372 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 948 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
373 | }; | 949 | }; |
374 | touch_irq_l { | 950 | ulpi_clk_py0 { |
375 | nvidia,pins = "gpio_w3_aud_pw3"; | 951 | nvidia,pins = "ulpi_clk_py0"; |
376 | nvidia,function = "spi6"; | 952 | nvidia,function = "spi1"; |
377 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 953 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
378 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 954 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
379 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 955 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
380 | }; | 956 | }; |
381 | tpm_davint_l { | 957 | ulpi_dir_py1 { |
382 | nvidia,pins = "ph6"; | 958 | nvidia,pins = "ulpi_dir_py1"; |
383 | nvidia,function = "gmi"; | 959 | nvidia,function = "spi1"; |
384 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 960 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
385 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 961 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
386 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 962 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
387 | }; | 963 | }; |
388 | ts_irq_l { | 964 | ulpi_nxt_py2 { |
389 | nvidia,pins = "pk2"; | 965 | nvidia,pins = "ulpi_nxt_py2"; |
390 | nvidia,function = "gmi"; | 966 | nvidia,function = "spi1"; |
391 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 967 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
392 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 968 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
393 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 969 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
394 | }; | 970 | }; |
395 | ts_reset_l { | 971 | ulpi_stp_py3 { |
396 | nvidia,pins = "pk4"; | 972 | nvidia,pins = "ulpi_stp_py3"; |
397 | nvidia,function = "gmi"; | 973 | nvidia,function = "spi1"; |
398 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 974 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
399 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 975 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
400 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 976 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
401 | }; | 977 | }; |
402 | ts_shdn_l { | 978 | sdmmc1_dat3_py4 { |
403 | nvidia,pins = "pk1"; | 979 | nvidia,pins = "sdmmc1_dat3_py4"; |
404 | nvidia,function = "gmi"; | 980 | nvidia,function = "sdmmc1"; |
405 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 981 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
406 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 982 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
407 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 983 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
408 | }; | 984 | }; |
409 | ph7 { | 985 | sdmmc1_dat2_py5 { |
410 | nvidia,pins = "ph7"; | 986 | nvidia,pins = "sdmmc1_dat2_py5"; |
411 | nvidia,function = "gmi"; | 987 | nvidia,function = "sdmmc1"; |
412 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 988 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
413 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 989 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
414 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 990 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
415 | }; | 991 | }; |
416 | kb_col0_ap { | 992 | sdmmc1_dat1_py6 { |
417 | nvidia,pins = "kb_col0_pq0"; | 993 | nvidia,pins = "sdmmc1_dat1_py6"; |
418 | nvidia,function = "rsvd4"; | 994 | nvidia,function = "sdmmc1"; |
419 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 995 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
420 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 996 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
421 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 997 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
422 | }; | 998 | }; |
423 | lid_open { | 999 | sdmmc1_dat0_py7 { |
424 | nvidia,pins = "kb_row4_pr4"; | 1000 | nvidia,pins = "sdmmc1_dat0_py7"; |
425 | nvidia,function = "rsvd3"; | 1001 | nvidia,function = "sdmmc1"; |
426 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 1002 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
427 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1003 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
428 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 1004 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
429 | }; | 1005 | }; |
430 | en_vdd_sd { | 1006 | sdmmc1_clk_pz0 { |
431 | nvidia,pins = "kb_row0_pr0"; | 1007 | nvidia,pins = "sdmmc1_clk_pz0"; |
432 | nvidia,function = "rsvd4"; | 1008 | nvidia,function = "sdmmc1"; |
433 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 1009 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
434 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1010 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
435 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 1011 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
436 | }; | 1012 | }; |
437 | ac_ok { | 1013 | sdmmc1_cmd_pz1 { |
438 | nvidia,pins = "pj0"; | 1014 | nvidia,pins = "sdmmc1_cmd_pz1"; |
439 | nvidia,function = "gmi"; | 1015 | nvidia,function = "sdmmc1"; |
440 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 1016 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
441 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1017 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
442 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 1018 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
443 | }; | 1019 | }; |
444 | sensor_irq_l { | 1020 | pwr_i2c_scl_pz6 { |
445 | nvidia,pins = "pi6"; | 1021 | nvidia,pins = "pwr_i2c_scl_pz6"; |
446 | nvidia,function = "gmi"; | 1022 | nvidia,function = "i2cpwr"; |
447 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 1023 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
448 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1024 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
449 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 1025 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
1026 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
450 | }; | 1027 | }; |
451 | wifi_en { | 1028 | pwr_i2c_sda_pz7 { |
452 | nvidia,pins = "gpio_x7_aud_px7"; | 1029 | nvidia,pins = "pwr_i2c_sda_pz7"; |
453 | nvidia,function = "rsvd4"; | 1030 | nvidia,function = "i2cpwr"; |
454 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 1031 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
455 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1032 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1033 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1034 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
1035 | }; | ||
1036 | sdmmc4_dat0_paa0 { | ||
1037 | nvidia,pins = "sdmmc4_dat0_paa0"; | ||
1038 | nvidia,function = "sdmmc4"; | ||
1039 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1040 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1041 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1042 | }; | ||
1043 | sdmmc4_dat1_paa1 { | ||
1044 | nvidia,pins = "sdmmc4_dat1_paa1"; | ||
1045 | nvidia,function = "sdmmc4"; | ||
1046 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1047 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1048 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1049 | }; | ||
1050 | sdmmc4_dat2_paa2 { | ||
1051 | nvidia,pins = "sdmmc4_dat2_paa2"; | ||
1052 | nvidia,function = "sdmmc4"; | ||
1053 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1054 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1055 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1056 | }; | ||
1057 | sdmmc4_dat3_paa3 { | ||
1058 | nvidia,pins = "sdmmc4_dat3_paa3"; | ||
1059 | nvidia,function = "sdmmc4"; | ||
1060 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1061 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1062 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1063 | }; | ||
1064 | sdmmc4_dat4_paa4 { | ||
1065 | nvidia,pins = "sdmmc4_dat4_paa4"; | ||
1066 | nvidia,function = "sdmmc4"; | ||
1067 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1068 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1069 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1070 | }; | ||
1071 | sdmmc4_dat5_paa5 { | ||
1072 | nvidia,pins = "sdmmc4_dat5_paa5"; | ||
1073 | nvidia,function = "sdmmc4"; | ||
1074 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1075 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1076 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1077 | }; | ||
1078 | sdmmc4_dat6_paa6 { | ||
1079 | nvidia,pins = "sdmmc4_dat6_paa6"; | ||
1080 | nvidia,function = "sdmmc4"; | ||
1081 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1082 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1083 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1084 | }; | ||
1085 | sdmmc4_dat7_paa7 { | ||
1086 | nvidia,pins = "sdmmc4_dat7_paa7"; | ||
1087 | nvidia,function = "sdmmc4"; | ||
1088 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | ||
1089 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1090 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1091 | }; | ||
1092 | pbb0 { | ||
1093 | nvidia,pins = "pbb0"; | ||
1094 | nvidia,function = "vgp6"; | ||
1095 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1096 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
456 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 1097 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
457 | }; | 1098 | }; |
458 | en_vdd_bl { | 1099 | cam_i2c_scl_pbb1 { |
459 | nvidia,pins = "dap3_dout_pp2"; | 1100 | nvidia,pins = "cam_i2c_scl_pbb1"; |
460 | nvidia,function = "i2s2"; | 1101 | nvidia,function = "rsvd3"; |
1102 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1103 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1104 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1105 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
1106 | }; | ||
1107 | cam_i2c_sda_pbb2 { | ||
1108 | nvidia,pins = "cam_i2c_sda_pbb2"; | ||
1109 | nvidia,function = "rsvd3"; | ||
1110 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1111 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1112 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1113 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
1114 | }; | ||
1115 | pbb3 { | ||
1116 | nvidia,pins = "pbb3"; | ||
1117 | nvidia,function = "vgp3"; | ||
1118 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1119 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1120 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1121 | }; | ||
1122 | pbb4 { | ||
1123 | nvidia,pins = "pbb4"; | ||
1124 | nvidia,function = "vgp4"; | ||
1125 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1126 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1127 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1128 | }; | ||
1129 | pbb5 { | ||
1130 | nvidia,pins = "pbb5"; | ||
1131 | nvidia,function = "rsvd3"; | ||
1132 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1133 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1134 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1135 | }; | ||
1136 | pbb6 { | ||
1137 | nvidia,pins = "pbb6"; | ||
1138 | nvidia,function = "rsvd2"; | ||
1139 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1140 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1141 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1142 | }; | ||
1143 | pbb7 { | ||
1144 | nvidia,pins = "pbb7"; | ||
1145 | nvidia,function = "rsvd2"; | ||
1146 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1147 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1148 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1149 | }; | ||
1150 | cam_mclk_pcc0 { | ||
1151 | nvidia,pins = "cam_mclk_pcc0"; | ||
1152 | nvidia,function = "vi"; | ||
1153 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1154 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1155 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1156 | }; | ||
1157 | pcc1 { | ||
1158 | nvidia,pins = "pcc1"; | ||
1159 | nvidia,function = "rsvd2"; | ||
461 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | 1160 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1161 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1162 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1163 | }; | ||
1164 | pcc2 { | ||
1165 | nvidia,pins = "pcc2"; | ||
1166 | nvidia,function = "rsvd2"; | ||
1167 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1168 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1170 | }; | ||
1171 | sdmmc4_clk_pcc4 { | ||
1172 | nvidia,pins = "sdmmc4_clk_pcc4"; | ||
1173 | nvidia,function = "sdmmc4"; | ||
1174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
462 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
1176 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1177 | }; | ||
1178 | clk2_req_pcc5 { | ||
1179 | nvidia,pins = "clk2_req_pcc5"; | ||
1180 | nvidia,function = "rsvd2"; | ||
1181 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1182 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
463 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 1183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
464 | }; | 1184 | }; |
465 | en_vdd_hdmi { | 1185 | pex_l0_rst_n_pdd1 { |
466 | nvidia,pins = "spdif_in_pk6"; | 1186 | nvidia,pins = "pex_l0_rst_n_pdd1"; |
467 | nvidia,function = "spdif"; | 1187 | nvidia,function = "rsvd2"; |
1188 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1189 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1190 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1191 | }; | ||
1192 | pex_l0_clkreq_n_pdd2 { | ||
1193 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; | ||
1194 | nvidia,function = "rsvd2"; | ||
1195 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1196 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1197 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1198 | }; | ||
1199 | pex_wake_n_pdd3 { | ||
1200 | nvidia,pins = "pex_wake_n_pdd3"; | ||
1201 | nvidia,function = "rsvd2"; | ||
1202 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1203 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1205 | }; | ||
1206 | pex_l1_rst_n_pdd5 { | ||
1207 | nvidia,pins = "pex_l1_rst_n_pdd5"; | ||
1208 | nvidia,function = "rsvd2"; | ||
1209 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1210 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1211 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1212 | }; | ||
1213 | pex_l1_clkreq_n_pdd6 { | ||
1214 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; | ||
1215 | nvidia,function = "rsvd2"; | ||
1216 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1217 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1218 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1219 | }; | ||
1220 | clk3_out_pee0 { | ||
1221 | nvidia,pins = "clk3_out_pee0"; | ||
1222 | nvidia,function = "rsvd2"; | ||
468 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | 1223 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1225 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1226 | }; | ||
1227 | clk3_req_pee1 { | ||
1228 | nvidia,pins = "clk3_req_pee1"; | ||
1229 | nvidia,function = "rsvd2"; | ||
1230 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1231 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1232 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1233 | }; | ||
1234 | dap_mclk1_req_pee2 { | ||
1235 | nvidia,pins = "dap_mclk1_req_pee2"; | ||
1236 | nvidia,function = "rsvd4"; | ||
1237 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1238 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1239 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1240 | }; | ||
1241 | hdmi_cec_pee3 { | ||
1242 | nvidia,pins = "hdmi_cec_pee3"; | ||
1243 | nvidia,function = "cec"; | ||
1244 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
1245 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1246 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | ||
1247 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | ||
1248 | }; | ||
1249 | sdmmc3_clk_lb_out_pee4 { | ||
1250 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; | ||
1251 | nvidia,function = "sdmmc3"; | ||
1252 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
469 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
470 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 1254 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
471 | }; | 1255 | }; |
472 | soc_warm_reset_l { | 1256 | sdmmc3_clk_lb_in_pee5 { |
473 | nvidia,pins = "pi5"; | 1257 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; |
474 | nvidia,function = "gmi"; | 1258 | nvidia,function = "sdmmc3"; |
475 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 1259 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
476 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1260 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
477 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | 1261 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
478 | }; | 1262 | }; |
479 | hp_det_l { | 1263 | dp_hpd_pff0 { |
480 | nvidia,pins = "pi7"; | 1264 | nvidia,pins = "dp_hpd_pff0"; |
481 | nvidia,function = "rsvd1"; | 1265 | nvidia,function = "dp"; |
482 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | 1266 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
483 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
484 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 1268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
485 | }; | 1269 | }; |
486 | mic_det_l { | 1270 | usb_vbus_en2_pff1 { |
487 | nvidia,pins = "kb_row7_pr7"; | 1271 | nvidia,pins = "usb_vbus_en2_pff1"; |
488 | nvidia,function = "rsvd2"; | 1272 | nvidia,function = "rsvd2"; |
489 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | 1273 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
1274 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1275 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1276 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
1277 | }; | ||
1278 | pff2 { | ||
1279 | nvidia,pins = "pff2"; | ||
1280 | nvidia,function = "rsvd2"; | ||
1281 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | ||
1282 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | ||
1283 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1284 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | ||
1285 | }; | ||
1286 | core_pwr_req { | ||
1287 | nvidia,pins = "core_pwr_req"; | ||
1288 | nvidia,function = "pwron"; | ||
1289 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
1290 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1291 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1292 | }; | ||
1293 | cpu_pwr_req { | ||
1294 | nvidia,pins = "cpu_pwr_req"; | ||
1295 | nvidia,function = "cpu"; | ||
1296 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
1297 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | ||
1298 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | ||
1299 | }; | ||
1300 | pwr_int_n { | ||
1301 | nvidia,pins = "pwr_int_n"; | ||
1302 | nvidia,function = "pmi"; | ||
1303 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | ||
490 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | 1304 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
491 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | 1305 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
492 | }; | 1306 | }; |
493 | }; | 1307 | reset_out_n { |
494 | }; | 1308 | nvidia,pins = "reset_out_n"; |
495 | 1309 | nvidia,function = "reset_out_n"; | |
496 | serial@0,70006000 { | 1310 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
497 | /* Debug connector on the bottom of the board near SD card. */ | 1311 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
498 | status = "okay"; | 1312 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
499 | }; | ||
500 | |||
501 | pwm@0,7000a000 { | ||
502 | status = "okay"; | ||
503 | }; | ||
504 | |||
505 | i2c@0,7000c000 { | ||
506 | status = "okay"; | ||
507 | clock-frequency = <100000>; | ||
508 | |||
509 | acodec: audio-codec@10 { | ||
510 | compatible = "maxim,max98090"; | ||
511 | reg = <0x10>; | ||
512 | interrupt-parent = <&gpio>; | ||
513 | interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | ||
514 | }; | ||
515 | |||
516 | temperature-sensor@4c { | ||
517 | compatible = "ti,tmp451"; | ||
518 | reg = <0x4c>; | ||
519 | interrupt-parent = <&gpio>; | ||
520 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; | ||
521 | |||
522 | #thermal-sensor-cells = <1>; | ||
523 | }; | ||
524 | }; | ||
525 | |||
526 | i2c@0,7000c400 { | ||
527 | status = "okay"; | ||
528 | clock-frequency = <100000>; | ||
529 | }; | ||
530 | |||
531 | i2c@0,7000c500 { | ||
532 | status = "okay"; | ||
533 | clock-frequency = <400000>; | ||
534 | |||
535 | tpm@20 { | ||
536 | compatible = "infineon,slb9645tt"; | ||
537 | reg = <0x20>; | ||
538 | }; | ||
539 | }; | ||
540 | |||
541 | hdmi_ddc: i2c@0,7000c700 { | ||
542 | status = "okay"; | ||
543 | clock-frequency = <100000>; | ||
544 | }; | ||
545 | |||
546 | i2c@0,7000d000 { | ||
547 | status = "okay"; | ||
548 | clock-frequency = <400000>; | ||
549 | |||
550 | pmic: pmic@40 { | ||
551 | compatible = "ams,as3722"; | ||
552 | reg = <0x40>; | ||
553 | interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; | ||
554 | |||
555 | ams,system-power-controller; | ||
556 | |||
557 | #interrupt-cells = <2>; | ||
558 | interrupt-controller; | ||
559 | |||
560 | gpio-controller; | ||
561 | #gpio-cells = <2>; | ||
562 | |||
563 | pinctrl-names = "default"; | ||
564 | pinctrl-0 = <&as3722_default>; | ||
565 | |||
566 | as3722_default: pinmux { | ||
567 | gpio0 { | ||
568 | pins = "gpio0"; | ||
569 | function = "gpio"; | ||
570 | bias-pull-down; | ||
571 | }; | ||
572 | |||
573 | gpio1 { | ||
574 | pins = "gpio1"; | ||
575 | function = "gpio"; | ||
576 | bias-pull-up; | ||
577 | }; | ||
578 | |||
579 | gpio2_4_7 { | ||
580 | pins = "gpio2", "gpio4", "gpio7"; | ||
581 | function = "gpio"; | ||
582 | bias-pull-up; | ||
583 | }; | ||
584 | |||
585 | gpio3_6 { | ||
586 | pins = "gpio3", "gpio6"; | ||
587 | bias-high-impedance; | ||
588 | }; | ||
589 | |||
590 | gpio5 { | ||
591 | pins = "gpio5"; | ||
592 | function = "clk32k-out"; | ||
593 | bias-pull-down; | ||
594 | }; | ||
595 | }; | 1313 | }; |
596 | 1314 | owr { | |
597 | regulators { | 1315 | nvidia,pins = "owr"; |
598 | vsup-sd2-supply = <&vdd_5v0_sys>; | 1316 | nvidia,function = "rsvd2"; |
599 | vsup-sd3-supply = <&vdd_5v0_sys>; | 1317 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
600 | vsup-sd4-supply = <&vdd_5v0_sys>; | 1318 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
601 | vsup-sd5-supply = <&vdd_5v0_sys>; | 1319 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
602 | vin-ldo0-supply = <&vdd_1v35_lp0>; | 1320 | nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; |
603 | vin-ldo1-6-supply = <&vdd_3v3_run>; | ||
604 | vin-ldo2-5-7-supply = <&vddio_1v8>; | ||
605 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | ||
606 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | ||
607 | vin-ldo11-supply = <&vdd_3v3_run>; | ||
608 | |||
609 | sd0 { | ||
610 | regulator-name = "+VDD_CPU_AP"; | ||
611 | regulator-min-microvolt = <700000>; | ||
612 | regulator-max-microvolt = <1350000>; | ||
613 | regulator-min-microamp = <3500000>; | ||
614 | regulator-max-microamp = <3500000>; | ||
615 | regulator-always-on; | ||
616 | regulator-boot-on; | ||
617 | ams,ext-control = <2>; | ||
618 | }; | ||
619 | |||
620 | sd1 { | ||
621 | regulator-name = "+VDD_CORE"; | ||
622 | regulator-min-microvolt = <700000>; | ||
623 | regulator-max-microvolt = <1350000>; | ||
624 | regulator-min-microamp = <2500000>; | ||
625 | regulator-max-microamp = <4000000>; | ||
626 | regulator-always-on; | ||
627 | regulator-boot-on; | ||
628 | ams,ext-control = <1>; | ||
629 | }; | ||
630 | |||
631 | vdd_1v35_lp0: sd2 { | ||
632 | regulator-name = "+1.35V_LP0(sd2)"; | ||
633 | regulator-min-microvolt = <1350000>; | ||
634 | regulator-max-microvolt = <1350000>; | ||
635 | regulator-always-on; | ||
636 | regulator-boot-on; | ||
637 | }; | ||
638 | |||
639 | sd3 { | ||
640 | regulator-name = "+1.35V_LP0(sd3)"; | ||
641 | regulator-min-microvolt = <1350000>; | ||
642 | regulator-max-microvolt = <1350000>; | ||
643 | regulator-always-on; | ||
644 | regulator-boot-on; | ||
645 | }; | ||
646 | |||
647 | vdd_1v05_run: sd4 { | ||
648 | regulator-name = "+1.05V_RUN"; | ||
649 | regulator-min-microvolt = <1050000>; | ||
650 | regulator-max-microvolt = <1050000>; | ||
651 | }; | ||
652 | |||
653 | vddio_1v8: sd5 { | ||
654 | regulator-name = "+1.8V_VDDIO"; | ||
655 | regulator-min-microvolt = <1800000>; | ||
656 | regulator-max-microvolt = <1800000>; | ||
657 | regulator-boot-on; | ||
658 | regulator-always-on; | ||
659 | }; | ||
660 | |||
661 | sd6 { | ||
662 | regulator-name = "+VDD_GPU_AP"; | ||
663 | regulator-min-microvolt = <650000>; | ||
664 | regulator-max-microvolt = <1200000>; | ||
665 | regulator-min-microamp = <3500000>; | ||
666 | regulator-max-microamp = <3500000>; | ||
667 | regulator-boot-on; | ||
668 | regulator-always-on; | ||
669 | }; | ||
670 | |||
671 | ldo0 { | ||
672 | regulator-name = "+1.05V_RUN_AVDD"; | ||
673 | regulator-min-microvolt = <1050000>; | ||
674 | regulator-max-microvolt = <1050000>; | ||
675 | regulator-boot-on; | ||
676 | regulator-always-on; | ||
677 | ams,ext-control = <1>; | ||
678 | }; | ||
679 | |||
680 | ldo1 { | ||
681 | regulator-name = "+1.8V_RUN_CAM"; | ||
682 | regulator-min-microvolt = <1800000>; | ||
683 | regulator-max-microvolt = <1800000>; | ||
684 | }; | ||
685 | |||
686 | ldo2 { | ||
687 | regulator-name = "+1.2V_GEN_AVDD"; | ||
688 | regulator-min-microvolt = <1200000>; | ||
689 | regulator-max-microvolt = <1200000>; | ||
690 | regulator-boot-on; | ||
691 | regulator-always-on; | ||
692 | }; | ||
693 | |||
694 | ldo3 { | ||
695 | regulator-name = "+1.00V_LP0_VDD_RTC"; | ||
696 | regulator-min-microvolt = <1000000>; | ||
697 | regulator-max-microvolt = <1000000>; | ||
698 | regulator-boot-on; | ||
699 | regulator-always-on; | ||
700 | ams,enable-tracking; | ||
701 | }; | ||
702 | |||
703 | vdd_run_cam: ldo4 { | ||
704 | regulator-name = "+3.3V_RUN_CAM"; | ||
705 | regulator-min-microvolt = <2800000>; | ||
706 | regulator-max-microvolt = <2800000>; | ||
707 | }; | ||
708 | |||
709 | ldo5 { | ||
710 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | ||
711 | regulator-min-microvolt = <1200000>; | ||
712 | regulator-max-microvolt = <1200000>; | ||
713 | }; | ||
714 | |||
715 | vddio_sdmmc3: ldo6 { | ||
716 | regulator-name = "+VDDIO_SDMMC3"; | ||
717 | regulator-min-microvolt = <1800000>; | ||
718 | regulator-max-microvolt = <3300000>; | ||
719 | }; | ||
720 | |||
721 | ldo7 { | ||
722 | regulator-name = "+1.05V_RUN_CAM_REAR"; | ||
723 | regulator-min-microvolt = <1050000>; | ||
724 | regulator-max-microvolt = <1050000>; | ||
725 | }; | ||
726 | |||
727 | ldo9 { | ||
728 | regulator-name = "+2.8V_RUN_TOUCH"; | ||
729 | regulator-min-microvolt = <2800000>; | ||
730 | regulator-max-microvolt = <2800000>; | ||
731 | }; | ||
732 | |||
733 | ldo10 { | ||
734 | regulator-name = "+2.8V_RUN_CAM_AF"; | ||
735 | regulator-min-microvolt = <2800000>; | ||
736 | regulator-max-microvolt = <2800000>; | ||
737 | }; | ||
738 | |||
739 | ldo11 { | ||
740 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | ||
741 | regulator-min-microvolt = <1800000>; | ||
742 | regulator-max-microvolt = <1800000>; | ||
743 | }; | ||
744 | }; | 1321 | }; |
745 | }; | 1322 | clk_32k_in { |
746 | }; | 1323 | nvidia,pins = "clk_32k_in"; |
747 | 1324 | nvidia,function = "clk"; | |
748 | spi@0,7000d400 { | 1325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
749 | status = "okay"; | 1326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
750 | 1327 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
751 | cros_ec: cros-ec@0 { | 1328 | }; |
752 | compatible = "google,cros-ec-spi"; | 1329 | jtag_rtck { |
753 | spi-max-frequency = <3000000>; | 1330 | nvidia,pins = "jtag_rtck"; |
754 | interrupt-parent = <&gpio>; | 1331 | nvidia,function = "rtck"; |
755 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; | 1332 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
756 | reg = <0>; | 1333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
757 | 1334 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
758 | google,cros-ec-spi-msg-delay = <2000>; | ||
759 | |||
760 | i2c-tunnel { | ||
761 | compatible = "google,cros-ec-i2c-tunnel"; | ||
762 | #address-cells = <1>; | ||
763 | #size-cells = <0>; | ||
764 | |||
765 | google,remote-bus = <0>; | ||
766 | |||
767 | charger: bq24735@9 { | ||
768 | compatible = "ti,bq24735"; | ||
769 | reg = <0x9>; | ||
770 | interrupt-parent = <&gpio>; | ||
771 | interrupts = <TEGRA_GPIO(J, 0) | ||
772 | GPIO_ACTIVE_HIGH>; | ||
773 | ti,ac-detect-gpios = <&gpio | ||
774 | TEGRA_GPIO(J, 0) | ||
775 | GPIO_ACTIVE_HIGH>; | ||
776 | }; | ||
777 | |||
778 | battery: sbs-battery@b { | ||
779 | compatible = "sbs,sbs-battery"; | ||
780 | reg = <0xb>; | ||
781 | sbs,i2c-retry-count = <2>; | ||
782 | sbs,poll-retry-count = <10>; | ||
783 | power-supplies = <&charger>; | ||
784 | }; | ||
785 | }; | 1335 | }; |
786 | }; | 1336 | }; |
787 | }; | 1337 | }; |
788 | |||
789 | spi@0,7000da00 { | ||
790 | status = "okay"; | ||
791 | spi-max-frequency = <25000000>; | ||
792 | |||
793 | flash@0 { | ||
794 | compatible = "winbond,w25q32dw"; | ||
795 | reg = <0>; | ||
796 | }; | ||
797 | }; | ||
798 | |||
799 | pmc@0,7000e400 { | ||
800 | nvidia,invert-interrupt; | ||
801 | nvidia,suspend-mode = <0>; | ||
802 | nvidia,cpu-pwr-good-time = <500>; | ||
803 | nvidia,cpu-pwr-off-time = <300>; | ||
804 | nvidia,core-pwr-good-time = <641 3845>; | ||
805 | nvidia,core-pwr-off-time = <61036>; | ||
806 | nvidia,core-power-req-active-high; | ||
807 | nvidia,sys-clock-req-active-high; | ||
808 | }; | ||
809 | |||
810 | hda@0,70030000 { | ||
811 | status = "okay"; | ||
812 | }; | ||
813 | |||
814 | sdhci@0,700b0000 { /* WiFi/BT on this bus */ | ||
815 | status = "okay"; | ||
816 | power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; | ||
817 | bus-width = <4>; | ||
818 | no-1-8-v; | ||
819 | non-removable; | ||
820 | }; | ||
821 | |||
822 | sdhci@0,700b0400 { /* SD Card on this bus */ | ||
823 | status = "okay"; | ||
824 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; | ||
825 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | ||
826 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; | ||
827 | bus-width = <4>; | ||
828 | no-1-8-v; | ||
829 | vqmmc-supply = <&vddio_sdmmc3>; | ||
830 | }; | ||
831 | |||
832 | sdhci@0,700b0600 { /* eMMC on this bus */ | ||
833 | status = "okay"; | ||
834 | bus-width = <8>; | ||
835 | no-1-8-v; | ||
836 | non-removable; | ||
837 | }; | ||
838 | |||
839 | ahub@0,70300000 { | ||
840 | i2s@0,70301100 { | ||
841 | status = "okay"; | ||
842 | }; | ||
843 | }; | ||
844 | |||
845 | usb@0,7d000000 { /* Rear external USB port. */ | ||
846 | status = "okay"; | ||
847 | }; | ||
848 | |||
849 | usb-phy@0,7d000000 { | ||
850 | status = "okay"; | ||
851 | vbus-supply = <&vdd_usb1_vbus>; | ||
852 | }; | ||
853 | |||
854 | usb@0,7d004000 { /* Internal webcam. */ | ||
855 | status = "okay"; | ||
856 | }; | ||
857 | |||
858 | usb-phy@0,7d004000 { | ||
859 | status = "okay"; | ||
860 | vbus-supply = <&vdd_run_cam>; | ||
861 | }; | ||
862 | |||
863 | usb@0,7d008000 { /* Left external USB port. */ | ||
864 | status = "okay"; | ||
865 | }; | ||
866 | |||
867 | usb-phy@0,7d008000 { | ||
868 | status = "okay"; | ||
869 | vbus-supply = <&vdd_usb3_vbus>; | ||
870 | }; | ||
871 | |||
872 | backlight: backlight { | ||
873 | compatible = "pwm-backlight"; | ||
874 | |||
875 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | ||
876 | power-supply = <&vdd_led>; | ||
877 | pwms = <&pwm 1 1000000>; | ||
878 | |||
879 | default-brightness-level = <224>; | ||
880 | brightness-levels = | ||
881 | < 0 1 2 3 4 5 6 7 | ||
882 | 8 9 10 11 12 13 14 15 | ||
883 | 16 17 18 19 20 21 22 23 | ||
884 | 24 25 26 27 28 29 30 31 | ||
885 | 32 33 34 35 36 37 38 39 | ||
886 | 40 41 42 43 44 45 46 47 | ||
887 | 48 49 50 51 52 53 54 55 | ||
888 | 56 57 58 59 60 61 62 63 | ||
889 | 64 65 66 67 68 69 70 71 | ||
890 | 72 73 74 75 76 77 78 79 | ||
891 | 80 81 82 83 84 85 86 87 | ||
892 | 88 89 90 91 92 93 94 95 | ||
893 | 96 97 98 99 100 101 102 103 | ||
894 | 104 105 106 107 108 109 110 111 | ||
895 | 112 113 114 115 116 117 118 119 | ||
896 | 120 121 122 123 124 125 126 127 | ||
897 | 128 129 130 131 132 133 134 135 | ||
898 | 136 137 138 139 140 141 142 143 | ||
899 | 144 145 146 147 148 149 150 151 | ||
900 | 152 153 154 155 156 157 158 159 | ||
901 | 160 161 162 163 164 165 166 167 | ||
902 | 168 169 170 171 172 173 174 175 | ||
903 | 176 177 178 179 180 181 182 183 | ||
904 | 184 185 186 187 188 189 190 191 | ||
905 | 192 193 194 195 196 197 198 199 | ||
906 | 200 201 202 203 204 205 206 207 | ||
907 | 208 209 210 211 212 213 214 215 | ||
908 | 216 217 218 219 220 221 222 223 | ||
909 | 224 225 226 227 228 229 230 231 | ||
910 | 232 233 234 235 236 237 238 239 | ||
911 | 240 241 242 243 244 245 246 247 | ||
912 | 248 249 250 251 252 253 254 255 | ||
913 | 256>; | ||
914 | }; | ||
915 | |||
916 | clocks { | ||
917 | compatible = "simple-bus"; | ||
918 | #address-cells = <1>; | ||
919 | #size-cells = <0>; | ||
920 | |||
921 | clk32k_in: clock@0 { | ||
922 | compatible = "fixed-clock"; | ||
923 | reg = <0>; | ||
924 | #clock-cells = <0>; | ||
925 | clock-frequency = <32768>; | ||
926 | }; | ||
927 | }; | ||
928 | |||
929 | gpio-keys { | ||
930 | compatible = "gpio-keys"; | ||
931 | |||
932 | lid { | ||
933 | label = "Lid"; | ||
934 | gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; | ||
935 | linux,input-type = <5>; | ||
936 | linux,code = <KEY_RESERVED>; | ||
937 | debounce-interval = <1>; | ||
938 | gpio-key,wakeup; | ||
939 | }; | ||
940 | |||
941 | power { | ||
942 | label = "Power"; | ||
943 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | ||
944 | linux,code = <KEY_POWER>; | ||
945 | debounce-interval = <30>; | ||
946 | gpio-key,wakeup; | ||
947 | }; | ||
948 | }; | ||
949 | |||
950 | panel: panel { | ||
951 | compatible = "auo,b133xtn01"; | ||
952 | |||
953 | backlight = <&backlight>; | ||
954 | ddc-i2c-bus = <&dpaux>; | ||
955 | }; | ||
956 | |||
957 | regulators { | ||
958 | compatible = "simple-bus"; | ||
959 | #address-cells = <1>; | ||
960 | #size-cells = <0>; | ||
961 | |||
962 | vdd_mux: regulator@0 { | ||
963 | compatible = "regulator-fixed"; | ||
964 | reg = <0>; | ||
965 | regulator-name = "+VDD_MUX"; | ||
966 | regulator-min-microvolt = <12000000>; | ||
967 | regulator-max-microvolt = <12000000>; | ||
968 | regulator-always-on; | ||
969 | regulator-boot-on; | ||
970 | }; | ||
971 | |||
972 | vdd_5v0_sys: regulator@1 { | ||
973 | compatible = "regulator-fixed"; | ||
974 | reg = <1>; | ||
975 | regulator-name = "+5V_SYS"; | ||
976 | regulator-min-microvolt = <5000000>; | ||
977 | regulator-max-microvolt = <5000000>; | ||
978 | regulator-always-on; | ||
979 | regulator-boot-on; | ||
980 | vin-supply = <&vdd_mux>; | ||
981 | }; | ||
982 | |||
983 | vdd_3v3_sys: regulator@2 { | ||
984 | compatible = "regulator-fixed"; | ||
985 | reg = <2>; | ||
986 | regulator-name = "+3.3V_SYS"; | ||
987 | regulator-min-microvolt = <3300000>; | ||
988 | regulator-max-microvolt = <3300000>; | ||
989 | regulator-always-on; | ||
990 | regulator-boot-on; | ||
991 | vin-supply = <&vdd_mux>; | ||
992 | }; | ||
993 | |||
994 | vdd_3v3_run: regulator@3 { | ||
995 | compatible = "regulator-fixed"; | ||
996 | reg = <3>; | ||
997 | regulator-name = "+3.3V_RUN"; | ||
998 | regulator-min-microvolt = <3300000>; | ||
999 | regulator-max-microvolt = <3300000>; | ||
1000 | regulator-always-on; | ||
1001 | regulator-boot-on; | ||
1002 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; | ||
1003 | enable-active-high; | ||
1004 | vin-supply = <&vdd_3v3_sys>; | ||
1005 | }; | ||
1006 | |||
1007 | vdd_3v3_hdmi: regulator@4 { | ||
1008 | compatible = "regulator-fixed"; | ||
1009 | reg = <4>; | ||
1010 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | ||
1011 | regulator-min-microvolt = <3300000>; | ||
1012 | regulator-max-microvolt = <3300000>; | ||
1013 | vin-supply = <&vdd_3v3_run>; | ||
1014 | }; | ||
1015 | |||
1016 | vdd_led: regulator@5 { | ||
1017 | compatible = "regulator-fixed"; | ||
1018 | reg = <5>; | ||
1019 | regulator-name = "+VDD_LED"; | ||
1020 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; | ||
1021 | enable-active-high; | ||
1022 | vin-supply = <&vdd_mux>; | ||
1023 | }; | ||
1024 | |||
1025 | vdd_5v0_ts: regulator@6 { | ||
1026 | compatible = "regulator-fixed"; | ||
1027 | reg = <6>; | ||
1028 | regulator-name = "+5V_VDD_TS_SW"; | ||
1029 | regulator-min-microvolt = <5000000>; | ||
1030 | regulator-max-microvolt = <5000000>; | ||
1031 | regulator-boot-on; | ||
1032 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | ||
1033 | enable-active-high; | ||
1034 | vin-supply = <&vdd_5v0_sys>; | ||
1035 | }; | ||
1036 | |||
1037 | vdd_usb1_vbus: regulator@7 { | ||
1038 | compatible = "regulator-fixed"; | ||
1039 | reg = <7>; | ||
1040 | regulator-name = "+5V_USB_HS"; | ||
1041 | regulator-min-microvolt = <5000000>; | ||
1042 | regulator-max-microvolt = <5000000>; | ||
1043 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | ||
1044 | enable-active-high; | ||
1045 | gpio-open-drain; | ||
1046 | vin-supply = <&vdd_5v0_sys>; | ||
1047 | }; | ||
1048 | |||
1049 | vdd_usb3_vbus: regulator@8 { | ||
1050 | compatible = "regulator-fixed"; | ||
1051 | reg = <8>; | ||
1052 | regulator-name = "+5V_USB_SS"; | ||
1053 | regulator-min-microvolt = <5000000>; | ||
1054 | regulator-max-microvolt = <5000000>; | ||
1055 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | ||
1056 | enable-active-high; | ||
1057 | gpio-open-drain; | ||
1058 | vin-supply = <&vdd_5v0_sys>; | ||
1059 | }; | ||
1060 | |||
1061 | vdd_3v3_panel: regulator@9 { | ||
1062 | compatible = "regulator-fixed"; | ||
1063 | reg = <9>; | ||
1064 | regulator-name = "+3.3V_PANEL"; | ||
1065 | regulator-min-microvolt = <3300000>; | ||
1066 | regulator-max-microvolt = <3300000>; | ||
1067 | gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; | ||
1068 | enable-active-high; | ||
1069 | vin-supply = <&vdd_3v3_run>; | ||
1070 | }; | ||
1071 | |||
1072 | vdd_3v3_lp0: regulator@10 { | ||
1073 | compatible = "regulator-fixed"; | ||
1074 | reg = <10>; | ||
1075 | regulator-name = "+3.3V_LP0"; | ||
1076 | regulator-min-microvolt = <3300000>; | ||
1077 | regulator-max-microvolt = <3300000>; | ||
1078 | /* | ||
1079 | * TODO: find a way to wire this up with the USB EHCI | ||
1080 | * controllers so that it can be enabled on demand. | ||
1081 | */ | ||
1082 | regulator-always-on; | ||
1083 | gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; | ||
1084 | enable-active-high; | ||
1085 | vin-supply = <&vdd_3v3_sys>; | ||
1086 | }; | ||
1087 | |||
1088 | vdd_hdmi_pll: regulator@11 { | ||
1089 | compatible = "regulator-fixed"; | ||
1090 | reg = <11>; | ||
1091 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; | ||
1092 | regulator-min-microvolt = <1050000>; | ||
1093 | regulator-max-microvolt = <1050000>; | ||
1094 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | ||
1095 | vin-supply = <&vdd_1v05_run>; | ||
1096 | }; | ||
1097 | |||
1098 | vdd_5v0_hdmi: regulator@12 { | ||
1099 | compatible = "regulator-fixed"; | ||
1100 | reg = <12>; | ||
1101 | regulator-name = "+5V_HDMI_CON"; | ||
1102 | regulator-min-microvolt = <5000000>; | ||
1103 | regulator-max-microvolt = <5000000>; | ||
1104 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | ||
1105 | enable-active-high; | ||
1106 | vin-supply = <&vdd_5v0_sys>; | ||
1107 | }; | ||
1108 | }; | ||
1109 | |||
1110 | sound { | ||
1111 | compatible = "nvidia,tegra-audio-max98090-nyan-big", | ||
1112 | "nvidia,tegra-audio-max98090"; | ||
1113 | nvidia,model = "Acer Chromebook 13"; | ||
1114 | |||
1115 | nvidia,audio-routing = | ||
1116 | "Headphones", "HPR", | ||
1117 | "Headphones", "HPL", | ||
1118 | "Speakers", "SPKR", | ||
1119 | "Speakers", "SPKL", | ||
1120 | "Mic Jack", "MICBIAS", | ||
1121 | "DMICL", "Int Mic", | ||
1122 | "DMICR", "Int Mic", | ||
1123 | "IN34", "Mic Jack"; | ||
1124 | |||
1125 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
1126 | nvidia,audio-codec = <&acodec>; | ||
1127 | |||
1128 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, | ||
1129 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, | ||
1130 | <&tegra_car TEGRA124_CLK_EXTERN1>; | ||
1131 | clock-names = "pll_a", "pll_a_out0", "mclk"; | ||
1132 | |||
1133 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; | ||
1134 | nvidia,mic-det-gpios = | ||
1135 | <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; | ||
1136 | }; | ||
1137 | }; | 1338 | }; |
1138 | |||
1139 | #include "cros-ec-keyboard.dtsi" | ||