1 files changed, 64 insertions, 32 deletions

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index dd34527293e4..382ebd137ee4 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -119,11 +119,19 @@
                 };
 
                 /* dummy clock until actually implemented */
-                pll6: pll6_clk {
+                pll5: pll5_clk {
                         #clock-cells = <0>;
                         compatible = "fixed-clock";
-                        clock-frequency = <600000000>;
-                        clock-output-names = "pll6";
+                        clock-frequency = <0>;
+                        clock-output-names = "pll5";
+                };
+
+                pll6: clk@01c20028 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-pll6-clk";
+                        reg = <0x01c20028 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll6", "pll6x2";
                 };
 
                 cpu: cpu_clk@01c20050 {
@@ -149,19 +157,11 @@
                         clock-output-names = "axi";
                 };
 
-                ahb1_mux: ahb1_mux_clk@01c20054 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
-                        reg = <0x01c20054 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
-                        clock-output-names = "ahb1_mux";
-                };
-
                 ahb1: ahb1_clk@01c20054 {
                         #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-ahb-clk";
+                        compatible = "allwinner,sun6i-a31-ahb1-clk";
                         reg = <0x01c20054 0x4>;
-                        clocks = <&ahb1_mux>;
+                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                         clock-output-names = "ahb1";
                 };
 
@@ -202,7 +202,7 @@
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-apb1-clk";
                         reg = <0x01c20058 0x4>;
-                        clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                         clock-output-names = "apb2";
                 };
 
@@ -218,27 +218,41 @@
                 };
 
                 mmc0_clk: clk@01c20088 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20088 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc0";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc0",
+                                             "mmc0_output",
+                                             "mmc0_sample";
                 };
 
                 mmc1_clk: clk@01c2008c {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c2008c 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc1";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc1",
+                                             "mmc1_output",
+                                             "mmc1_sample";
                 };
 
                 mmc2_clk: clk@01c20090 {
-                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-mmc-clk";
                         reg = <0x01c20090 0x4>;
-                        clocks = <&osc24M>, <&pll6>;
-                        clock-output-names = "mmc2";
+                        clocks = <&osc24M>, <&pll6 0>;
+                        clock-output-names = "mmc2",
+                                             "mmc2_output",
+                                             "mmc2_sample";
+                };
+
+                mbus_clk: clk@01c2015c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun8i-a23-mbus-clk";
+                        reg = <0x01c2015c 0x4>;
+                        clocks = <&osc24M>, <&pll6 1>, <&pll5>;
+                        clock-output-names = "mbus";
                 };
         };
 
@@ -260,8 +274,14 @@
                 mmc0: mmc@01c0f000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c0f000 0x1000>;
-                        clocks = <&ahb1_gates 8>, <&mmc0_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 8>,
+                                 <&mmc0_clk 0>,
+                                 <&mmc0_clk 1>,
+                                 <&mmc0_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 8>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -271,8 +291,14 @@
                 mmc1: mmc@01c10000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c10000 0x1000>;
-                        clocks = <&ahb1_gates 9>, <&mmc1_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 9>,
+                                 <&mmc1_clk 0>,
+                                 <&mmc1_clk 1>,
+                                 <&mmc1_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 9>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -282,8 +308,14 @@
                 mmc2: mmc@01c11000 {
                         compatible = "allwinner,sun5i-a13-mmc";
                         reg = <0x01c11000 0x1000>;
-                        clocks = <&ahb1_gates 10>, <&mmc2_clk>;
-                        clock-names = "ahb", "mmc";
+                        clocks = <&ahb1_gates 10>,
+                                 <&mmc2_clk 0>,
+                                 <&mmc2_clk 1>,
+                                 <&mmc2_clk 2>;
+                        clock-names = "ahb",
+                                      "mmc",
+                                      "output",
+                                      "sample";
                         resets = <&ahb1_rst 10>;
                         reset-names = "ahb";
                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;