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Diffstat (limited to 'arch/arm/boot/dts/ste-hrefprev60.dtsi')
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dtsi73
1 files changed, 69 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi
index b2cd7bc2752f..b0f5def8e2a8 100644
--- a/arch/arm/boot/dts/ste-hrefprev60.dtsi
+++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi
@@ -28,18 +28,20 @@
28 reg = <0x33>; 28 reg = <0x33>;
29 }; 29 };
30 30
31 tc3589x@42 { 31 tc35892@42 {
32 compatible = "tc3589x"; 32 compatible = "toshiba,tc35892";
33 reg = <0x42>; 33 reg = <0x42>;
34 interrupt-parent = <&gpio6>; 34 interrupt-parent = <&gpio6>;
35 interrupts = <25 IRQ_TYPE_EDGE_RISING>; 35 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
36 pinctrl-names = "default";
37 pinctrl-0 = <&tc35892_hrefprev60_mode>;
36 38
37 interrupt-controller; 39 interrupt-controller;
38 #interrupt-cells = <2>; 40 #interrupt-cells = <1>;
39 41
40 tc3589x_gpio: tc3589x_gpio { 42 tc3589x_gpio: tc3589x_gpio {
41 compatible = "tc3589x-gpio"; 43 compatible = "tc3589x-gpio";
42 interrupts = <0 IRQ_TYPE_EDGE_RISING>; 44 interrupts = <0>;
43 45
44 interrupt-controller; 46 interrupt-controller;
45 #interrupt-cells = <2>; 47 #interrupt-cells = <2>;
@@ -49,11 +51,74 @@
49 }; 51 };
50 }; 52 };
51 53
54 ssp@80002000 {
55 /*
56 * On the first generation boards, this SSP/SPI port was connected
57 * to the AB8500.
58 */
59 pinctrl-names = "default";
60 pinctrl-0 = <&ssp0_hrefprev60_mode>;
61 };
62
52 vmmci: regulator-gpio { 63 vmmci: regulator-gpio {
53 gpios = <&tc3589x_gpio 18 0x4>; 64 gpios = <&tc3589x_gpio 18 0x4>;
54 enable-gpio = <&tc3589x_gpio 17 0x4>; 65 enable-gpio = <&tc3589x_gpio 17 0x4>;
55 66
56 status = "okay"; 67 status = "okay";
57 }; 68 };
69
70 pinctrl {
71 /* Set this up using hogs */
72 pinctrl-names = "default";
73 pinctrl-0 = <&ipgpio_hrefprev60_mode>;
74
75 ssp0 {
76 ssp0_hrefprev60_mode: ssp0_hrefprev60_default {
77 hrefprev60_mux {
78 ste,function = "ssp0";
79 ste,pins = "ssp0_a_1";
80 };
81 hrefprev60_cfg1 {
82 ste,pins = "GPIO145_C13"; /* RXD */
83 ste,config = <&in_pd>;
84 };
85
86 };
87 };
88 sdi0 {
89 /* This additional pin needed on early MOP500 and HREFs previous to v60 */
90 sdi0_default_mode: sdi0_default {
91 hrefprev60_mux {
92 ste,function = "mc0";
93 ste,pins = "mc0dat31dir_a_1";
94 };
95 hrefprev60_cfg1 {
96 ste,pins = "GPIO21_AB3"; /* DAT31DIR */
97 ste,config = <&out_hi>;
98 };
99
100 };
101 };
102 tc35892 {
103 tc35892_hrefprev60_mode: tc35892_hrefprev60 {
104 hrefprev60_cfg {
105 ste,pins = "GPIO217_AH12";
106 ste,config = <&gpio_in_pu>;
107 };
108 };
109 };
110 ipgpio {
111 ipgpio_hrefprev60_mode: ipgpio_hrefprev60 {
112 hrefprev60_mux {
113 ste,function = "ipgpio";
114 ste,pins = "ipgpio0_c_1", "ipgpio1_c_1";
115 };
116 hrefprev60_cfg1 {
117 ste,pins = "GPIO6_AF6", "GPIO7_AG5";
118 ste,config = <&in_pu>;
119 };
120 };
121 };
122 };
58 }; 123 };
59}; 124};