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-rw-r--r--arch/arm/boot/dts/socfpga.dtsi157
1 files changed, 157 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 7e8769bd5977..16a6e13e08b4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -81,6 +81,163 @@
81 }; 81 };
82 }; 82 };
83 83
84 clkmgr@ffd04000 {
85 compatible = "altr,clk-mgr";
86 reg = <0xffd04000 0x1000>;
87
88 clocks {
89 #address-cells = <1>;
90 #size-cells = <0>;
91
92 osc: osc1 {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 };
96
97 main_pll: main_pll {
98 #address-cells = <1>;
99 #size-cells = <0>;
100 #clock-cells = <0>;
101 compatible = "altr,socfpga-pll-clock";
102 clocks = <&osc>;
103 reg = <0x40>;
104
105 mpuclk: mpuclk {
106 #clock-cells = <0>;
107 compatible = "altr,socfpga-perip-clk";
108 clocks = <&main_pll>;
109 fixed-divider = <2>;
110 reg = <0x48>;
111 };
112
113 mainclk: mainclk {
114 #clock-cells = <0>;
115 compatible = "altr,socfpga-perip-clk";
116 clocks = <&main_pll>;
117 fixed-divider = <4>;
118 reg = <0x4C>;
119 };
120
121 dbg_base_clk: dbg_base_clk {
122 #clock-cells = <0>;
123 compatible = "altr,socfpga-perip-clk";
124 clocks = <&main_pll>;
125 fixed-divider = <4>;
126 reg = <0x50>;
127 };
128
129 main_qspi_clk: main_qspi_clk {
130 #clock-cells = <0>;
131 compatible = "altr,socfpga-perip-clk";
132 clocks = <&main_pll>;
133 reg = <0x54>;
134 };
135
136 main_nand_sdmmc_clk: main_nand_sdmmc_clk {
137 #clock-cells = <0>;
138 compatible = "altr,socfpga-perip-clk";
139 clocks = <&main_pll>;
140 reg = <0x58>;
141 };
142
143 cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
144 #clock-cells = <0>;
145 compatible = "altr,socfpga-perip-clk";
146 clocks = <&main_pll>;
147 reg = <0x5C>;
148 };
149 };
150
151 periph_pll: periph_pll {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 #clock-cells = <0>;
155 compatible = "altr,socfpga-pll-clock";
156 clocks = <&osc>;
157 reg = <0x80>;
158
159 emac0_clk: emac0_clk {
160 #clock-cells = <0>;
161 compatible = "altr,socfpga-perip-clk";
162 clocks = <&periph_pll>;
163 reg = <0x88>;
164 };
165
166 emac1_clk: emac1_clk {
167 #clock-cells = <0>;
168 compatible = "altr,socfpga-perip-clk";
169 clocks = <&periph_pll>;
170 reg = <0x8C>;
171 };
172
173 per_qspi_clk: per_qsi_clk {
174 #clock-cells = <0>;
175 compatible = "altr,socfpga-perip-clk";
176 clocks = <&periph_pll>;
177 reg = <0x90>;
178 };
179
180 per_nand_mmc_clk: per_nand_mmc_clk {
181 #clock-cells = <0>;
182 compatible = "altr,socfpga-perip-clk";
183 clocks = <&periph_pll>;
184 reg = <0x94>;
185 };
186
187 per_base_clk: per_base_clk {
188 #clock-cells = <0>;
189 compatible = "altr,socfpga-perip-clk";
190 clocks = <&periph_pll>;
191 reg = <0x98>;
192 };
193
194 s2f_usr1_clk: s2f_usr1_clk {
195 #clock-cells = <0>;
196 compatible = "altr,socfpga-perip-clk";
197 clocks = <&periph_pll>;
198 reg = <0x9C>;
199 };
200 };
201
202 sdram_pll: sdram_pll {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 #clock-cells = <0>;
206 compatible = "altr,socfpga-pll-clock";
207 clocks = <&osc>;
208 reg = <0xC0>;
209
210 ddr_dqs_clk: ddr_dqs_clk {
211 #clock-cells = <0>;
212 compatible = "altr,socfpga-perip-clk";
213 clocks = <&sdram_pll>;
214 reg = <0xC8>;
215 };
216
217 ddr_2x_dqs_clk: ddr_2x_dqs_clk {
218 #clock-cells = <0>;
219 compatible = "altr,socfpga-perip-clk";
220 clocks = <&sdram_pll>;
221 reg = <0xCC>;
222 };
223
224 ddr_dq_clk: ddr_dq_clk {
225 #clock-cells = <0>;
226 compatible = "altr,socfpga-perip-clk";
227 clocks = <&sdram_pll>;
228 reg = <0xD0>;
229 };
230
231 s2f_usr2_clk: s2f_usr2_clk {
232 #clock-cells = <0>;
233 compatible = "altr,socfpga-perip-clk";
234 clocks = <&sdram_pll>;
235 reg = <0xD4>;
236 };
237 };
238 };
239 };
240
84 gmac0: stmmac@ff700000 { 241 gmac0: stmmac@ff700000 {
85 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 242 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
86 reg = <0xff700000 0x2000>; 243 reg = <0xff700000 0x2000>;