diff options
Diffstat (limited to 'arch/arm/boot/dts/socfpga.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 217 |
1 files changed, 215 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 16a6e13e08b4..bee62a2cf6d6 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | aliases { | 24 | aliases { |
| 25 | ethernet0 = &gmac0; | 25 | ethernet0 = &gmac0; |
| 26 | ethernet1 = &gmac1; | ||
| 26 | serial0 = &uart0; | 27 | serial0 = &uart0; |
| 27 | serial1 = &uart1; | 28 | serial1 = &uart1; |
| 28 | timer0 = &timer0; | 29 | timer0 = &timer0; |
| @@ -94,6 +95,12 @@ | |||
| 94 | compatible = "fixed-clock"; | 95 | compatible = "fixed-clock"; |
| 95 | }; | 96 | }; |
| 96 | 97 | ||
| 98 | f2s_periph_ref_clk: f2s_periph_ref_clk { | ||
| 99 | #clock-cells = <0>; | ||
| 100 | compatible = "fixed-clock"; | ||
| 101 | clock-frequency = <10000000>; | ||
| 102 | }; | ||
| 103 | |||
| 97 | main_pll: main_pll { | 104 | main_pll: main_pll { |
| 98 | #address-cells = <1>; | 105 | #address-cells = <1>; |
| 99 | #size-cells = <0>; | 106 | #size-cells = <0>; |
| @@ -235,16 +242,222 @@ | |||
| 235 | reg = <0xD4>; | 242 | reg = <0xD4>; |
| 236 | }; | 243 | }; |
| 237 | }; | 244 | }; |
| 245 | |||
| 246 | mpu_periph_clk: mpu_periph_clk { | ||
| 247 | #clock-cells = <0>; | ||
| 248 | compatible = "altr,socfpga-gate-clk"; | ||
| 249 | clocks = <&mpuclk>; | ||
| 250 | fixed-divider = <4>; | ||
| 251 | }; | ||
| 252 | |||
| 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { | ||
| 254 | #clock-cells = <0>; | ||
| 255 | compatible = "altr,socfpga-gate-clk"; | ||
| 256 | clocks = <&mpuclk>; | ||
| 257 | fixed-divider = <2>; | ||
| 258 | }; | ||
| 259 | |||
| 260 | l4_main_clk: l4_main_clk { | ||
| 261 | #clock-cells = <0>; | ||
| 262 | compatible = "altr,socfpga-gate-clk"; | ||
| 263 | clocks = <&mainclk>; | ||
| 264 | clk-gate = <0x60 0>; | ||
| 265 | }; | ||
| 266 | |||
| 267 | l3_main_clk: l3_main_clk { | ||
| 268 | #clock-cells = <0>; | ||
| 269 | compatible = "altr,socfpga-gate-clk"; | ||
| 270 | clocks = <&mainclk>; | ||
| 271 | }; | ||
| 272 | |||
| 273 | l3_mp_clk: l3_mp_clk { | ||
| 274 | #clock-cells = <0>; | ||
| 275 | compatible = "altr,socfpga-gate-clk"; | ||
| 276 | clocks = <&mainclk>; | ||
| 277 | div-reg = <0x64 0 2>; | ||
| 278 | clk-gate = <0x60 1>; | ||
| 279 | }; | ||
| 280 | |||
| 281 | l3_sp_clk: l3_sp_clk { | ||
| 282 | #clock-cells = <0>; | ||
| 283 | compatible = "altr,socfpga-gate-clk"; | ||
| 284 | clocks = <&mainclk>; | ||
| 285 | div-reg = <0x64 2 2>; | ||
| 286 | }; | ||
| 287 | |||
| 288 | l4_mp_clk: l4_mp_clk { | ||
| 289 | #clock-cells = <0>; | ||
| 290 | compatible = "altr,socfpga-gate-clk"; | ||
| 291 | clocks = <&mainclk>, <&per_base_clk>; | ||
| 292 | div-reg = <0x64 4 3>; | ||
| 293 | clk-gate = <0x60 2>; | ||
| 294 | }; | ||
| 295 | |||
| 296 | l4_sp_clk: l4_sp_clk { | ||
| 297 | #clock-cells = <0>; | ||
| 298 | compatible = "altr,socfpga-gate-clk"; | ||
| 299 | clocks = <&mainclk>, <&per_base_clk>; | ||
| 300 | div-reg = <0x64 7 3>; | ||
| 301 | clk-gate = <0x60 3>; | ||
| 302 | }; | ||
| 303 | |||
| 304 | dbg_at_clk: dbg_at_clk { | ||
| 305 | #clock-cells = <0>; | ||
| 306 | compatible = "altr,socfpga-gate-clk"; | ||
| 307 | clocks = <&dbg_base_clk>; | ||
| 308 | div-reg = <0x68 0 2>; | ||
| 309 | clk-gate = <0x60 4>; | ||
| 310 | }; | ||
| 311 | |||
| 312 | dbg_clk: dbg_clk { | ||
| 313 | #clock-cells = <0>; | ||
| 314 | compatible = "altr,socfpga-gate-clk"; | ||
| 315 | clocks = <&dbg_base_clk>; | ||
| 316 | div-reg = <0x68 2 2>; | ||
| 317 | clk-gate = <0x60 5>; | ||
| 318 | }; | ||
| 319 | |||
| 320 | dbg_trace_clk: dbg_trace_clk { | ||
| 321 | #clock-cells = <0>; | ||
| 322 | compatible = "altr,socfpga-gate-clk"; | ||
| 323 | clocks = <&dbg_base_clk>; | ||
| 324 | div-reg = <0x6C 0 3>; | ||
| 325 | clk-gate = <0x60 6>; | ||
| 326 | }; | ||
| 327 | |||
| 328 | dbg_timer_clk: dbg_timer_clk { | ||
| 329 | #clock-cells = <0>; | ||
| 330 | compatible = "altr,socfpga-gate-clk"; | ||
| 331 | clocks = <&dbg_base_clk>; | ||
| 332 | clk-gate = <0x60 7>; | ||
| 333 | }; | ||
| 334 | |||
| 335 | cfg_clk: cfg_clk { | ||
| 336 | #clock-cells = <0>; | ||
| 337 | compatible = "altr,socfpga-gate-clk"; | ||
| 338 | clocks = <&cfg_s2f_usr0_clk>; | ||
| 339 | clk-gate = <0x60 8>; | ||
| 340 | }; | ||
| 341 | |||
| 342 | s2f_user0_clk: s2f_user0_clk { | ||
| 343 | #clock-cells = <0>; | ||
| 344 | compatible = "altr,socfpga-gate-clk"; | ||
| 345 | clocks = <&cfg_s2f_usr0_clk>; | ||
| 346 | clk-gate = <0x60 9>; | ||
| 347 | }; | ||
| 348 | |||
| 349 | emac_0_clk: emac_0_clk { | ||
| 350 | #clock-cells = <0>; | ||
| 351 | compatible = "altr,socfpga-gate-clk"; | ||
| 352 | clocks = <&emac0_clk>; | ||
| 353 | clk-gate = <0xa0 0>; | ||
| 354 | }; | ||
| 355 | |||
| 356 | emac_1_clk: emac_1_clk { | ||
| 357 | #clock-cells = <0>; | ||
| 358 | compatible = "altr,socfpga-gate-clk"; | ||
| 359 | clocks = <&emac1_clk>; | ||
| 360 | clk-gate = <0xa0 1>; | ||
| 361 | }; | ||
| 362 | |||
| 363 | usb_mp_clk: usb_mp_clk { | ||
| 364 | #clock-cells = <0>; | ||
| 365 | compatible = "altr,socfpga-gate-clk"; | ||
| 366 | clocks = <&per_base_clk>; | ||
| 367 | clk-gate = <0xa0 2>; | ||
| 368 | div-reg = <0xa4 0 3>; | ||
| 369 | }; | ||
| 370 | |||
| 371 | spi_m_clk: spi_m_clk { | ||
| 372 | #clock-cells = <0>; | ||
| 373 | compatible = "altr,socfpga-gate-clk"; | ||
| 374 | clocks = <&per_base_clk>; | ||
| 375 | clk-gate = <0xa0 3>; | ||
| 376 | div-reg = <0xa4 3 3>; | ||
| 377 | }; | ||
| 378 | |||
| 379 | can0_clk: can0_clk { | ||
| 380 | #clock-cells = <0>; | ||
| 381 | compatible = "altr,socfpga-gate-clk"; | ||
| 382 | clocks = <&per_base_clk>; | ||
| 383 | clk-gate = <0xa0 4>; | ||
| 384 | div-reg = <0xa4 6 3>; | ||
| 385 | }; | ||
| 386 | |||
| 387 | can1_clk: can1_clk { | ||
| 388 | #clock-cells = <0>; | ||
| 389 | compatible = "altr,socfpga-gate-clk"; | ||
| 390 | clocks = <&per_base_clk>; | ||
| 391 | clk-gate = <0xa0 5>; | ||
| 392 | div-reg = <0xa4 9 3>; | ||
| 393 | }; | ||
| 394 | |||
| 395 | gpio_db_clk: gpio_db_clk { | ||
| 396 | #clock-cells = <0>; | ||
| 397 | compatible = "altr,socfpga-gate-clk"; | ||
| 398 | clocks = <&per_base_clk>; | ||
| 399 | clk-gate = <0xa0 6>; | ||
| 400 | div-reg = <0xa8 0 24>; | ||
| 401 | }; | ||
| 402 | |||
| 403 | s2f_user1_clk: s2f_user1_clk { | ||
| 404 | #clock-cells = <0>; | ||
| 405 | compatible = "altr,socfpga-gate-clk"; | ||
| 406 | clocks = <&s2f_usr1_clk>; | ||
| 407 | clk-gate = <0xa0 7>; | ||
| 408 | }; | ||
| 409 | |||
| 410 | sdmmc_clk: sdmmc_clk { | ||
| 411 | #clock-cells = <0>; | ||
| 412 | compatible = "altr,socfpga-gate-clk"; | ||
| 413 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 414 | clk-gate = <0xa0 8>; | ||
| 415 | }; | ||
| 416 | |||
| 417 | nand_x_clk: nand_x_clk { | ||
| 418 | #clock-cells = <0>; | ||
| 419 | compatible = "altr,socfpga-gate-clk"; | ||
| 420 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 421 | clk-gate = <0xa0 9>; | ||
| 422 | }; | ||
| 423 | |||
| 424 | nand_clk: nand_clk { | ||
| 425 | #clock-cells = <0>; | ||
| 426 | compatible = "altr,socfpga-gate-clk"; | ||
| 427 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | ||
| 428 | clk-gate = <0xa0 10>; | ||
| 429 | fixed-divider = <4>; | ||
| 430 | }; | ||
| 431 | |||
| 432 | qspi_clk: qspi_clk { | ||
| 433 | #clock-cells = <0>; | ||
| 434 | compatible = "altr,socfpga-gate-clk"; | ||
| 435 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | ||
| 436 | clk-gate = <0xa0 11>; | ||
| 437 | }; | ||
| 238 | }; | 438 | }; |
| 239 | }; | 439 | }; |
| 240 | 440 | ||
| 241 | gmac0: stmmac@ff700000 { | 441 | gmac0: ethernet@ff700000 { |
| 242 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | 442 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
| 243 | reg = <0xff700000 0x2000>; | 443 | reg = <0xff700000 0x2000>; |
| 244 | interrupts = <0 115 4>; | 444 | interrupts = <0 115 4>; |
| 245 | interrupt-names = "macirq"; | 445 | interrupt-names = "macirq"; |
| 246 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | 446 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ |
| 247 | phy-mode = "gmii"; | 447 | clocks = <&emac0_clk>; |
| 448 | clock-names = "stmmaceth"; | ||
| 449 | status = "disabled"; | ||
| 450 | }; | ||
| 451 | |||
| 452 | gmac1: ethernet@ff702000 { | ||
| 453 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | ||
| 454 | reg = <0xff702000 0x2000>; | ||
| 455 | interrupts = <0 120 4>; | ||
| 456 | interrupt-names = "macirq"; | ||
| 457 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | ||
| 458 | clocks = <&emac1_clk>; | ||
| 459 | clock-names = "stmmaceth"; | ||
| 460 | status = "disabled"; | ||
| 248 | }; | 461 | }; |
| 249 | 462 | ||
| 250 | L2: l2-cache@fffef000 { | 463 | L2: l2-cache@fffef000 { |