1 files changed, 98 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 874e66dbb93b..fd19f00784bd 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3288-cru.h>
+#include <dt-bindings/thermal/thermal.h>
 #include "skeleton.dtsi"
 
 / {
@@ -46,26 +47,50 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "rockchip,rk3066-smp";
+                rockchip,pmu = <&pmu>;
 
-                cpu@500 {
+                cpu0: cpu@500 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x500>;
+                        resets = <&cru SRST_CORE0>;
+                        operating-points = <
+                                /* KHz    uV */
+                                1608000 1350000
+                                1512000 1300000
+                                1416000 1200000
+                                1200000 1100000
+                                1008000 1050000
+                                 816000 1000000
+                                 696000  950000
+                                 600000  900000
+                                 408000  900000
+                                 312000  900000
+                                 216000  900000
+                                 126000  900000
+                        >;
+                        #cooling-cells = <2>; /* min followed by max */
+                        clock-latency = <40000>;
+                        clocks = <&cru ARMCLK>;
                 };
                 cpu@501 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x501>;
+                        resets = <&cru SRST_CORE1>;
                 };
                 cpu@502 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x502>;
+                        resets = <&cru SRST_CORE2>;
                 };
                 cpu@503 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a12";
                         reg = <0x503>;
+                        resets = <&cru SRST_CORE3>;
                 };
         };
 
@@ -116,6 +141,7 @@
 
         timer {
                 compatible = "arm,armv7-timer";
+                arm,cpu-registers-not-fw-configured;
                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
@@ -177,6 +203,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 11>, <&dmac_peri 12>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
@@ -190,6 +218,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 13>, <&dmac_peri 14>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
@@ -203,6 +233,8 @@
                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
                 clock-names = "spiclk", "apb_pclk";
+                dmas = <&dmac_peri 15>, <&dmac_peri 16>;
+                dma-names = "tx", "rx";
                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
@@ -329,6 +361,25 @@
                 status = "disabled";
         };
 
+        thermal-zones {
+                #include "rk3288-thermal.dtsi"
+        };
+
+        tsadc: tsadc@ff280000 {
+                compatible = "rockchip,rk3288-tsadc";
+                reg = <0xff280000 0x100>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+                clock-names = "tsadc", "apb_pclk";
+                resets = <&cru SRST_TSADC>;
+                reset-names = "tsadc-apb";
+                pinctrl-names = "default";
+                pinctrl-0 = <&otp_out>;
+                #thermal-sensor-cells = <1>;
+                rockchip,hw-tshut-temp = <95000>;
+                status = "disabled";
+        };
+
         usb_host0_ehci: usb@ff500000 {
                 compatible = "generic-ehci";
                 reg = <0xff500000 0x100>;
@@ -439,6 +490,18 @@
                 status = "disabled";
         };
 
+        bus_intmem@ff700000 {
+                compatible = "mmio-sram";
+                reg = <0xff700000 0x18000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xff700000 0x18000>;
+                smp-sram@0 {
+                        compatible = "rockchip,rk3066-smp-sram";
+                        reg = <0x00 0x10>;
+                };
+        };
+
         pmu: power-management@ff730000 {
                 compatible = "rockchip,rk3288-pmu", "syscon";
                 reg = <0xff730000 0x100>;
@@ -455,6 +518,16 @@
                 rockchip,grf = <&grf>;
                 #clock-cells = <1>;
                 #reset-cells = <1>;
+                assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+                                  <&cru PLL_NPLL>, <&cru ACLK_CPU>,
+                                  <&cru HCLK_CPU>, <&cru PCLK_CPU>,
+                                  <&cru ACLK_PERI>, <&cru HCLK_PERI>,
+                                  <&cru PCLK_PERI>;
+                assigned-clock-rates = <594000000>, <400000000>,
+                                       <500000000>, <300000000>,
+                                       <150000000>, <75000000>,
+                                       <300000000>, <150000000>,
+                                       <75000000>;
         };
 
         grf: syscon@ff770000 {
@@ -484,6 +557,24 @@
                 status = "disabled";
         };
 
+        vopb_mmu: iommu@ff930300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff930300 0x100>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopb_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
+        vopl_mmu: iommu@ff940300 {
+                compatible = "rockchip,iommu";
+                reg = <0xff940300 0x100>;
+                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "vopl_mmu";
+                #iommu-cells = <0>;
+                status = "disabled";
+        };
+
         gic: interrupt-controller@ffc01000 {
                 compatible = "arm,gic-400";
                 interrupt-controller;
@@ -948,6 +1039,12 @@
                         };
                 };
 
+                tsadc {
+                        otp_out: otp-out {
+                                rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
                 pwm0 {
                         pwm0_pin: pwm0-pin {
                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;