aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/r8a7791.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1c58ce0a488a..98c1b8bef61f 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * Device Tree Source for the r8a7791 SoC 2 * Device Tree Source for the r8a7791 SoC
3 * 3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation 4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc. 6 * Copyright (C) 2014 Cogent Embedded Inc.
7 * 7 *
@@ -977,17 +977,18 @@
977 mstp1_clks: mstp1_clks@e6150134 { 977 mstp1_clks: mstp1_clks@e6150134 {
978 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 978 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
979 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 979 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
980 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 980 clocks = <&m2_clk>, <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
981 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; 981 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
982 #clock-cells = <1>; 982 #clock-cells = <1>;
983 renesas,clock-indices = < 983 renesas,clock-indices = <
984 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 984 R8A7791_CLK_JPU R8A7791_CLK_TMU1 R8A7791_CLK_3DG
985 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
985 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 986 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
986 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S 987 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
987 >; 988 >;
988 clock-output-names = 989 clock-output-names =
989 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 990 "jpu", "tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0",
990 "vsp1-du0", "vsp1-sy"; 991 "vsp1-du1", "vsp1-du0", "vsp1-sy";
991 }; 992 };
992 mstp2_clks: mstp2_clks@e6150138 { 993 mstp2_clks: mstp2_clks@e6150138 {
993 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 994 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";