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Diffstat (limited to 'arch/arm/boot/dts/r8a7779.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi220
1 files changed, 220 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index b517c8e6b420..94e2fc836492 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -11,6 +11,7 @@
11 11
12/include/ "skeleton.dtsi" 12/include/ "skeleton.dtsi"
13 13
14#include <dt-bindings/clock/r8a7779-clock.h>
14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
15 16
16/ { 17/ {
@@ -25,21 +26,25 @@
25 device_type = "cpu"; 26 device_type = "cpu";
26 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
27 reg = <0>; 28 reg = <0>;
29 clock-frequency = <1000000000>;
28 }; 30 };
29 cpu@1 { 31 cpu@1 {
30 device_type = "cpu"; 32 device_type = "cpu";
31 compatible = "arm,cortex-a9"; 33 compatible = "arm,cortex-a9";
32 reg = <1>; 34 reg = <1>;
35 clock-frequency = <1000000000>;
33 }; 36 };
34 cpu@2 { 37 cpu@2 {
35 device_type = "cpu"; 38 device_type = "cpu";
36 compatible = "arm,cortex-a9"; 39 compatible = "arm,cortex-a9";
37 reg = <2>; 40 reg = <2>;
41 clock-frequency = <1000000000>;
38 }; 42 };
39 cpu@3 { 43 cpu@3 {
40 device_type = "cpu"; 44 device_type = "cpu";
41 compatible = "arm,cortex-a9"; 45 compatible = "arm,cortex-a9";
42 reg = <3>; 46 reg = <3>;
47 clock-frequency = <1000000000>;
43 }; 48 };
44 }; 49 };
45 50
@@ -157,6 +162,7 @@
157 compatible = "renesas,i2c-r8a7779"; 162 compatible = "renesas,i2c-r8a7779";
158 reg = <0xffc70000 0x1000>; 163 reg = <0xffc70000 0x1000>;
159 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 164 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
160 status = "disabled"; 166 status = "disabled";
161 }; 167 };
162 168
@@ -166,6 +172,7 @@
166 compatible = "renesas,i2c-r8a7779"; 172 compatible = "renesas,i2c-r8a7779";
167 reg = <0xffc71000 0x1000>; 173 reg = <0xffc71000 0x1000>;
168 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 174 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
175 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
169 status = "disabled"; 176 status = "disabled";
170 }; 177 };
171 178
@@ -175,6 +182,7 @@
175 compatible = "renesas,i2c-r8a7779"; 182 compatible = "renesas,i2c-r8a7779";
176 reg = <0xffc72000 0x1000>; 183 reg = <0xffc72000 0x1000>;
177 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 184 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
178 status = "disabled"; 186 status = "disabled";
179 }; 187 };
180 188
@@ -184,6 +192,67 @@
184 compatible = "renesas,i2c-r8a7779"; 192 compatible = "renesas,i2c-r8a7779";
185 reg = <0xffc73000 0x1000>; 193 reg = <0xffc73000 0x1000>;
186 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 194 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
196 status = "disabled";
197 };
198
199 scif0: serial@ffe40000 {
200 compatible = "renesas,scif-r8a7779", "renesas,scif";
201 reg = <0xffe40000 0x100>;
202 interrupt-parent = <&gic>;
203 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&cpg_clocks R8A7779_CLK_P>;
205 clock-names = "sci_ick";
206 status = "disabled";
207 };
208
209 scif1: serial@ffe41000 {
210 compatible = "renesas,scif-r8a7779", "renesas,scif";
211 reg = <0xffe41000 0x100>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cpg_clocks R8A7779_CLK_P>;
215 clock-names = "sci_ick";
216 status = "disabled";
217 };
218
219 scif2: serial@ffe42000 {
220 compatible = "renesas,scif-r8a7779", "renesas,scif";
221 reg = <0xffe42000 0x100>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&cpg_clocks R8A7779_CLK_P>;
225 clock-names = "sci_ick";
226 status = "disabled";
227 };
228
229 scif3: serial@ffe43000 {
230 compatible = "renesas,scif-r8a7779", "renesas,scif";
231 reg = <0xffe43000 0x100>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpg_clocks R8A7779_CLK_P>;
235 clock-names = "sci_ick";
236 status = "disabled";
237 };
238
239 scif4: serial@ffe44000 {
240 compatible = "renesas,scif-r8a7779", "renesas,scif";
241 reg = <0xffe44000 0x100>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpg_clocks R8A7779_CLK_P>;
245 clock-names = "sci_ick";
246 status = "disabled";
247 };
248
249 scif5: serial@ffe45000 {
250 compatible = "renesas,scif-r8a7779", "renesas,scif";
251 reg = <0xffe45000 0x100>;
252 interrupt-parent = <&gic>;
253 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&cpg_clocks R8A7779_CLK_P>;
255 clock-names = "sci_ick";
187 status = "disabled"; 256 status = "disabled";
188 }; 257 };
189 258
@@ -201,12 +270,14 @@
201 compatible = "renesas,rcar-sata"; 270 compatible = "renesas,rcar-sata";
202 reg = <0xfc600000 0x2000>; 271 reg = <0xfc600000 0x2000>;
203 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 272 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
204 }; 274 };
205 275
206 sdhi0: sd@ffe4c000 { 276 sdhi0: sd@ffe4c000 {
207 compatible = "renesas,sdhi-r8a7779"; 277 compatible = "renesas,sdhi-r8a7779";
208 reg = <0xffe4c000 0x100>; 278 reg = <0xffe4c000 0x100>;
209 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 279 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
210 cap-sd-highspeed; 281 cap-sd-highspeed;
211 cap-sdio-irq; 282 cap-sdio-irq;
212 status = "disabled"; 283 status = "disabled";
@@ -216,6 +287,7 @@
216 compatible = "renesas,sdhi-r8a7779"; 287 compatible = "renesas,sdhi-r8a7779";
217 reg = <0xffe4d000 0x100>; 288 reg = <0xffe4d000 0x100>;
218 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
219 cap-sd-highspeed; 291 cap-sd-highspeed;
220 cap-sdio-irq; 292 cap-sdio-irq;
221 status = "disabled"; 293 status = "disabled";
@@ -225,6 +297,7 @@
225 compatible = "renesas,sdhi-r8a7779"; 297 compatible = "renesas,sdhi-r8a7779";
226 reg = <0xffe4e000 0x100>; 298 reg = <0xffe4e000 0x100>;
227 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 299 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
228 cap-sd-highspeed; 301 cap-sd-highspeed;
229 cap-sdio-irq; 302 cap-sdio-irq;
230 status = "disabled"; 303 status = "disabled";
@@ -234,6 +307,7 @@
234 compatible = "renesas,sdhi-r8a7779"; 307 compatible = "renesas,sdhi-r8a7779";
235 reg = <0xffe4f000 0x100>; 308 reg = <0xffe4f000 0x100>;
236 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 309 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
237 cap-sd-highspeed; 311 cap-sd-highspeed;
238 cap-sdio-irq; 312 cap-sdio-irq;
239 status = "disabled"; 313 status = "disabled";
@@ -245,6 +319,7 @@
245 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 319 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>; 320 #address-cells = <1>;
247 #size-cells = <0>; 321 #size-cells = <0>;
322 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
248 status = "disabled"; 323 status = "disabled";
249 }; 324 };
250 325
@@ -254,6 +329,7 @@
254 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 329 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>; 330 #address-cells = <1>;
256 #size-cells = <0>; 331 #size-cells = <0>;
332 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
257 status = "disabled"; 333 status = "disabled";
258 }; 334 };
259 335
@@ -263,6 +339,150 @@
263 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 339 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
264 #address-cells = <1>; 340 #address-cells = <1>;
265 #size-cells = <0>; 341 #size-cells = <0>;
342 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
266 status = "disabled"; 343 status = "disabled";
267 }; 344 };
345
346 clocks {
347 #address-cells = <1>;
348 #size-cells = <1>;
349 ranges;
350
351 /* External root clock */
352 extal_clk: extal_clk {
353 compatible = "fixed-clock";
354 #clock-cells = <0>;
355 /* This value must be overriden by the board. */
356 clock-frequency = <0>;
357 clock-output-names = "extal";
358 };
359
360 /* Special CPG clocks */
361 cpg_clocks: clocks@ffc80000 {
362 compatible = "renesas,r8a7779-cpg-clocks";
363 reg = <0xffc80000 0x30>;
364 clocks = <&extal_clk>;
365 #clock-cells = <1>;
366 clock-output-names = "plla", "z", "zs", "s",
367 "s1", "p", "b", "out";
368 };
369
370 /* Fixed factor clocks */
371 i_clk: i_clk {
372 compatible = "fixed-factor-clock";
373 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
374 #clock-cells = <0>;
375 clock-div = <2>;
376 clock-mult = <1>;
377 clock-output-names = "i";
378 };
379 s3_clk: s3_clk {
380 compatible = "fixed-factor-clock";
381 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
382 #clock-cells = <0>;
383 clock-div = <8>;
384 clock-mult = <1>;
385 clock-output-names = "s3";
386 };
387 s4_clk: s4_clk {
388 compatible = "fixed-factor-clock";
389 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
390 #clock-cells = <0>;
391 clock-div = <16>;
392 clock-mult = <1>;
393 clock-output-names = "s4";
394 };
395 g_clk: g_clk {
396 compatible = "fixed-factor-clock";
397 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
398 #clock-cells = <0>;
399 clock-div = <24>;
400 clock-mult = <1>;
401 clock-output-names = "g";
402 };
403
404 /* Gate clocks */
405 mstp0_clks: clocks@ffc80030 {
406 compatible = "renesas,r8a7779-mstp-clocks",
407 "renesas,cpg-mstp-clocks";
408 reg = <0xffc80030 4>;
409 clocks = <&cpg_clocks R8A7779_CLK_S>,
410 <&cpg_clocks R8A7779_CLK_P>,
411 <&cpg_clocks R8A7779_CLK_P>,
412 <&cpg_clocks R8A7779_CLK_P>,
413 <&cpg_clocks R8A7779_CLK_S>,
414 <&cpg_clocks R8A7779_CLK_S>,
415 <&cpg_clocks R8A7779_CLK_S1>,
416 <&cpg_clocks R8A7779_CLK_S1>,
417 <&cpg_clocks R8A7779_CLK_S1>,
418 <&cpg_clocks R8A7779_CLK_S1>,
419 <&cpg_clocks R8A7779_CLK_S1>,
420 <&cpg_clocks R8A7779_CLK_S1>,
421 <&cpg_clocks R8A7779_CLK_P>,
422 <&cpg_clocks R8A7779_CLK_P>,
423 <&cpg_clocks R8A7779_CLK_P>,
424 <&cpg_clocks R8A7779_CLK_P>;
425 #clock-cells = <1>;
426 renesas,clock-indices = <
427 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
428 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
429 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
430 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
431 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
432 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
433 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
434 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
435 >;
436 clock-output-names =
437 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
438 "hscif0", "scif5", "scif4", "scif3", "scif2",
439 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
440 "i2c0";
441 };
442 mstp1_clks: clocks@ffc80034 {
443 compatible = "renesas,r8a7779-mstp-clocks",
444 "renesas,cpg-mstp-clocks";
445 reg = <0xffc80034 4>, <0xffc80044 4>;
446 clocks = <&cpg_clocks R8A7779_CLK_P>,
447 <&cpg_clocks R8A7779_CLK_P>,
448 <&cpg_clocks R8A7779_CLK_S>,
449 <&cpg_clocks R8A7779_CLK_S>,
450 <&cpg_clocks R8A7779_CLK_S>,
451 <&cpg_clocks R8A7779_CLK_S>,
452 <&cpg_clocks R8A7779_CLK_P>,
453 <&cpg_clocks R8A7779_CLK_P>,
454 <&cpg_clocks R8A7779_CLK_P>,
455 <&cpg_clocks R8A7779_CLK_S>;
456 #clock-cells = <1>;
457 renesas,clock-indices = <
458 R8A7779_CLK_USB01 R8A7779_CLK_USB2
459 R8A7779_CLK_DU R8A7779_CLK_VIN2
460 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
461 R8A7779_CLK_ETHER R8A7779_CLK_SATA
462 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
463 >;
464 clock-output-names =
465 "usb01", "usb2",
466 "du", "vin2",
467 "vin1", "vin0",
468 "ether", "sata",
469 "pcie", "vin3";
470 };
471 mstp3_clks: clocks@ffc8003c {
472 compatible = "renesas,r8a7779-mstp-clocks",
473 "renesas,cpg-mstp-clocks";
474 reg = <0xffc8003c 4>;
475 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
476 <&s4_clk>, <&s4_clk>;
477 #clock-cells = <1>;
478 renesas,clock-indices = <
479 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
480 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
481 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
482 >;
483 clock-output-names =
484 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
485 "mmc1", "mmc0";
486 };
487 };
268}; 488};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 21:00:46 -0500