1 files changed, 51 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index e3e009a5912b..1f130bc16858 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -2,6 +2,9 @@
 
 #include "skeleton.dtsi"
 
+#include <dt-bindings/clock/qcom,gcc-apq8084.h>
+#include <dt-bindings/gpio/gpio.h>
+
 / {
         model = "Qualcomm APQ 8084";
         compatible = "qcom,apq8084";
@@ -175,5 +178,53 @@
                         compatible = "qcom,pshold";
                         reg = <0xfc4ab000 0x4>;
                 };
+
+                gcc: clock-controller@fc400000 {
+                        compatible = "qcom,gcc-apq8084";
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        reg = <0xfc400000 0x4000>;
+                };
+
+                tlmm: pinctrl@fd510000 {
+                        compatible = "qcom,apq8084-pinctrl";
+                        reg = <0xfd510000 0x4000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 208 0>;
+                };
+
+                serial@f995e000 {
+                        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                        reg = <0xf995e000 0x1000>;
+                        interrupts = <0 114 0x0>;
+                        clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                sdhci@f9824900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 123 0>, <0 138 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+
+                sdhci@f98a4900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
         };
 };