1 files changed, 55 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index 1f130bc16858..7084010ee61b 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -21,6 +21,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@1 {
@@ -30,6 +32,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@2 {
@@ -39,6 +43,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 cpu@3 {
@@ -48,6 +54,8 @@
                         enable-method = "qcom,kpss-acc-v2";
                         next-level-cache = <&L2>;
                         qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                        cpu-idle-states = <&CPU_SPC>;
                 };
 
                 L2: l2-cache {
@@ -55,6 +63,16 @@
                         cache-level = <2>;
                         qcom,saw = <&saw_l2>;
                 };
+
+                idle-states {
+                        CPU_SPC: spc {
+                                compatible = "qcom,idle-state-spc",
+                                                "arm,idle-state";
+                                entry-latency-us = <150>;
+                                exit-latency-us = <200>;
+                                min-residency-us = <2000>;
+                        };
+                };
         };
 
         cpu-pmu {
@@ -144,7 +162,27 @@
                         };
                 };
 
-                saw_l2: regulator@f9012000 {
+                saw0: power-controller@f9089000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw1: power-controller@f9099000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw2: power-controller@f90a9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw3: power-controller@f90b9000 {
+                        compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
+                        reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
+                };
+
+                saw_l2: power-controller@f9012000 {
                         compatible = "qcom,saw2";
                         reg = <0xf9012000 0x1000>;
                         regulator;
@@ -226,5 +264,21 @@
                         clock-names = "core", "iface";
                         status = "disabled";
                 };
+
+                spmi_bus: spmi@fc4cf000 {
+                        compatible = "qcom,spmi-pmic-arb";
+                        reg-names = "core", "intr", "cnfg";
+                        reg = <0xfc4cf000 0x1000>,
+                              <0xfc4cb000 0x1000>,
+                              <0xfc4ca000 0x1000>;
+                        interrupt-names = "periph_irq";
+                        interrupts = <0 190 0>;
+                        qcom,ee = <0>;
+                        qcom,channel = <0>;
+                        #address-cells = <2>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        #interrupt-cells = <4>;
+                };
         };
 };