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-rw-r--r--arch/arm/boot/dts/prima2.dtsi23
1 files changed, 12 insertions, 11 deletions
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 0e219932d7cc..20145526cd7b 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -76,9 +76,10 @@
76 #clock-cells = <1>; 76 #clock-cells = <1>;
77 }; 77 };
78 78
79 reset-controller@88010000 { 79 rstc: reset-controller@88010000 {
80 compatible = "sirf,prima2-rstc"; 80 compatible = "sirf,prima2-rstc";
81 reg = <0x88010000 0x1000>; 81 reg = <0x88010000 0x1000>;
82 #reset-cells = <1>;
82 }; 83 };
83 84
84 rsc-controller@88020000 { 85 rsc-controller@88020000 {
@@ -223,8 +224,8 @@
223 interrupts = <17>; 224 interrupts = <17>;
224 fifosize = <128>; 225 fifosize = <128>;
225 clocks = <&clks 13>; 226 clocks = <&clks 13>;
226 sirf,uart-dma-rx-channel = <21>; 227 dmas = <&dmac1 5>, <&dmac0 2>;
227 sirf,uart-dma-tx-channel = <2>; 228 dma-names = "rx", "tx";
228 }; 229 };
229 230
230 uart1: uart@b0060000 { 231 uart1: uart@b0060000 {
@@ -243,8 +244,8 @@
243 interrupts = <19>; 244 interrupts = <19>;
244 fifosize = <128>; 245 fifosize = <128>;
245 clocks = <&clks 15>; 246 clocks = <&clks 15>;
246 sirf,uart-dma-rx-channel = <6>; 247 dmas = <&dmac0 6>, <&dmac0 7>;
247 sirf,uart-dma-tx-channel = <7>; 248 dma-names = "rx", "tx";
248 }; 249 };
249 250
250 usp0: usp@b0080000 { 251 usp0: usp@b0080000 {
@@ -254,8 +255,8 @@
254 interrupts = <20>; 255 interrupts = <20>;
255 fifosize = <128>; 256 fifosize = <128>;
256 clocks = <&clks 28>; 257 clocks = <&clks 28>;
257 sirf,usp-dma-rx-channel = <17>; 258 dmas = <&dmac1 1>, <&dmac1 2>;
258 sirf,usp-dma-tx-channel = <18>; 259 dma-names = "rx", "tx";
259 }; 260 };
260 261
261 usp1: usp@b0090000 { 262 usp1: usp@b0090000 {
@@ -265,8 +266,8 @@
265 interrupts = <21>; 266 interrupts = <21>;
266 fifosize = <128>; 267 fifosize = <128>;
267 clocks = <&clks 29>; 268 clocks = <&clks 29>;
268 sirf,usp-dma-rx-channel = <14>; 269 dmas = <&dmac0 14>, <&dmac0 15>;
269 sirf,usp-dma-tx-channel = <15>; 270 dma-names = "rx", "tx";
270 }; 271 };
271 272
272 usp2: usp@b00a0000 { 273 usp2: usp@b00a0000 {
@@ -276,8 +277,8 @@
276 interrupts = <22>; 277 interrupts = <22>;
277 fifosize = <128>; 278 fifosize = <128>;
278 clocks = <&clks 30>; 279 clocks = <&clks 30>;
279 sirf,usp-dma-rx-channel = <10>; 280 dmas = <&dmac0 10>, <&dmac0 11>;
280 sirf,usp-dma-tx-channel = <11>; 281 dma-names = "rx", "tx";
281 }; 282 };
282 283
283 dmac0: dma-controller@b00b0000 { 284 dmac0: dma-controller@b00b0000 {