aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/orion5x.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/orion5x.dtsi')
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi289
1 files changed, 178 insertions, 111 deletions
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 174d89241f70..75cd01bd6024 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -6,7 +6,9 @@
6 * warranty of any kind, whether express or implied. 6 * warranty of any kind, whether express or implied.
7 */ 7 */
8 8
9/include/ "skeleton.dtsi" 9#include "skeleton.dtsi"
10
11#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
10 12
11/ { 13/ {
12 model = "Marvell Orion5x SoC"; 14 model = "Marvell Orion5x SoC";
@@ -17,149 +19,214 @@
17 gpio0 = &gpio0; 19 gpio0 = &gpio0;
18 }; 20 };
19 21
20 intc: interrupt-controller { 22 soc {
21 compatible = "marvell,orion-intc"; 23 #address-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <1>;
24 reg = <0xf1020200 0x08>;
25 };
26
27 ocp@f1000000 {
28 compatible = "simple-bus";
29 ranges = <0x00000000 0xf1000000 0x4000000
30 0xf2200000 0xf2200000 0x0000800>;
31 #address-cells = <1>;
32 #size-cells = <1>; 24 #size-cells = <1>;
25 controller = <&mbusc>;
33 26
34 gpio0: gpio@10100 { 27 devbus_bootcs: devbus-bootcs {
35 compatible = "marvell,orion-gpio"; 28 compatible = "marvell,orion-devbus";
36 #gpio-cells = <2>; 29 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
37 gpio-controller; 30 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
38 reg = <0x10100 0x40>;
39 ngpios = <32>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
42 interrupts = <6>, <7>, <8>, <9>;
43 };
44
45 spi@10600 {
46 compatible = "marvell,orion-spi";
47 #address-cells = <1>; 31 #address-cells = <1>;
48 #size-cells = <0>; 32 #size-cells = <1>;
49 cell-index = <0>; 33 clocks = <&core_clk 0>;
50 reg = <0x10600 0x28>;
51 status = "disabled"; 34 status = "disabled";
52 }; 35 };
53 36
54 i2c@11000 { 37 devbus_cs0: devbus-cs0 {
55 compatible = "marvell,mv64xxx-i2c"; 38 compatible = "marvell,orion-devbus";
56 reg = <0x11000 0x20>; 39 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
57 #address-cells = <1>; 41 #address-cells = <1>;
58 #size-cells = <0>; 42 #size-cells = <1>;
59 interrupts = <5>; 43 clocks = <&core_clk 0>;
60 clock-frequency = <100000>;
61 status = "disabled"; 44 status = "disabled";
62 }; 45 };
63 46
64 serial@12000 { 47 devbus_cs1: devbus-cs1 {
65 compatible = "ns16550a"; 48 compatible = "marvell,orion-devbus";
66 reg = <0x12000 0x100>; 49 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
67 reg-shift = <2>; 50 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
68 interrupts = <3>; 51 #address-cells = <1>;
69 /* set clock-frequency in board dts */ 52 #size-cells = <1>;
53 clocks = <&core_clk 0>;
70 status = "disabled"; 54 status = "disabled";
71 }; 55 };
72 56
73 serial@12100 { 57 devbus_cs2: devbus-cs2 {
74 compatible = "ns16550a"; 58 compatible = "marvell,orion-devbus";
75 reg = <0x12100 0x100>; 59 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
76 reg-shift = <2>; 60 ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
77 interrupts = <4>; 61 #address-cells = <1>;
78 /* set clock-frequency in board dts */ 62 #size-cells = <1>;
63 clocks = <&core_clk 0>;
79 status = "disabled"; 64 status = "disabled";
80 }; 65 };
81 66
82 wdt@20300 { 67 internal-regs {
83 compatible = "marvell,orion-wdt"; 68 compatible = "simple-bus";
84 reg = <0x20300 0x28>; 69 #address-cells = <1>;
85 status = "okay"; 70 #size-cells = <1>;
86 }; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
72
73 gpio0: gpio@10100 {
74 compatible = "marvell,orion-gpio";
75 #gpio-cells = <2>;
76 gpio-controller;
77 reg = <0x10100 0x40>;
78 ngpios = <32>;
79 interrupt-controller;
80 #interrupt-cells = <2>;
81 interrupts = <6>, <7>, <8>, <9>;
82 };
87 83
88 ehci@50000 { 84 spi: spi@10600 {
89 compatible = "marvell,orion-ehci"; 85 compatible = "marvell,orion-spi";
90 reg = <0x50000 0x1000>; 86 #address-cells = <1>;
91 interrupts = <17>; 87 #size-cells = <0>;
92 status = "disabled"; 88 cell-index = <0>;
93 }; 89 reg = <0x10600 0x28>;
90 status = "disabled";
91 };
94 92
95 xor@60900 { 93 i2c: i2c@11000 {
96 compatible = "marvell,orion-xor"; 94 compatible = "marvell,mv64xxx-i2c";
97 reg = <0x60900 0x100 95 reg = <0x11000 0x20>;
98 0x60b00 0x100>; 96 #address-cells = <1>;
99 status = "okay"; 97 #size-cells = <0>;
98 interrupts = <5>;
99 clocks = <&core_clk 0>;
100 status = "disabled";
101 };
100 102
101 xor00 { 103 uart0: serial@12000 {
102 interrupts = <30>; 104 compatible = "ns16550a";
103 dmacap,memcpy; 105 reg = <0x12000 0x100>;
104 dmacap,xor; 106 reg-shift = <2>;
107 interrupts = <3>;
108 clocks = <&core_clk 0>;
109 status = "disabled";
105 }; 110 };
106 xor01 { 111
107 interrupts = <31>; 112 uart1: serial@12100 {
108 dmacap,memcpy; 113 compatible = "ns16550a";
109 dmacap,xor; 114 reg = <0x12100 0x100>;
110 dmacap,memset; 115 reg-shift = <2>;
116 interrupts = <4>;
117 clocks = <&core_clk 0>;
118 status = "disabled";
111 }; 119 };
112 };
113 120
114 eth: ethernet-controller@72000 { 121 bridge_intc: bridge-interrupt-ctrl@20110 {
115 compatible = "marvell,orion-eth"; 122 compatible = "marvell,orion-bridge-intc";
116 #address-cells = <1>; 123 interrupt-controller;
117 #size-cells = <0>; 124 #interrupt-cells = <1>;
118 reg = <0x72000 0x4000>; 125 reg = <0x20110 0x8>;
119 marvell,tx-checksum-limit = <1600>; 126 interrupts = <0>;
120 status = "disabled"; 127 marvell,#interrupts = <4>;
128 };
121 129
122 ethernet-port@0 { 130 intc: interrupt-controller@20200 {
123 compatible = "marvell,orion-eth-port"; 131 compatible = "marvell,orion-intc";
124 reg = <0>; 132 interrupt-controller;
125 /* overwrite MAC address in bootloader */ 133 #interrupt-cells = <1>;
126 local-mac-address = [00 00 00 00 00 00]; 134 reg = <0x20200 0x08>;
127 /* set phy-handle property in board file */
128 }; 135 };
129 };
130 136
131 mdio: mdio-bus@72004 { 137 timer: timer@20300 {
132 compatible = "marvell,orion-mdio"; 138 compatible = "marvell,orion-timer";
133 #address-cells = <1>; 139 reg = <0x20300 0x20>;
134 #size-cells = <0>; 140 interrupt-parent = <&bridge_intc>;
135 reg = <0x72004 0x84>; 141 interrupts = <1>, <2>;
136 interrupts = <22>; 142 clocks = <&core_clk 0>;
137 status = "disabled"; 143 };
138 144
139 /* add phy nodes in board file */ 145 wdt: wdt@20300 {
140 }; 146 compatible = "marvell,orion-wdt";
147 reg = <0x20300 0x28>;
148 interrupt-parent = <&bridge_intc>;
149 interrupts = <3>;
150 status = "okay";
151 };
141 152
142 sata@80000 { 153 ehci0: ehci@50000 {
143 compatible = "marvell,orion-sata"; 154 compatible = "marvell,orion-ehci";
144 reg = <0x80000 0x5000>; 155 reg = <0x50000 0x1000>;
145 interrupts = <29>; 156 interrupts = <17>;
146 status = "disabled"; 157 status = "disabled";
158 };
159
160 xor: dma-controller@60900 {
161 compatible = "marvell,orion-xor";
162 reg = <0x60900 0x100
163 0x60b00 0x100>;
164 status = "okay";
165
166 xor00 {
167 interrupts = <30>;
168 dmacap,memcpy;
169 dmacap,xor;
170 };
171 xor01 {
172 interrupts = <31>;
173 dmacap,memcpy;
174 dmacap,xor;
175 dmacap,memset;
176 };
177 };
178
179 eth: ethernet-controller@72000 {
180 compatible = "marvell,orion-eth";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 reg = <0x72000 0x4000>;
184 marvell,tx-checksum-limit = <1600>;
185 status = "disabled";
186
187 ethport: ethernet-port@0 {
188 compatible = "marvell,orion-eth-port";
189 reg = <0>;
190 interrupts = <21>;
191 /* overwrite MAC address in bootloader */
192 local-mac-address = [00 00 00 00 00 00];
193 /* set phy-handle property in board file */
194 };
195 };
196
197 mdio: mdio-bus@72004 {
198 compatible = "marvell,orion-mdio";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 reg = <0x72004 0x84>;
202 interrupts = <22>;
203 status = "disabled";
204
205 /* add phy nodes in board file */
206 };
207
208 sata: sata@80000 {
209 compatible = "marvell,orion-sata";
210 reg = <0x80000 0x5000>;
211 interrupts = <29>;
212 status = "disabled";
213 };
214
215 ehci1: ehci@a0000 {
216 compatible = "marvell,orion-ehci";
217 reg = <0xa0000 0x1000>;
218 interrupts = <12>;
219 status = "disabled";
220 };
147 }; 221 };
148 222
149 crypto@90000 { 223 cesa: crypto@90000 {
150 compatible = "marvell,orion-crypto"; 224 compatible = "marvell,orion-crypto";
151 reg = <0x90000 0x10000>, 225 reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
152 <0xf2200000 0x800>; 226 <MBUS_ID(0x09, 0x00) 0x0 0x800>;
153 reg-names = "regs", "sram"; 227 reg-names = "regs", "sram";
154 interrupts = <28>; 228 interrupts = <28>;
155 status = "okay"; 229 status = "okay";
156 }; 230 };
157
158 ehci@a0000 {
159 compatible = "marvell,orion-ehci";
160 reg = <0xa0000 0x1000>;
161 interrupts = <12>;
162 status = "disabled";
163 };
164 }; 231 };
165}; 232};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 23:07:44 -0500