diff options
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 178 |
1 files changed, 169 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 42c78beb4fdc..790bb2a4b343 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
| @@ -77,6 +77,12 @@ | |||
| 77 | ranges; | 77 | ranges; |
| 78 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; | 78 | ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; |
| 79 | 79 | ||
| 80 | counter32k: counter@4ae04000 { | ||
| 81 | compatible = "ti,omap-counter32k"; | ||
| 82 | reg = <0x4ae04000 0x40>; | ||
| 83 | ti,hwmods = "counter_32k"; | ||
| 84 | }; | ||
| 85 | |||
| 80 | omap5_pmx_core: pinmux@4a002840 { | 86 | omap5_pmx_core: pinmux@4a002840 { |
| 81 | compatible = "ti,omap4-padconf", "pinctrl-single"; | 87 | compatible = "ti,omap4-padconf", "pinctrl-single"; |
| 82 | reg = <0x4a002840 0x01b6>; | 88 | reg = <0x4a002840 0x01b6>; |
| @@ -104,6 +110,8 @@ | |||
| 104 | 110 | ||
| 105 | gpio1: gpio@4ae10000 { | 111 | gpio1: gpio@4ae10000 { |
| 106 | compatible = "ti,omap4-gpio"; | 112 | compatible = "ti,omap4-gpio"; |
| 113 | reg = <0x4ae10000 0x200>; | ||
| 114 | interrupts = <0 29 0x4>; | ||
| 107 | ti,hwmods = "gpio1"; | 115 | ti,hwmods = "gpio1"; |
| 108 | gpio-controller; | 116 | gpio-controller; |
| 109 | #gpio-cells = <2>; | 117 | #gpio-cells = <2>; |
| @@ -113,6 +121,8 @@ | |||
| 113 | 121 | ||
| 114 | gpio2: gpio@48055000 { | 122 | gpio2: gpio@48055000 { |
| 115 | compatible = "ti,omap4-gpio"; | 123 | compatible = "ti,omap4-gpio"; |
| 124 | reg = <0x48055000 0x200>; | ||
| 125 | interrupts = <0 30 0x4>; | ||
| 116 | ti,hwmods = "gpio2"; | 126 | ti,hwmods = "gpio2"; |
| 117 | gpio-controller; | 127 | gpio-controller; |
| 118 | #gpio-cells = <2>; | 128 | #gpio-cells = <2>; |
| @@ -122,6 +132,8 @@ | |||
| 122 | 132 | ||
| 123 | gpio3: gpio@48057000 { | 133 | gpio3: gpio@48057000 { |
| 124 | compatible = "ti,omap4-gpio"; | 134 | compatible = "ti,omap4-gpio"; |
| 135 | reg = <0x48057000 0x200>; | ||
| 136 | interrupts = <0 31 0x4>; | ||
| 125 | ti,hwmods = "gpio3"; | 137 | ti,hwmods = "gpio3"; |
| 126 | gpio-controller; | 138 | gpio-controller; |
| 127 | #gpio-cells = <2>; | 139 | #gpio-cells = <2>; |
| @@ -131,6 +143,8 @@ | |||
| 131 | 143 | ||
| 132 | gpio4: gpio@48059000 { | 144 | gpio4: gpio@48059000 { |
| 133 | compatible = "ti,omap4-gpio"; | 145 | compatible = "ti,omap4-gpio"; |
| 146 | reg = <0x48059000 0x200>; | ||
| 147 | interrupts = <0 32 0x4>; | ||
| 134 | ti,hwmods = "gpio4"; | 148 | ti,hwmods = "gpio4"; |
| 135 | gpio-controller; | 149 | gpio-controller; |
| 136 | #gpio-cells = <2>; | 150 | #gpio-cells = <2>; |
| @@ -140,6 +154,8 @@ | |||
| 140 | 154 | ||
| 141 | gpio5: gpio@4805b000 { | 155 | gpio5: gpio@4805b000 { |
| 142 | compatible = "ti,omap4-gpio"; | 156 | compatible = "ti,omap4-gpio"; |
| 157 | reg = <0x4805b000 0x200>; | ||
| 158 | interrupts = <0 33 0x4>; | ||
| 143 | ti,hwmods = "gpio5"; | 159 | ti,hwmods = "gpio5"; |
| 144 | gpio-controller; | 160 | gpio-controller; |
| 145 | #gpio-cells = <2>; | 161 | #gpio-cells = <2>; |
| @@ -149,6 +165,8 @@ | |||
| 149 | 165 | ||
| 150 | gpio6: gpio@4805d000 { | 166 | gpio6: gpio@4805d000 { |
| 151 | compatible = "ti,omap4-gpio"; | 167 | compatible = "ti,omap4-gpio"; |
| 168 | reg = <0x4805d000 0x200>; | ||
| 169 | interrupts = <0 34 0x4>; | ||
| 152 | ti,hwmods = "gpio6"; | 170 | ti,hwmods = "gpio6"; |
| 153 | gpio-controller; | 171 | gpio-controller; |
| 154 | #gpio-cells = <2>; | 172 | #gpio-cells = <2>; |
| @@ -158,6 +176,8 @@ | |||
| 158 | 176 | ||
| 159 | gpio7: gpio@48051000 { | 177 | gpio7: gpio@48051000 { |
| 160 | compatible = "ti,omap4-gpio"; | 178 | compatible = "ti,omap4-gpio"; |
| 179 | reg = <0x48051000 0x200>; | ||
| 180 | interrupts = <0 35 0x4>; | ||
| 161 | ti,hwmods = "gpio7"; | 181 | ti,hwmods = "gpio7"; |
| 162 | gpio-controller; | 182 | gpio-controller; |
| 163 | #gpio-cells = <2>; | 183 | #gpio-cells = <2>; |
| @@ -167,6 +187,8 @@ | |||
| 167 | 187 | ||
| 168 | gpio8: gpio@48053000 { | 188 | gpio8: gpio@48053000 { |
| 169 | compatible = "ti,omap4-gpio"; | 189 | compatible = "ti,omap4-gpio"; |
| 190 | reg = <0x48053000 0x200>; | ||
| 191 | interrupts = <0 121 0x4>; | ||
| 170 | ti,hwmods = "gpio8"; | 192 | ti,hwmods = "gpio8"; |
| 171 | gpio-controller; | 193 | gpio-controller; |
| 172 | #gpio-cells = <2>; | 194 | #gpio-cells = <2>; |
| @@ -176,6 +198,8 @@ | |||
| 176 | 198 | ||
| 177 | i2c1: i2c@48070000 { | 199 | i2c1: i2c@48070000 { |
| 178 | compatible = "ti,omap4-i2c"; | 200 | compatible = "ti,omap4-i2c"; |
| 201 | reg = <0x48070000 0x100>; | ||
| 202 | interrupts = <0 56 0x4>; | ||
| 179 | #address-cells = <1>; | 203 | #address-cells = <1>; |
| 180 | #size-cells = <0>; | 204 | #size-cells = <0>; |
| 181 | ti,hwmods = "i2c1"; | 205 | ti,hwmods = "i2c1"; |
| @@ -183,6 +207,8 @@ | |||
| 183 | 207 | ||
| 184 | i2c2: i2c@48072000 { | 208 | i2c2: i2c@48072000 { |
| 185 | compatible = "ti,omap4-i2c"; | 209 | compatible = "ti,omap4-i2c"; |
| 210 | reg = <0x48072000 0x100>; | ||
| 211 | interrupts = <0 57 0x4>; | ||
| 186 | #address-cells = <1>; | 212 | #address-cells = <1>; |
| 187 | #size-cells = <0>; | 213 | #size-cells = <0>; |
| 188 | ti,hwmods = "i2c2"; | 214 | ti,hwmods = "i2c2"; |
| @@ -190,20 +216,26 @@ | |||
| 190 | 216 | ||
| 191 | i2c3: i2c@48060000 { | 217 | i2c3: i2c@48060000 { |
| 192 | compatible = "ti,omap4-i2c"; | 218 | compatible = "ti,omap4-i2c"; |
| 219 | reg = <0x48060000 0x100>; | ||
| 220 | interrupts = <0 61 0x4>; | ||
| 193 | #address-cells = <1>; | 221 | #address-cells = <1>; |
| 194 | #size-cells = <0>; | 222 | #size-cells = <0>; |
| 195 | ti,hwmods = "i2c3"; | 223 | ti,hwmods = "i2c3"; |
| 196 | }; | 224 | }; |
| 197 | 225 | ||
| 198 | i2c4: i2c@4807A000 { | 226 | i2c4: i2c@4807a000 { |
| 199 | compatible = "ti,omap4-i2c"; | 227 | compatible = "ti,omap4-i2c"; |
| 228 | reg = <0x4807a000 0x100>; | ||
| 229 | interrupts = <0 62 0x4>; | ||
| 200 | #address-cells = <1>; | 230 | #address-cells = <1>; |
| 201 | #size-cells = <0>; | 231 | #size-cells = <0>; |
| 202 | ti,hwmods = "i2c4"; | 232 | ti,hwmods = "i2c4"; |
| 203 | }; | 233 | }; |
| 204 | 234 | ||
| 205 | i2c5: i2c@4807C000 { | 235 | i2c5: i2c@4807c000 { |
| 206 | compatible = "ti,omap4-i2c"; | 236 | compatible = "ti,omap4-i2c"; |
| 237 | reg = <0x4807c000 0x100>; | ||
| 238 | interrupts = <0 60 0x4>; | ||
| 207 | #address-cells = <1>; | 239 | #address-cells = <1>; |
| 208 | #size-cells = <0>; | 240 | #size-cells = <0>; |
| 209 | ti,hwmods = "i2c5"; | 241 | ti,hwmods = "i2c5"; |
| @@ -211,42 +243,56 @@ | |||
| 211 | 243 | ||
| 212 | uart1: serial@4806a000 { | 244 | uart1: serial@4806a000 { |
| 213 | compatible = "ti,omap4-uart"; | 245 | compatible = "ti,omap4-uart"; |
| 246 | reg = <0x4806a000 0x100>; | ||
| 247 | interrupts = <0 72 0x4>; | ||
| 214 | ti,hwmods = "uart1"; | 248 | ti,hwmods = "uart1"; |
| 215 | clock-frequency = <48000000>; | 249 | clock-frequency = <48000000>; |
| 216 | }; | 250 | }; |
| 217 | 251 | ||
| 218 | uart2: serial@4806c000 { | 252 | uart2: serial@4806c000 { |
| 219 | compatible = "ti,omap4-uart"; | 253 | compatible = "ti,omap4-uart"; |
| 254 | reg = <0x4806c000 0x100>; | ||
| 255 | interrupts = <0 73 0x4>; | ||
| 220 | ti,hwmods = "uart2"; | 256 | ti,hwmods = "uart2"; |
| 221 | clock-frequency = <48000000>; | 257 | clock-frequency = <48000000>; |
| 222 | }; | 258 | }; |
| 223 | 259 | ||
| 224 | uart3: serial@48020000 { | 260 | uart3: serial@48020000 { |
| 225 | compatible = "ti,omap4-uart"; | 261 | compatible = "ti,omap4-uart"; |
| 262 | reg = <0x48020000 0x100>; | ||
| 263 | interrupts = <0 74 0x4>; | ||
| 226 | ti,hwmods = "uart3"; | 264 | ti,hwmods = "uart3"; |
| 227 | clock-frequency = <48000000>; | 265 | clock-frequency = <48000000>; |
| 228 | }; | 266 | }; |
| 229 | 267 | ||
| 230 | uart4: serial@4806e000 { | 268 | uart4: serial@4806e000 { |
| 231 | compatible = "ti,omap4-uart"; | 269 | compatible = "ti,omap4-uart"; |
| 270 | reg = <0x4806e000 0x100>; | ||
| 271 | interrupts = <0 70 0x4>; | ||
| 232 | ti,hwmods = "uart4"; | 272 | ti,hwmods = "uart4"; |
| 233 | clock-frequency = <48000000>; | 273 | clock-frequency = <48000000>; |
| 234 | }; | 274 | }; |
| 235 | 275 | ||
| 236 | uart5: serial@48066000 { | 276 | uart5: serial@48066000 { |
| 237 | compatible = "ti,omap5-uart"; | 277 | compatible = "ti,omap4-uart"; |
| 278 | reg = <0x48066000 0x100>; | ||
| 279 | interrupts = <0 105 0x4>; | ||
| 238 | ti,hwmods = "uart5"; | 280 | ti,hwmods = "uart5"; |
| 239 | clock-frequency = <48000000>; | 281 | clock-frequency = <48000000>; |
| 240 | }; | 282 | }; |
| 241 | 283 | ||
| 242 | uart6: serial@48068000 { | 284 | uart6: serial@48068000 { |
| 243 | compatible = "ti,omap6-uart"; | 285 | compatible = "ti,omap4-uart"; |
| 286 | reg = <0x48068000 0x100>; | ||
| 287 | interrupts = <0 106 0x4>; | ||
| 244 | ti,hwmods = "uart6"; | 288 | ti,hwmods = "uart6"; |
| 245 | clock-frequency = <48000000>; | 289 | clock-frequency = <48000000>; |
| 246 | }; | 290 | }; |
| 247 | 291 | ||
| 248 | mmc1: mmc@4809c000 { | 292 | mmc1: mmc@4809c000 { |
| 249 | compatible = "ti,omap4-hsmmc"; | 293 | compatible = "ti,omap4-hsmmc"; |
| 294 | reg = <0x4809c000 0x400>; | ||
| 295 | interrupts = <0 83 0x4>; | ||
| 250 | ti,hwmods = "mmc1"; | 296 | ti,hwmods = "mmc1"; |
| 251 | ti,dual-volt; | 297 | ti,dual-volt; |
| 252 | ti,needs-special-reset; | 298 | ti,needs-special-reset; |
| @@ -254,24 +300,32 @@ | |||
| 254 | 300 | ||
| 255 | mmc2: mmc@480b4000 { | 301 | mmc2: mmc@480b4000 { |
| 256 | compatible = "ti,omap4-hsmmc"; | 302 | compatible = "ti,omap4-hsmmc"; |
| 303 | reg = <0x480b4000 0x400>; | ||
| 304 | interrupts = <0 86 0x4>; | ||
| 257 | ti,hwmods = "mmc2"; | 305 | ti,hwmods = "mmc2"; |
| 258 | ti,needs-special-reset; | 306 | ti,needs-special-reset; |
| 259 | }; | 307 | }; |
| 260 | 308 | ||
| 261 | mmc3: mmc@480ad000 { | 309 | mmc3: mmc@480ad000 { |
| 262 | compatible = "ti,omap4-hsmmc"; | 310 | compatible = "ti,omap4-hsmmc"; |
| 311 | reg = <0x480ad000 0x400>; | ||
| 312 | interrupts = <0 94 0x4>; | ||
| 263 | ti,hwmods = "mmc3"; | 313 | ti,hwmods = "mmc3"; |
| 264 | ti,needs-special-reset; | 314 | ti,needs-special-reset; |
| 265 | }; | 315 | }; |
| 266 | 316 | ||
| 267 | mmc4: mmc@480d1000 { | 317 | mmc4: mmc@480d1000 { |
| 268 | compatible = "ti,omap4-hsmmc"; | 318 | compatible = "ti,omap4-hsmmc"; |
| 319 | reg = <0x480d1000 0x400>; | ||
| 320 | interrupts = <0 96 0x4>; | ||
| 269 | ti,hwmods = "mmc4"; | 321 | ti,hwmods = "mmc4"; |
| 270 | ti,needs-special-reset; | 322 | ti,needs-special-reset; |
| 271 | }; | 323 | }; |
| 272 | 324 | ||
| 273 | mmc5: mmc@480d5000 { | 325 | mmc5: mmc@480d5000 { |
| 274 | compatible = "ti,omap4-hsmmc"; | 326 | compatible = "ti,omap4-hsmmc"; |
| 327 | reg = <0x480d5000 0x400>; | ||
| 328 | interrupts = <0 59 0x4>; | ||
| 275 | ti,hwmods = "mmc5"; | 329 | ti,hwmods = "mmc5"; |
| 276 | ti,needs-special-reset; | 330 | ti,needs-special-reset; |
| 277 | }; | 331 | }; |
| @@ -287,7 +341,6 @@ | |||
| 287 | <0x49032000 0x7f>; /* L3 Interconnect */ | 341 | <0x49032000 0x7f>; /* L3 Interconnect */ |
| 288 | reg-names = "mpu", "dma"; | 342 | reg-names = "mpu", "dma"; |
| 289 | interrupts = <0 112 0x4>; | 343 | interrupts = <0 112 0x4>; |
| 290 | interrupt-parent = <&gic>; | ||
| 291 | ti,hwmods = "mcpdm"; | 344 | ti,hwmods = "mcpdm"; |
| 292 | }; | 345 | }; |
| 293 | 346 | ||
| @@ -297,7 +350,6 @@ | |||
| 297 | <0x4902e000 0x7f>; /* L3 Interconnect */ | 350 | <0x4902e000 0x7f>; /* L3 Interconnect */ |
| 298 | reg-names = "mpu", "dma"; | 351 | reg-names = "mpu", "dma"; |
| 299 | interrupts = <0 114 0x4>; | 352 | interrupts = <0 114 0x4>; |
| 300 | interrupt-parent = <&gic>; | ||
| 301 | ti,hwmods = "dmic"; | 353 | ti,hwmods = "dmic"; |
| 302 | }; | 354 | }; |
| 303 | 355 | ||
| @@ -308,7 +360,6 @@ | |||
| 308 | reg-names = "mpu", "dma"; | 360 | reg-names = "mpu", "dma"; |
| 309 | interrupts = <0 17 0x4>; | 361 | interrupts = <0 17 0x4>; |
| 310 | interrupt-names = "common"; | 362 | interrupt-names = "common"; |
| 311 | interrupt-parent = <&gic>; | ||
| 312 | ti,buffer-size = <128>; | 363 | ti,buffer-size = <128>; |
| 313 | ti,hwmods = "mcbsp1"; | 364 | ti,hwmods = "mcbsp1"; |
| 314 | }; | 365 | }; |
| @@ -320,7 +371,6 @@ | |||
| 320 | reg-names = "mpu", "dma"; | 371 | reg-names = "mpu", "dma"; |
| 321 | interrupts = <0 22 0x4>; | 372 | interrupts = <0 22 0x4>; |
| 322 | interrupt-names = "common"; | 373 | interrupt-names = "common"; |
| 323 | interrupt-parent = <&gic>; | ||
| 324 | ti,buffer-size = <128>; | 374 | ti,buffer-size = <128>; |
| 325 | ti,hwmods = "mcbsp2"; | 375 | ti,hwmods = "mcbsp2"; |
| 326 | }; | 376 | }; |
| @@ -332,9 +382,119 @@ | |||
| 332 | reg-names = "mpu", "dma"; | 382 | reg-names = "mpu", "dma"; |
| 333 | interrupts = <0 23 0x4>; | 383 | interrupts = <0 23 0x4>; |
| 334 | interrupt-names = "common"; | 384 | interrupt-names = "common"; |
| 335 | interrupt-parent = <&gic>; | ||
| 336 | ti,buffer-size = <128>; | 385 | ti,buffer-size = <128>; |
| 337 | ti,hwmods = "mcbsp3"; | 386 | ti,hwmods = "mcbsp3"; |
| 338 | }; | 387 | }; |
| 388 | |||
| 389 | timer1: timer@4ae18000 { | ||
| 390 | compatible = "ti,omap2-timer"; | ||
| 391 | reg = <0x4ae18000 0x80>; | ||
| 392 | interrupts = <0 37 0x4>; | ||
| 393 | ti,hwmods = "timer1"; | ||
| 394 | ti,timer-alwon; | ||
| 395 | }; | ||
| 396 | |||
| 397 | timer2: timer@48032000 { | ||
| 398 | compatible = "ti,omap2-timer"; | ||
| 399 | reg = <0x48032000 0x80>; | ||
| 400 | interrupts = <0 38 0x4>; | ||
| 401 | ti,hwmods = "timer2"; | ||
| 402 | }; | ||
| 403 | |||
| 404 | timer3: timer@48034000 { | ||
| 405 | compatible = "ti,omap2-timer"; | ||
| 406 | reg = <0x48034000 0x80>; | ||
| 407 | interrupts = <0 39 0x4>; | ||
| 408 | ti,hwmods = "timer3"; | ||
| 409 | }; | ||
| 410 | |||
| 411 | timer4: timer@48036000 { | ||
| 412 | compatible = "ti,omap2-timer"; | ||
| 413 | reg = <0x48036000 0x80>; | ||
| 414 | interrupts = <0 40 0x4>; | ||
| 415 | ti,hwmods = "timer4"; | ||
| 416 | }; | ||
| 417 | |||
| 418 | timer5: timer@40138000 { | ||
| 419 | compatible = "ti,omap2-timer"; | ||
| 420 | reg = <0x40138000 0x80>, | ||
| 421 | <0x49038000 0x80>; | ||
| 422 | interrupts = <0 41 0x4>; | ||
| 423 | ti,hwmods = "timer5"; | ||
| 424 | ti,timer-dsp; | ||
| 425 | }; | ||
| 426 | |||
| 427 | timer6: timer@4013a000 { | ||
| 428 | compatible = "ti,omap2-timer"; | ||
| 429 | reg = <0x4013a000 0x80>, | ||
| 430 | <0x4903a000 0x80>; | ||
| 431 | interrupts = <0 42 0x4>; | ||
| 432 | ti,hwmods = "timer6"; | ||
| 433 | ti,timer-dsp; | ||
| 434 | ti,timer-pwm; | ||
| 435 | }; | ||
| 436 | |||
| 437 | timer7: timer@4013c000 { | ||
| 438 | compatible = "ti,omap2-timer"; | ||
| 439 | reg = <0x4013c000 0x80>, | ||
| 440 | <0x4903c000 0x80>; | ||
| 441 | interrupts = <0 43 0x4>; | ||
| 442 | ti,hwmods = "timer7"; | ||
| 443 | ti,timer-dsp; | ||
| 444 | }; | ||
| 445 | |||
| 446 | timer8: timer@4013e000 { | ||
| 447 | compatible = "ti,omap2-timer"; | ||
| 448 | reg = <0x4013e000 0x80>, | ||
| 449 | <0x4903e000 0x80>; | ||
| 450 | interrupts = <0 44 0x4>; | ||
| 451 | ti,hwmods = "timer8"; | ||
| 452 | ti,timer-dsp; | ||
| 453 | ti,timer-pwm; | ||
| 454 | }; | ||
| 455 | |||
| 456 | timer9: timer@4803e000 { | ||
| 457 | compatible = "ti,omap2-timer"; | ||
| 458 | reg = <0x4803e000 0x80>; | ||
| 459 | interrupts = <0 45 0x4>; | ||
| 460 | ti,hwmods = "timer9"; | ||
| 461 | }; | ||
| 462 | |||
| 463 | timer10: timer@48086000 { | ||
| 464 | compatible = "ti,omap2-timer"; | ||
| 465 | reg = <0x48086000 0x80>; | ||
| 466 | interrupts = <0 46 0x4>; | ||
| 467 | ti,hwmods = "timer10"; | ||
| 468 | }; | ||
| 469 | |||
| 470 | timer11: timer@48088000 { | ||
| 471 | compatible = "ti,omap2-timer"; | ||
| 472 | reg = <0x48088000 0x80>; | ||
| 473 | interrupts = <0 47 0x4>; | ||
| 474 | ti,hwmods = "timer11"; | ||
| 475 | ti,timer-pwm; | ||
| 476 | }; | ||
| 477 | |||
| 478 | emif1: emif@0x4c000000 { | ||
| 479 | compatible = "ti,emif-4d5"; | ||
| 480 | ti,hwmods = "emif1"; | ||
| 481 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | ||
| 482 | reg = <0x4c000000 0x400>; | ||
| 483 | interrupts = <0 110 0x4>; | ||
| 484 | hw-caps-read-idle-ctrl; | ||
| 485 | hw-caps-ll-interface; | ||
| 486 | hw-caps-temp-alert; | ||
| 487 | }; | ||
| 488 | |||
| 489 | emif2: emif@0x4d000000 { | ||
| 490 | compatible = "ti,emif-4d5"; | ||
| 491 | ti,hwmods = "emif2"; | ||
| 492 | phy-type = <2>; /* DDR PHY type: Intelli PHY */ | ||
| 493 | reg = <0x4d000000 0x400>; | ||
| 494 | interrupts = <0 111 0x4>; | ||
| 495 | hw-caps-read-idle-ctrl; | ||
| 496 | hw-caps-ll-interface; | ||
| 497 | hw-caps-temp-alert; | ||
| 498 | }; | ||
| 339 | }; | 499 | }; |
| 340 | }; | 500 | }; |