aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/omap4.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
-rw-r--r--arch/arm/boot/dts/omap4.dtsi195
1 files changed, 165 insertions, 30 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff91..5d1c48459e6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
30 cpus { 30 cpus {
31 cpu@0 { 31 cpu@0 {
32 compatible = "arm,cortex-a9"; 32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
33 }; 34 };
34 cpu@1 { 35 cpu@1 {
35 compatible = "arm,cortex-a9"; 36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
36 }; 38 };
37 }; 39 };
38 40
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
48
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
55
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
61
39 /* 62 /*
40 * The soc node represents the soc top level view. It is uses for IPs 63 * The soc node represents the soc top level view. It is uses for IPs
41 * that are not memory mapped in the MPU view or for the MPU itself. 64 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
61 /* 84 /*
62 * XXX: Use a flat representation of the OMAP4 interconnect. 85 * XXX: Use a flat representation of the OMAP4 interconnect.
63 * The real OMAP interconnect network is quite complex. 86 * The real OMAP interconnect network is quite complex.
64 *
65 * MPU -+-- MPU_PRIVATE - GIC, L2
66 * |
67 * +----------------+----------+
68 * | | |
69 * + +- EMIF - DDR |
70 * | | |
71 * | + +--------+
72 * | | |
73 * | +- L4_ABE - AESS, MCBSP, TIMERs...
74 * | |
75 * +- L3_MAIN --+- L4_CORE - IPs...
76 * |
77 * +- L4_PER - IPs...
78 * |
79 * +- L4_CFG -+- L4_WKUP - IPs...
80 * | |
81 * | +- IPs...
82 * +- IPU ----+
83 * | |
84 * +- DSP ----+
85 * | |
86 * +- DSS ----+
87 *
88 * Since that will not bring real advantage to represent that in DT for 87 * Since that will not bring real advantage to represent that in DT for
89 * the moment, just use a fake OCP bus entry to represent the whole bus 88 * the moment, just use a fake OCP bus entry to represent the whole bus
90 * hierarchy. 89 * hierarchy.
@@ -96,16 +95,27 @@
96 ranges; 95 ranges;
97 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
98 97
99 gic: interrupt-controller@48241000 { 98 omap4_pmx_core: pinmux@4a100040 {
100 compatible = "arm,cortex-a9-gic"; 99 compatible = "ti,omap4-padconf", "pinctrl-single";
101 interrupt-controller; 100 reg = <0x4a100040 0x0196>;
102 #interrupt-cells = <3>; 101 #address-cells = <1>;
103 reg = <0x48241000 0x1000>, 102 #size-cells = <0>;
104 <0x48240100 0x0100>; 103 pinctrl-single,register-width = <16>;
104 pinctrl-single,function-mask = <0x7fff>;
105 };
106 omap4_pmx_wkup: pinmux@4a31e040 {
107 compatible = "ti,omap4-padconf", "pinctrl-single";
108 reg = <0x4a31e040 0x0038>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0x7fff>;
105 }; 113 };
106 114
107 gpio1: gpio@4a310000 { 115 gpio1: gpio@4a310000 {
108 compatible = "ti,omap4-gpio"; 116 compatible = "ti,omap4-gpio";
117 reg = <0x4a310000 0x200>;
118 interrupts = <0 29 0x4>;
109 ti,hwmods = "gpio1"; 119 ti,hwmods = "gpio1";
110 gpio-controller; 120 gpio-controller;
111 #gpio-cells = <2>; 121 #gpio-cells = <2>;
@@ -115,6 +125,8 @@
115 125
116 gpio2: gpio@48055000 { 126 gpio2: gpio@48055000 {
117 compatible = "ti,omap4-gpio"; 127 compatible = "ti,omap4-gpio";
128 reg = <0x48055000 0x200>;
129 interrupts = <0 30 0x4>;
118 ti,hwmods = "gpio2"; 130 ti,hwmods = "gpio2";
119 gpio-controller; 131 gpio-controller;
120 #gpio-cells = <2>; 132 #gpio-cells = <2>;
@@ -124,6 +136,8 @@
124 136
125 gpio3: gpio@48057000 { 137 gpio3: gpio@48057000 {
126 compatible = "ti,omap4-gpio"; 138 compatible = "ti,omap4-gpio";
139 reg = <0x48057000 0x200>;
140 interrupts = <0 31 0x4>;
127 ti,hwmods = "gpio3"; 141 ti,hwmods = "gpio3";
128 gpio-controller; 142 gpio-controller;
129 #gpio-cells = <2>; 143 #gpio-cells = <2>;
@@ -133,6 +147,8 @@
133 147
134 gpio4: gpio@48059000 { 148 gpio4: gpio@48059000 {
135 compatible = "ti,omap4-gpio"; 149 compatible = "ti,omap4-gpio";
150 reg = <0x48059000 0x200>;
151 interrupts = <0 32 0x4>;
136 ti,hwmods = "gpio4"; 152 ti,hwmods = "gpio4";
137 gpio-controller; 153 gpio-controller;
138 #gpio-cells = <2>; 154 #gpio-cells = <2>;
@@ -142,6 +158,8 @@
142 158
143 gpio5: gpio@4805b000 { 159 gpio5: gpio@4805b000 {
144 compatible = "ti,omap4-gpio"; 160 compatible = "ti,omap4-gpio";
161 reg = <0x4805b000 0x200>;
162 interrupts = <0 33 0x4>;
145 ti,hwmods = "gpio5"; 163 ti,hwmods = "gpio5";
146 gpio-controller; 164 gpio-controller;
147 #gpio-cells = <2>; 165 #gpio-cells = <2>;
@@ -151,6 +169,8 @@
151 169
152 gpio6: gpio@4805d000 { 170 gpio6: gpio@4805d000 {
153 compatible = "ti,omap4-gpio"; 171 compatible = "ti,omap4-gpio";
172 reg = <0x4805d000 0x200>;
173 interrupts = <0 34 0x4>;
154 ti,hwmods = "gpio6"; 174 ti,hwmods = "gpio6";
155 gpio-controller; 175 gpio-controller;
156 #gpio-cells = <2>; 176 #gpio-cells = <2>;
@@ -160,30 +180,40 @@
160 180
161 uart1: serial@4806a000 { 181 uart1: serial@4806a000 {
162 compatible = "ti,omap4-uart"; 182 compatible = "ti,omap4-uart";
183 reg = <0x4806a000 0x100>;
184 interrupts = <0 72 0x4>;
163 ti,hwmods = "uart1"; 185 ti,hwmods = "uart1";
164 clock-frequency = <48000000>; 186 clock-frequency = <48000000>;
165 }; 187 };
166 188
167 uart2: serial@4806c000 { 189 uart2: serial@4806c000 {
168 compatible = "ti,omap4-uart"; 190 compatible = "ti,omap4-uart";
191 reg = <0x4806c000 0x100>;
192 interrupts = <0 73 0x4>;
169 ti,hwmods = "uart2"; 193 ti,hwmods = "uart2";
170 clock-frequency = <48000000>; 194 clock-frequency = <48000000>;
171 }; 195 };
172 196
173 uart3: serial@48020000 { 197 uart3: serial@48020000 {
174 compatible = "ti,omap4-uart"; 198 compatible = "ti,omap4-uart";
199 reg = <0x48020000 0x100>;
200 interrupts = <0 74 0x4>;
175 ti,hwmods = "uart3"; 201 ti,hwmods = "uart3";
176 clock-frequency = <48000000>; 202 clock-frequency = <48000000>;
177 }; 203 };
178 204
179 uart4: serial@4806e000 { 205 uart4: serial@4806e000 {
180 compatible = "ti,omap4-uart"; 206 compatible = "ti,omap4-uart";
207 reg = <0x4806e000 0x100>;
208 interrupts = <0 70 0x4>;
181 ti,hwmods = "uart4"; 209 ti,hwmods = "uart4";
182 clock-frequency = <48000000>; 210 clock-frequency = <48000000>;
183 }; 211 };
184 212
185 i2c1: i2c@48070000 { 213 i2c1: i2c@48070000 {
186 compatible = "ti,omap4-i2c"; 214 compatible = "ti,omap4-i2c";
215 reg = <0x48070000 0x100>;
216 interrupts = <0 56 0x4>;
187 #address-cells = <1>; 217 #address-cells = <1>;
188 #size-cells = <0>; 218 #size-cells = <0>;
189 ti,hwmods = "i2c1"; 219 ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
191 221
192 i2c2: i2c@48072000 { 222 i2c2: i2c@48072000 {
193 compatible = "ti,omap4-i2c"; 223 compatible = "ti,omap4-i2c";
224 reg = <0x48072000 0x100>;
225 interrupts = <0 57 0x4>;
194 #address-cells = <1>; 226 #address-cells = <1>;
195 #size-cells = <0>; 227 #size-cells = <0>;
196 ti,hwmods = "i2c2"; 228 ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
198 230
199 i2c3: i2c@48060000 { 231 i2c3: i2c@48060000 {
200 compatible = "ti,omap4-i2c"; 232 compatible = "ti,omap4-i2c";
233 reg = <0x48060000 0x100>;
234 interrupts = <0 61 0x4>;
201 #address-cells = <1>; 235 #address-cells = <1>;
202 #size-cells = <0>; 236 #size-cells = <0>;
203 ti,hwmods = "i2c3"; 237 ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
205 239
206 i2c4: i2c@48350000 { 240 i2c4: i2c@48350000 {
207 compatible = "ti,omap4-i2c"; 241 compatible = "ti,omap4-i2c";
242 reg = <0x48350000 0x100>;
243 interrupts = <0 62 0x4>;
208 #address-cells = <1>; 244 #address-cells = <1>;
209 #size-cells = <0>; 245 #size-cells = <0>;
210 ti,hwmods = "i2c4"; 246 ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
212 248
213 mcspi1: spi@48098000 { 249 mcspi1: spi@48098000 {
214 compatible = "ti,omap4-mcspi"; 250 compatible = "ti,omap4-mcspi";
251 reg = <0x48098000 0x200>;
252 interrupts = <0 65 0x4>;
215 #address-cells = <1>; 253 #address-cells = <1>;
216 #size-cells = <0>; 254 #size-cells = <0>;
217 ti,hwmods = "mcspi1"; 255 ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
220 258
221 mcspi2: spi@4809a000 { 259 mcspi2: spi@4809a000 {
222 compatible = "ti,omap4-mcspi"; 260 compatible = "ti,omap4-mcspi";
261 reg = <0x4809a000 0x200>;
262 interrupts = <0 66 0x4>;
223 #address-cells = <1>; 263 #address-cells = <1>;
224 #size-cells = <0>; 264 #size-cells = <0>;
225 ti,hwmods = "mcspi2"; 265 ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
228 268
229 mcspi3: spi@480b8000 { 269 mcspi3: spi@480b8000 {
230 compatible = "ti,omap4-mcspi"; 270 compatible = "ti,omap4-mcspi";
271 reg = <0x480b8000 0x200>;
272 interrupts = <0 91 0x4>;
231 #address-cells = <1>; 273 #address-cells = <1>;
232 #size-cells = <0>; 274 #size-cells = <0>;
233 ti,hwmods = "mcspi3"; 275 ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
236 278
237 mcspi4: spi@480ba000 { 279 mcspi4: spi@480ba000 {
238 compatible = "ti,omap4-mcspi"; 280 compatible = "ti,omap4-mcspi";
281 reg = <0x480ba000 0x200>;
282 interrupts = <0 48 0x4>;
239 #address-cells = <1>; 283 #address-cells = <1>;
240 #size-cells = <0>; 284 #size-cells = <0>;
241 ti,hwmods = "mcspi4"; 285 ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
244 288
245 mmc1: mmc@4809c000 { 289 mmc1: mmc@4809c000 {
246 compatible = "ti,omap4-hsmmc"; 290 compatible = "ti,omap4-hsmmc";
291 reg = <0x4809c000 0x400>;
292 interrupts = <0 83 0x4>;
247 ti,hwmods = "mmc1"; 293 ti,hwmods = "mmc1";
248 ti,dual-volt; 294 ti,dual-volt;
249 ti,needs-special-reset; 295 ti,needs-special-reset;
@@ -251,30 +297,40 @@
251 297
252 mmc2: mmc@480b4000 { 298 mmc2: mmc@480b4000 {
253 compatible = "ti,omap4-hsmmc"; 299 compatible = "ti,omap4-hsmmc";
300 reg = <0x480b4000 0x400>;
301 interrupts = <0 86 0x4>;
254 ti,hwmods = "mmc2"; 302 ti,hwmods = "mmc2";
255 ti,needs-special-reset; 303 ti,needs-special-reset;
256 }; 304 };
257 305
258 mmc3: mmc@480ad000 { 306 mmc3: mmc@480ad000 {
259 compatible = "ti,omap4-hsmmc"; 307 compatible = "ti,omap4-hsmmc";
308 reg = <0x480ad000 0x400>;
309 interrupts = <0 94 0x4>;
260 ti,hwmods = "mmc3"; 310 ti,hwmods = "mmc3";
261 ti,needs-special-reset; 311 ti,needs-special-reset;
262 }; 312 };
263 313
264 mmc4: mmc@480d1000 { 314 mmc4: mmc@480d1000 {
265 compatible = "ti,omap4-hsmmc"; 315 compatible = "ti,omap4-hsmmc";
316 reg = <0x480d1000 0x400>;
317 interrupts = <0 96 0x4>;
266 ti,hwmods = "mmc4"; 318 ti,hwmods = "mmc4";
267 ti,needs-special-reset; 319 ti,needs-special-reset;
268 }; 320 };
269 321
270 mmc5: mmc@480d5000 { 322 mmc5: mmc@480d5000 {
271 compatible = "ti,omap4-hsmmc"; 323 compatible = "ti,omap4-hsmmc";
324 reg = <0x480d5000 0x400>;
325 interrupts = <0 59 0x4>;
272 ti,hwmods = "mmc5"; 326 ti,hwmods = "mmc5";
273 ti,needs-special-reset; 327 ti,needs-special-reset;
274 }; 328 };
275 329
276 wdt2: wdt@4a314000 { 330 wdt2: wdt@4a314000 {
277 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 331 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
332 reg = <0x4a314000 0x80>;
333 interrupts = <0 80 0x4>;
278 ti,hwmods = "wd_timer2"; 334 ti,hwmods = "wd_timer2";
279 }; 335 };
280 336
@@ -282,6 +338,7 @@
282 compatible = "ti,omap4-mcpdm"; 338 compatible = "ti,omap4-mcpdm";
283 reg = <0x40132000 0x7f>, /* MPU private access */ 339 reg = <0x40132000 0x7f>, /* MPU private access */
284 <0x49032000 0x7f>; /* L3 Interconnect */ 340 <0x49032000 0x7f>; /* L3 Interconnect */
341 reg-names = "mpu", "dma";
285 interrupts = <0 112 0x4>; 342 interrupts = <0 112 0x4>;
286 interrupt-parent = <&gic>; 343 interrupt-parent = <&gic>;
287 ti,hwmods = "mcpdm"; 344 ti,hwmods = "mcpdm";
@@ -291,9 +348,87 @@
291 compatible = "ti,omap4-dmic"; 348 compatible = "ti,omap4-dmic";
292 reg = <0x4012e000 0x7f>, /* MPU private access */ 349 reg = <0x4012e000 0x7f>, /* MPU private access */
293 <0x4902e000 0x7f>; /* L3 Interconnect */ 350 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma";
294 interrupts = <0 114 0x4>; 352 interrupts = <0 114 0x4>;
295 interrupt-parent = <&gic>; 353 interrupt-parent = <&gic>;
296 ti,hwmods = "dmic"; 354 ti,hwmods = "dmic";
297 }; 355 };
356
357 mcbsp1: mcbsp@40122000 {
358 compatible = "ti,omap4-mcbsp";
359 reg = <0x40122000 0xff>, /* MPU private access */
360 <0x49022000 0xff>; /* L3 Interconnect */
361 reg-names = "mpu", "dma";
362 interrupts = <0 17 0x4>;
363 interrupt-names = "common";
364 interrupt-parent = <&gic>;
365 ti,buffer-size = <128>;
366 ti,hwmods = "mcbsp1";
367 };
368
369 mcbsp2: mcbsp@40124000 {
370 compatible = "ti,omap4-mcbsp";
371 reg = <0x40124000 0xff>, /* MPU private access */
372 <0x49024000 0xff>; /* L3 Interconnect */
373 reg-names = "mpu", "dma";
374 interrupts = <0 22 0x4>;
375 interrupt-names = "common";
376 interrupt-parent = <&gic>;
377 ti,buffer-size = <128>;
378 ti,hwmods = "mcbsp2";
379 };
380
381 mcbsp3: mcbsp@40126000 {
382 compatible = "ti,omap4-mcbsp";
383 reg = <0x40126000 0xff>, /* MPU private access */
384 <0x49026000 0xff>; /* L3 Interconnect */
385 reg-names = "mpu", "dma";
386 interrupts = <0 23 0x4>;
387 interrupt-names = "common";
388 interrupt-parent = <&gic>;
389 ti,buffer-size = <128>;
390 ti,hwmods = "mcbsp3";
391 };
392
393 mcbsp4: mcbsp@48096000 {
394 compatible = "ti,omap4-mcbsp";
395 reg = <0x48096000 0xff>; /* L4 Interconnect */
396 reg-names = "mpu";
397 interrupts = <0 16 0x4>;
398 interrupt-names = "common";
399 interrupt-parent = <&gic>;
400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4";
402 };
403
404 keypad: keypad@4a31c000 {
405 compatible = "ti,omap4-keypad";
406 reg = <0x4a31c000 0x80>;
407 interrupts = <0 120 0x4>;
408 reg-names = "mpu";
409 ti,hwmods = "kbd";
410 };
411
412 emif1: emif@4c000000 {
413 compatible = "ti,emif-4d";
414 reg = <0x4c000000 0x100>;
415 interrupts = <0 110 0x4>;
416 ti,hwmods = "emif1";
417 phy-type = <1>;
418 hw-caps-read-idle-ctrl;
419 hw-caps-ll-interface;
420 hw-caps-temp-alert;
421 };
422
423 emif2: emif@4d000000 {
424 compatible = "ti,emif-4d";
425 reg = <0x4d000000 0x100>;
426 interrupts = <0 111 0x4>;
427 ti,hwmods = "emif2";
428 phy-type = <1>;
429 hw-caps-read-idle-ctrl;
430 hw-caps-ll-interface;
431 hw-caps-temp-alert;
432 };
298 }; 433 };
299}; 434};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 18:25:54 -0500