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Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-wandboard.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi131
1 files changed, 118 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 35f547929167..bdfdf89d405f 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -12,17 +12,21 @@
12/ { 12/ {
13 regulators { 13 regulators {
14 compatible = "simple-bus"; 14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <0>;
15 17
16 reg_2p5v: 2p5v { 18 reg_2p5v: regulator@0 {
17 compatible = "regulator-fixed"; 19 compatible = "regulator-fixed";
20 reg = <0>;
18 regulator-name = "2P5V"; 21 regulator-name = "2P5V";
19 regulator-min-microvolt = <2500000>; 22 regulator-min-microvolt = <2500000>;
20 regulator-max-microvolt = <2500000>; 23 regulator-max-microvolt = <2500000>;
21 regulator-always-on; 24 regulator-always-on;
22 }; 25 };
23 26
24 reg_3p3v: 3p3v { 27 reg_3p3v: regulator@1 {
25 compatible = "regulator-fixed"; 28 compatible = "regulator-fixed";
29 reg = <1>;
26 regulator-name = "3P3V"; 30 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>; 31 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>;
@@ -54,14 +58,14 @@
54 58
55&audmux { 59&audmux {
56 pinctrl-names = "default"; 60 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_audmux_2>; 61 pinctrl-0 = <&pinctrl_audmux>;
58 status = "okay"; 62 status = "okay";
59}; 63};
60 64
61&i2c2 { 65&i2c2 {
62 clock-frequency = <100000>; 66 clock-frequency = <100000>;
63 pinctrl-names = "default"; 67 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_i2c2_2>; 68 pinctrl-0 = <&pinctrl_i2c2>;
65 status = "okay"; 69 status = "okay";
66 70
67 codec: sgtl5000@0a { 71 codec: sgtl5000@0a {
@@ -77,7 +81,7 @@
77 pinctrl-names = "default"; 81 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_hog>; 82 pinctrl-0 = <&pinctrl_hog>;
79 83
80 hog { 84 imx6qdl-wandboard {
81 pinctrl_hog: hoggrp { 85 pinctrl_hog: hoggrp {
82 fsl,pins = < 86 fsl,pins = <
83 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 87 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
@@ -91,20 +95,121 @@
91 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 95 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
92 >; 96 >;
93 }; 97 };
98
99 pinctrl_audmux: audmuxgrp {
100 fsl,pins = <
101 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
102 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
103 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
104 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
105 >;
106 };
107
108 pinctrl_enet: enetgrp {
109 fsl,pins = <
110 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
111 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
112 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
113 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
114 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
115 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
116 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
117 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
118 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
119 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
120 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
121 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
122 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
123 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
124 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
125 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
126 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
127 >;
128 };
129
130 pinctrl_i2c2: i2c2grp {
131 fsl,pins = <
132 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
133 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
134 >;
135 };
136
137 pinctrl_spdif: spdifgrp {
138 fsl,pins = <
139 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
140 >;
141 };
142
143 pinctrl_uart1: uart1grp {
144 fsl,pins = <
145 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
146 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
147 >;
148 };
149
150 pinctrl_uart3: uart3grp {
151 fsl,pins = <
152 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
153 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
154 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
155 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
156 >;
157 };
158
159 pinctrl_usbotg: usbotggrp {
160 fsl,pins = <
161 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
162 >;
163 };
164
165 pinctrl_usdhc1: usdhc1grp {
166 fsl,pins = <
167 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
168 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
169 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
170 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
171 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
172 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
173 >;
174 };
175
176 pinctrl_usdhc2: usdhc2grp {
177 fsl,pins = <
178 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
179 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
180 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
181 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
182 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
183 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
184 >;
185 };
186
187 pinctrl_usdhc3: usdhc3grp {
188 fsl,pins = <
189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
190 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
191 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
192 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
193 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
194 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
195 >;
196 };
94 }; 197 };
95}; 198};
96 199
97&fec { 200&fec {
98 pinctrl-names = "default"; 201 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_enet_1>; 202 pinctrl-0 = <&pinctrl_enet>;
100 phy-mode = "rgmii"; 203 phy-mode = "rgmii";
101 phy-reset-gpios = <&gpio3 29 0>; 204 phy-reset-gpios = <&gpio3 29 0>;
205 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
206 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
102 status = "okay"; 207 status = "okay";
103}; 208};
104 209
105&spdif { 210&spdif {
106 pinctrl-names = "default"; 211 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_spdif_3>; 212 pinctrl-0 = <&pinctrl_spdif>;
108 status = "okay"; 213 status = "okay";
109}; 214};
110 215
@@ -115,13 +220,13 @@
115 220
116&uart1 { 221&uart1 {
117 pinctrl-names = "default"; 222 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_uart1_1>; 223 pinctrl-0 = <&pinctrl_uart1>;
119 status = "okay"; 224 status = "okay";
120}; 225};
121 226
122&uart3 { 227&uart3 {
123 pinctrl-names = "default"; 228 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_uart3_2>; 229 pinctrl-0 = <&pinctrl_uart3>;
125 fsl,uart-has-rtscts; 230 fsl,uart-has-rtscts;
126 status = "okay"; 231 status = "okay";
127}; 232};
@@ -132,7 +237,7 @@
132 237
133&usbotg { 238&usbotg {
134 pinctrl-names = "default"; 239 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_usbotg_1>; 240 pinctrl-0 = <&pinctrl_usbotg>;
136 disable-over-current; 241 disable-over-current;
137 dr_mode = "peripheral"; 242 dr_mode = "peripheral";
138 status = "okay"; 243 status = "okay";
@@ -140,21 +245,21 @@
140 245
141&usdhc1 { 246&usdhc1 {
142 pinctrl-names = "default"; 247 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_usdhc1_2>; 248 pinctrl-0 = <&pinctrl_usdhc1>;
144 cd-gpios = <&gpio1 2 0>; 249 cd-gpios = <&gpio1 2 0>;
145 status = "okay"; 250 status = "okay";
146}; 251};
147 252
148&usdhc2 { 253&usdhc2 {
149 pinctrl-names = "default"; 254 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_usdhc2_2>; 255 pinctrl-0 = <&pinctrl_usdhc2>;
151 non-removable; 256 non-removable;
152 status = "okay"; 257 status = "okay";
153}; 258};
154 259
155&usdhc3 { 260&usdhc3 {
156 pinctrl-names = "default"; 261 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_usdhc3_2>; 262 pinctrl-0 = <&pinctrl_usdhc3>;
158 cd-gpios = <&gpio3 9 0>; 263 cd-gpios = <&gpio3 9 0>;
159 status = "okay"; 264 status = "okay";
160}; 265};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 06:32:05 -0500