diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6dl.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6dl.dtsi | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 5bcdf3a90bb3..2b3ecd679350 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi | |||
| @@ -18,12 +18,14 @@ | |||
| 18 | 18 | ||
| 19 | cpu@0 { | 19 | cpu@0 { |
| 20 | compatible = "arm,cortex-a9"; | 20 | compatible = "arm,cortex-a9"; |
| 21 | device_type = "cpu"; | ||
| 21 | reg = <0>; | 22 | reg = <0>; |
| 22 | next-level-cache = <&L2>; | 23 | next-level-cache = <&L2>; |
| 23 | }; | 24 | }; |
| 24 | 25 | ||
| 25 | cpu@1 { | 26 | cpu@1 { |
| 26 | compatible = "arm,cortex-a9"; | 27 | compatible = "arm,cortex-a9"; |
| 28 | device_type = "cpu"; | ||
| 27 | reg = <1>; | 29 | reg = <1>; |
| 28 | next-level-cache = <&L2>; | 30 | next-level-cache = <&L2>; |
| 29 | }; | 31 | }; |
| @@ -35,6 +37,27 @@ | |||
| 35 | compatible = "fsl,imx6dl-iomuxc"; | 37 | compatible = "fsl,imx6dl-iomuxc"; |
| 36 | reg = <0x020e0000 0x4000>; | 38 | reg = <0x020e0000 0x4000>; |
| 37 | 39 | ||
| 40 | audmux { | ||
| 41 | pinctrl_audmux_2: audmux-2 { | ||
| 42 | fsl,pins = < | ||
| 43 | MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000 | ||
| 44 | MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000 | ||
| 45 | MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000 | ||
| 46 | MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000 | ||
| 47 | >; | ||
| 48 | }; | ||
| 49 | }; | ||
| 50 | |||
| 51 | ecspi1 { | ||
| 52 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
| 53 | fsl,pins = < | ||
| 54 | MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 | ||
| 55 | MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 | ||
| 56 | MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 | ||
| 57 | >; | ||
| 58 | }; | ||
| 59 | }; | ||
| 60 | |||
| 38 | enet { | 61 | enet { |
| 39 | pinctrl_enet_1: enetgrp-1 { | 62 | pinctrl_enet_1: enetgrp-1 { |
| 40 | fsl,pins = < | 63 | fsl,pins = < |
| @@ -78,6 +101,39 @@ | |||
| 78 | }; | 101 | }; |
| 79 | }; | 102 | }; |
| 80 | 103 | ||
| 104 | gpmi-nand { | ||
| 105 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
| 106 | fsl,pins = < | ||
| 107 | MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 | ||
| 108 | MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 | ||
| 109 | MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 | ||
| 110 | MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000 | ||
| 111 | MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 | ||
| 112 | MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 | ||
| 113 | MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 | ||
| 114 | MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 | ||
| 115 | MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 | ||
| 116 | MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 | ||
| 117 | MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 | ||
| 118 | MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 | ||
| 119 | MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 | ||
| 120 | MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 | ||
| 121 | MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 | ||
| 122 | MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 | ||
| 123 | MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1 | ||
| 124 | >; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | |||
| 128 | i2c1 { | ||
| 129 | pinctrl_i2c1_2: i2c1grp-2 { | ||
| 130 | fsl,pins = < | ||
| 131 | MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 | ||
| 132 | MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 | ||
| 133 | >; | ||
| 134 | }; | ||
| 135 | }; | ||
| 136 | |||
| 81 | uart1 { | 137 | uart1 { |
| 82 | pinctrl_uart1_1: uart1grp-1 { | 138 | pinctrl_uart1_1: uart1grp-1 { |
| 83 | fsl,pins = < | 139 | fsl,pins = < |
| @@ -149,6 +205,64 @@ | |||
| 149 | }; | 205 | }; |
| 150 | }; | 206 | }; |
| 151 | 207 | ||
| 208 | weim { | ||
| 209 | pinctrl_weim_cs0_1: weim_cs0grp-1 { | ||
| 210 | fsl,pins = < | ||
| 211 | MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 | ||
| 212 | >; | ||
| 213 | }; | ||
| 214 | |||
| 215 | pinctrl_weim_nor_1: weim_norgrp-1 { | ||
| 216 | fsl,pins = < | ||
| 217 | MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1 | ||
| 218 | MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1 | ||
| 219 | MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 | ||
| 220 | /* data */ | ||
| 221 | MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 | ||
| 222 | MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 | ||
| 223 | MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 | ||
| 224 | MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 | ||
| 225 | MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 | ||
| 226 | MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 | ||
| 227 | MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 | ||
| 228 | MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 | ||
| 229 | MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 | ||
| 230 | MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 | ||
| 231 | MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 | ||
| 232 | MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 | ||
| 233 | MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 | ||
| 234 | MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 | ||
| 235 | MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 | ||
| 236 | MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 | ||
| 237 | /* address */ | ||
| 238 | MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 | ||
| 239 | MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 | ||
| 240 | MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 | ||
| 241 | MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 | ||
| 242 | MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 | ||
| 243 | MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 | ||
| 244 | MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 | ||
| 245 | MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 | ||
| 246 | MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1 | ||
| 247 | MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1 | ||
| 248 | MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1 | ||
| 249 | MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1 | ||
| 250 | MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1 | ||
| 251 | MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1 | ||
| 252 | MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1 | ||
| 253 | MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1 | ||
| 254 | MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1 | ||
| 255 | MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1 | ||
| 256 | MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1 | ||
| 257 | MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1 | ||
| 258 | MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1 | ||
| 259 | MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1 | ||
| 260 | MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1 | ||
| 261 | MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1 | ||
| 262 | >; | ||
| 263 | }; | ||
| 264 | |||
| 265 | }; | ||
| 152 | 266 | ||
| 153 | }; | 267 | }; |
| 154 | 268 | ||