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-rw-r--r--arch/arm/boot/dts/imx53.dtsi297
1 files changed, 296 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index eb83aa039b8b..3895fbba8fce 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -27,6 +27,9 @@
27 gpio4 = &gpio5; 27 gpio4 = &gpio5;
28 gpio5 = &gpio6; 28 gpio5 = &gpio6;
29 gpio6 = &gpio7; 29 gpio6 = &gpio7;
30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
30 }; 33 };
31 34
32 tzic: tz-interrupt-controller@0fffc000 { 35 tzic: tz-interrupt-controller@0fffc000 {
@@ -163,10 +166,27 @@
163 }; 166 };
164 }; 167 };
165 168
169 usbphy0: usbphy@0 {
170 compatible = "usb-nop-xceiv";
171 clocks = <&clks 124>;
172 clock-names = "main_clk";
173 status = "okay";
174 };
175
176 usbphy1: usbphy@1 {
177 compatible = "usb-nop-xceiv";
178 clocks = <&clks 125>;
179 clock-names = "main_clk";
180 status = "okay";
181 };
182
166 usbotg: usb@53f80000 { 183 usbotg: usb@53f80000 {
167 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
168 reg = <0x53f80000 0x0200>; 185 reg = <0x53f80000 0x0200>;
169 interrupts = <18>; 186 interrupts = <18>;
187 clocks = <&clks 108>;
188 fsl,usbmisc = <&usbmisc 0>;
189 fsl,usbphy = <&usbphy0>;
170 status = "disabled"; 190 status = "disabled";
171 }; 191 };
172 192
@@ -174,6 +194,9 @@
174 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 194 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
175 reg = <0x53f80200 0x0200>; 195 reg = <0x53f80200 0x0200>;
176 interrupts = <14>; 196 interrupts = <14>;
197 clocks = <&clks 108>;
198 fsl,usbmisc = <&usbmisc 1>;
199 fsl,usbphy = <&usbphy1>;
177 status = "disabled"; 200 status = "disabled";
178 }; 201 };
179 202
@@ -181,6 +204,8 @@
181 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 204 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
182 reg = <0x53f80400 0x0200>; 205 reg = <0x53f80400 0x0200>;
183 interrupts = <16>; 206 interrupts = <16>;
207 clocks = <&clks 108>;
208 fsl,usbmisc = <&usbmisc 2>;
184 status = "disabled"; 209 status = "disabled";
185 }; 210 };
186 211
@@ -188,9 +213,18 @@
188 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 213 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
189 reg = <0x53f80600 0x0200>; 214 reg = <0x53f80600 0x0200>;
190 interrupts = <17>; 215 interrupts = <17>;
216 clocks = <&clks 108>;
217 fsl,usbmisc = <&usbmisc 3>;
191 status = "disabled"; 218 status = "disabled";
192 }; 219 };
193 220
221 usbmisc: usbmisc@53f80800 {
222 #index-cells = <1>;
223 compatible = "fsl,imx53-usbmisc";
224 reg = <0x53f80800 0x200>;
225 clocks = <&clks 108>;
226 };
227
194 gpio1: gpio@53f84000 { 228 gpio1: gpio@53f84000 {
195 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 229 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
196 reg = <0x53f84000 0x4000>; 230 reg = <0x53f84000 0x4000>;
@@ -267,6 +301,24 @@
267 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 301 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
268 >; 302 >;
269 }; 303 };
304
305 pinctrl_audmux_2: audmuxgrp-2 {
306 fsl,pins = <
307 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
308 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
309 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
310 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
311 >;
312 };
313
314 pinctrl_audmux_3: audmuxgrp-3 {
315 fsl,pins = <
316 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
317 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
318 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
319 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
320 >;
321 };
270 }; 322 };
271 323
272 fec { 324 fec {
@@ -284,6 +336,29 @@
284 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 336 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
285 >; 337 >;
286 }; 338 };
339
340 pinctrl_fec_2: fecgrp-2 {
341 fsl,pins = <
342 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
343 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
344 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
345 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
346 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
347 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
348 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
349 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
350 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
351 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
352 MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
353 MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
354 MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
355 MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
356 MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
357 MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
358 MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
359 MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
360 >;
361 };
287 }; 362 };
288 363
289 csi { 364 csi {
@@ -312,6 +387,22 @@
312 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 387 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
313 >; 388 >;
314 }; 389 };
390
391 pinctrl_csi_2: csigrp-2 {
392 fsl,pins = <
393 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
394 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
395 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
396 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
397 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
398 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
399 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
400 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
401 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
402 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
403 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
404 >;
405 };
315 }; 406 };
316 407
317 cspi { 408 cspi {
@@ -322,6 +413,14 @@
322 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 413 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
323 >; 414 >;
324 }; 415 };
416
417 pinctrl_cspi_2: cspigrp-2 {
418 fsl,pins = <
419 MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
420 MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
421 MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
422 >;
423 };
325 }; 424 };
326 425
327 ecspi1 { 426 ecspi1 {
@@ -332,6 +431,27 @@
332 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 431 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
333 >; 432 >;
334 }; 433 };
434
435 pinctrl_ecspi1_2: ecspi1grp-2 {
436 fsl,pins = <
437 MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
438 MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
439 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
440 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
441 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
442 MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
443 >;
444 };
445 };
446
447 ecspi2 {
448 pinctrl_ecspi2_1: ecspi2grp-1 {
449 fsl,pins = <
450 MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
451 MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
452 MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
453 >;
454 };
335 }; 455 };
336 456
337 esdhc1 { 457 esdhc1 {
@@ -406,6 +526,13 @@
406 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 526 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
407 >; 527 >;
408 }; 528 };
529
530 pinctrl_can1_3: can1grp-3 {
531 fsl,pins = <
532 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
533 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
534 >;
535 };
409 }; 536 };
410 537
411 can2 { 538 can2 {
@@ -424,6 +551,13 @@
424 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 551 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
425 >; 552 >;
426 }; 553 };
554
555 pinctrl_i2c1_2: i2c1grp-2 {
556 fsl,pins = <
557 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
558 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
559 >;
560 };
427 }; 561 };
428 562
429 i2c2 { 563 i2c2 {
@@ -433,6 +567,13 @@
433 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 567 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
434 >; 568 >;
435 }; 569 };
570
571 pinctrl_i2c2_2: i2c2grp-2 {
572 fsl,pins = <
573 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
574 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
575 >;
576 };
436 }; 577 };
437 578
438 i2c3 { 579 i2c3 {
@@ -444,6 +585,119 @@
444 }; 585 };
445 }; 586 };
446 587
588 ipu_disp0 {
589 pinctrl_ipu_disp0_1: ipudisp0grp-1 {
590 fsl,pins = <
591 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
592 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
593 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
594 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
595 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
596 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
597 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
598 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
599 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
600 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
601 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
602 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
603 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
604 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
605 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
606 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
607 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
608 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
609 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
610 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
611 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
612 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
613 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
614 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
615 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
616 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
617 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
618 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
619 >;
620 };
621 };
622
623 ipu_disp1 {
624 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
625 fsl,pins = <
626 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
627 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
628 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
629 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
630 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
631 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
632 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
633 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
634 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
635 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
636 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
637 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
638 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
639 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
640 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
641 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
642 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
643 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
644 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
645 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
646 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
647 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
648 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
649 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
650 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
651 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
652 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
653 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
654 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
655 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
656 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
657 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
658 >;
659 };
660 };
661
662 ipu_disp2 {
663 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
664 fsl,pins = <
665 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
666 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
667 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
668 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
669 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
670 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
671 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
672 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
673 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
674 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
675 >;
676 };
677 };
678
679 nand {
680 pinctrl_nand_1: nandgrp-1 {
681 fsl,pins = <
682 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
683 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
684 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
685 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
686 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
687 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
688 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
689 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
690 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
691 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
692 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
693 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
694 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
695 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
696 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
697 >;
698 };
699 };
700
447 owire { 701 owire {
448 pinctrl_owire_1: owiregrp-1 { 702 pinctrl_owire_1: owiregrp-1 {
449 fsl,pins = < 703 fsl,pins = <
@@ -452,6 +706,22 @@
452 }; 706 };
453 }; 707 };
454 708
709 pwm1 {
710 pinctrl_pwm1_1: pwm1grp-1 {
711 fsl,pins = <
712 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
713 >;
714 };
715 };
716
717 pwm2 {
718 pinctrl_pwm2_1: pwm2grp-1 {
719 fsl,pins = <
720 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
721 >;
722 };
723 };
724
455 uart1 { 725 uart1 {
456 pinctrl_uart1_1: uart1grp-1 { 726 pinctrl_uart1_1: uart1grp-1 {
457 fsl,pins = < 727 fsl,pins = <
@@ -466,6 +736,13 @@
466 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 736 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
467 >; 737 >;
468 }; 738 };
739
740 pinctrl_uart1_3: uart1grp-3 {
741 fsl,pins = <
742 MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
743 MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
744 >;
745 };
469 }; 746 };
470 747
471 uart2 { 748 uart2 {
@@ -475,6 +752,15 @@
475 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 752 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
476 >; 753 >;
477 }; 754 };
755
756 pinctrl_uart2_2: uart2grp-2 {
757 fsl,pins = <
758 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
759 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
760 MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
761 MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
762 >;
763 };
478 }; 764 };
479 765
480 uart3 { 766 uart3 {
@@ -513,7 +799,6 @@
513 >; 799 >;
514 }; 800 };
515 }; 801 };
516
517 }; 802 };
518 803
519 gpr: iomuxc-gpr@53fa8000 { 804 gpr: iomuxc-gpr@53fa8000 {
@@ -781,6 +1066,16 @@
781 clock-names = "ipg", "ahb", "ptp"; 1066 clock-names = "ipg", "ahb", "ptp";
782 status = "disabled"; 1067 status = "disabled";
783 }; 1068 };
1069
1070 tve: tve@63ff0000 {
1071 compatible = "fsl,imx53-tve";
1072 reg = <0x63ff0000 0x1000>;
1073 interrupts = <92>;
1074 clocks = <&clks 69>, <&clks 116>;
1075 clock-names = "tve", "di_sel";
1076 crtcs = <&ipu 1>;
1077 status = "disabled";
1078 };
784 }; 1079 };
785 }; 1080 };
786}; 1081};
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 03:28:05 -0400