aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx51.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/imx51.dtsi')
-rw-r--r--arch/arm/boot/dts/imx51.dtsi481
1 files changed, 107 insertions, 374 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 4bcdd3ad15e5..5f8216d08f6b 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -12,6 +12,10 @@
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14#include "imx51-pinfunc.h" 14#include "imx51-pinfunc.h"
15#include <dt-bindings/clock/imx5-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
15 19
16/ { 20/ {
17 aliases { 21 aliases {
@@ -21,6 +25,10 @@
21 gpio3 = &gpio4; 25 gpio3 = &gpio4;
22 i2c0 = &i2c1; 26 i2c0 = &i2c1;
23 i2c1 = &i2c2; 27 i2c1 = &i2c2;
28 mmc0 = &esdhc1;
29 mmc1 = &esdhc2;
30 mmc2 = &esdhc3;
31 mmc3 = &esdhc4;
24 serial0 = &uart1; 32 serial0 = &uart1;
25 serial1 = &uart2; 33 serial1 = &uart2;
26 serial2 = &uart3; 34 serial2 = &uart3;
@@ -64,21 +72,40 @@
64 cpus { 72 cpus {
65 #address-cells = <1>; 73 #address-cells = <1>;
66 #size-cells = <0>; 74 #size-cells = <0>;
67 cpu@0 { 75 cpu: cpu@0 {
68 device_type = "cpu"; 76 device_type = "cpu";
69 compatible = "arm,cortex-a8"; 77 compatible = "arm,cortex-a8";
70 reg = <0>; 78 reg = <0>;
71 clock-latency = <61036>; /* two CLK32 periods */ 79 clock-latency = <62500>;
72 clocks = <&clks 24>; 80 clocks = <&clks IMX5_CLK_CPU_PODF>;
73 clock-names = "cpu"; 81 clock-names = "cpu";
74 operating-points = < 82 operating-points = <
75 /* kHz uV (No regulator support) */ 83 166000 1000000
76 160000 0 84 600000 1050000
77 800000 0 85 800000 1100000
78 >; 86 >;
87 voltage-tolerance = <5>;
79 }; 88 };
80 }; 89 };
81 90
91 usbphy {
92 #address-cells = <1>;
93 #size-cells = <0>;
94 compatible = "simple-bus";
95
96 usbphy0: usbphy@0 {
97 compatible = "usb-nop-xceiv";
98 reg = <0>;
99 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
100 clock-names = "main_clk";
101 };
102 };
103
104 display-subsystem {
105 compatible = "fsl,imx-display-subsystem";
106 ports = <&ipu_di0>, <&ipu_di1>;
107 };
108
82 soc { 109 soc {
83 #address-cells = <1>; 110 #address-cells = <1>;
84 #size-cells = <1>; 111 #size-cells = <1>;
@@ -92,13 +119,30 @@
92 }; 119 };
93 120
94 ipu: ipu@40000000 { 121 ipu: ipu@40000000 {
95 #crtc-cells = <1>; 122 #address-cells = <1>;
123 #size-cells = <0>;
96 compatible = "fsl,imx51-ipu"; 124 compatible = "fsl,imx51-ipu";
97 reg = <0x40000000 0x20000000>; 125 reg = <0x40000000 0x20000000>;
98 interrupts = <11 10>; 126 interrupts = <11 10>;
99 clocks = <&clks 59>, <&clks 110>, <&clks 61>; 127 clocks = <&clks IMX5_CLK_IPU_GATE>,
128 <&clks IMX5_CLK_IPU_DI0_GATE>,
129 <&clks IMX5_CLK_IPU_DI1_GATE>;
100 clock-names = "bus", "di0", "di1"; 130 clock-names = "bus", "di0", "di1";
101 resets = <&src 2>; 131 resets = <&src 2>;
132
133 ipu_di0: port@2 {
134 reg = <2>;
135
136 ipu_di0_disp0: endpoint {
137 };
138 };
139
140 ipu_di1: port@3 {
141 reg = <3>;
142
143 ipu_di1_disp1: endpoint {
144 };
145 };
102 }; 146 };
103 147
104 aips@70000000 { /* AIPS1 */ 148 aips@70000000 { /* AIPS1 */
@@ -119,7 +163,9 @@
119 compatible = "fsl,imx51-esdhc"; 163 compatible = "fsl,imx51-esdhc";
120 reg = <0x70004000 0x4000>; 164 reg = <0x70004000 0x4000>;
121 interrupts = <1>; 165 interrupts = <1>;
122 clocks = <&clks 44>, <&clks 0>, <&clks 71>; 166 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
167 <&clks IMX5_CLK_DUMMY>,
168 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
123 clock-names = "ipg", "ahb", "per"; 169 clock-names = "ipg", "ahb", "per";
124 status = "disabled"; 170 status = "disabled";
125 }; 171 };
@@ -128,7 +174,9 @@
128 compatible = "fsl,imx51-esdhc"; 174 compatible = "fsl,imx51-esdhc";
129 reg = <0x70008000 0x4000>; 175 reg = <0x70008000 0x4000>;
130 interrupts = <2>; 176 interrupts = <2>;
131 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 177 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
178 <&clks IMX5_CLK_DUMMY>,
179 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
132 clock-names = "ipg", "ahb", "per"; 180 clock-names = "ipg", "ahb", "per";
133 bus-width = <4>; 181 bus-width = <4>;
134 status = "disabled"; 182 status = "disabled";
@@ -138,7 +186,8 @@
138 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 186 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
139 reg = <0x7000c000 0x4000>; 187 reg = <0x7000c000 0x4000>;
140 interrupts = <33>; 188 interrupts = <33>;
141 clocks = <&clks 32>, <&clks 33>; 189 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
190 <&clks IMX5_CLK_UART3_PER_GATE>;
142 clock-names = "ipg", "per"; 191 clock-names = "ipg", "per";
143 status = "disabled"; 192 status = "disabled";
144 }; 193 };
@@ -149,7 +198,8 @@
149 compatible = "fsl,imx51-ecspi"; 198 compatible = "fsl,imx51-ecspi";
150 reg = <0x70010000 0x4000>; 199 reg = <0x70010000 0x4000>;
151 interrupts = <36>; 200 interrupts = <36>;
152 clocks = <&clks 51>, <&clks 52>; 201 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
202 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
153 clock-names = "ipg", "per"; 203 clock-names = "ipg", "per";
154 status = "disabled"; 204 status = "disabled";
155 }; 205 };
@@ -158,7 +208,7 @@
158 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 208 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
159 reg = <0x70014000 0x4000>; 209 reg = <0x70014000 0x4000>;
160 interrupts = <30>; 210 interrupts = <30>;
161 clocks = <&clks 49>; 211 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
162 dmas = <&sdma 24 1 0>, 212 dmas = <&sdma 24 1 0>,
163 <&sdma 25 1 0>; 213 <&sdma 25 1 0>;
164 dma-names = "rx", "tx"; 214 dma-names = "rx", "tx";
@@ -171,7 +221,9 @@
171 compatible = "fsl,imx51-esdhc"; 221 compatible = "fsl,imx51-esdhc";
172 reg = <0x70020000 0x4000>; 222 reg = <0x70020000 0x4000>;
173 interrupts = <3>; 223 interrupts = <3>;
174 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 224 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
225 <&clks IMX5_CLK_DUMMY>,
226 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
175 clock-names = "ipg", "ahb", "per"; 227 clock-names = "ipg", "ahb", "per";
176 bus-width = <4>; 228 bus-width = <4>;
177 status = "disabled"; 229 status = "disabled";
@@ -181,25 +233,20 @@
181 compatible = "fsl,imx51-esdhc"; 233 compatible = "fsl,imx51-esdhc";
182 reg = <0x70024000 0x4000>; 234 reg = <0x70024000 0x4000>;
183 interrupts = <4>; 235 interrupts = <4>;
184 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 236 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
237 <&clks IMX5_CLK_DUMMY>,
238 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
185 clock-names = "ipg", "ahb", "per"; 239 clock-names = "ipg", "ahb", "per";
186 bus-width = <4>; 240 bus-width = <4>;
187 status = "disabled"; 241 status = "disabled";
188 }; 242 };
189 }; 243 };
190 244
191 usbphy0: usbphy@0 {
192 compatible = "usb-nop-xceiv";
193 clocks = <&clks 75>;
194 clock-names = "main_clk";
195 status = "okay";
196 };
197
198 usbotg: usb@73f80000 { 245 usbotg: usb@73f80000 {
199 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 246 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
200 reg = <0x73f80000 0x0200>; 247 reg = <0x73f80000 0x0200>;
201 interrupts = <18>; 248 interrupts = <18>;
202 clocks = <&clks 108>; 249 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
203 fsl,usbmisc = <&usbmisc 0>; 250 fsl,usbmisc = <&usbmisc 0>;
204 fsl,usbphy = <&usbphy0>; 251 fsl,usbphy = <&usbphy0>;
205 status = "disabled"; 252 status = "disabled";
@@ -209,7 +256,7 @@
209 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 256 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
210 reg = <0x73f80200 0x0200>; 257 reg = <0x73f80200 0x0200>;
211 interrupts = <14>; 258 interrupts = <14>;
212 clocks = <&clks 108>; 259 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
213 fsl,usbmisc = <&usbmisc 1>; 260 fsl,usbmisc = <&usbmisc 1>;
214 status = "disabled"; 261 status = "disabled";
215 }; 262 };
@@ -218,7 +265,7 @@
218 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 265 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
219 reg = <0x73f80400 0x0200>; 266 reg = <0x73f80400 0x0200>;
220 interrupts = <16>; 267 interrupts = <16>;
221 clocks = <&clks 108>; 268 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
222 fsl,usbmisc = <&usbmisc 2>; 269 fsl,usbmisc = <&usbmisc 2>;
223 status = "disabled"; 270 status = "disabled";
224 }; 271 };
@@ -227,7 +274,7 @@
227 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 274 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
228 reg = <0x73f80600 0x0200>; 275 reg = <0x73f80600 0x0200>;
229 interrupts = <17>; 276 interrupts = <17>;
230 clocks = <&clks 108>; 277 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
231 fsl,usbmisc = <&usbmisc 3>; 278 fsl,usbmisc = <&usbmisc 3>;
232 status = "disabled"; 279 status = "disabled";
233 }; 280 };
@@ -236,7 +283,7 @@
236 #index-cells = <1>; 283 #index-cells = <1>;
237 compatible = "fsl,imx51-usbmisc"; 284 compatible = "fsl,imx51-usbmisc";
238 reg = <0x73f80800 0x200>; 285 reg = <0x73f80800 0x200>;
239 clocks = <&clks 108>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
240 }; 287 };
241 288
242 gpio1: gpio@73f84000 { 289 gpio1: gpio@73f84000 {
@@ -283,7 +330,7 @@
283 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 330 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
284 reg = <0x73f94000 0x4000>; 331 reg = <0x73f94000 0x4000>;
285 interrupts = <60>; 332 interrupts = <60>;
286 clocks = <&clks 0>; 333 clocks = <&clks IMX5_CLK_DUMMY>;
287 status = "disabled"; 334 status = "disabled";
288 }; 335 };
289 336
@@ -291,14 +338,14 @@
291 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 338 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
292 reg = <0x73f98000 0x4000>; 339 reg = <0x73f98000 0x4000>;
293 interrupts = <58>; 340 interrupts = <58>;
294 clocks = <&clks 0>; 341 clocks = <&clks IMX5_CLK_DUMMY>;
295 }; 342 };
296 343
297 wdog2: wdog@73f9c000 { 344 wdog2: wdog@73f9c000 {
298 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 345 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
299 reg = <0x73f9c000 0x4000>; 346 reg = <0x73f9c000 0x4000>;
300 interrupts = <59>; 347 interrupts = <59>;
301 clocks = <&clks 0>; 348 clocks = <&clks IMX5_CLK_DUMMY>;
302 status = "disabled"; 349 status = "disabled";
303 }; 350 };
304 351
@@ -306,7 +353,8 @@
306 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 353 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
307 reg = <0x73fa0000 0x4000>; 354 reg = <0x73fa0000 0x4000>;
308 interrupts = <39>; 355 interrupts = <39>;
309 clocks = <&clks 36>, <&clks 41>; 356 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
357 <&clks IMX5_CLK_GPT_HF_GATE>;
310 clock-names = "ipg", "per"; 358 clock-names = "ipg", "per";
311 }; 359 };
312 360
@@ -319,7 +367,8 @@
319 #pwm-cells = <2>; 367 #pwm-cells = <2>;
320 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 368 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
321 reg = <0x73fb4000 0x4000>; 369 reg = <0x73fb4000 0x4000>;
322 clocks = <&clks 37>, <&clks 38>; 370 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
371 <&clks IMX5_CLK_PWM1_HF_GATE>;
323 clock-names = "ipg", "per"; 372 clock-names = "ipg", "per";
324 interrupts = <61>; 373 interrupts = <61>;
325 }; 374 };
@@ -328,7 +377,8 @@
328 #pwm-cells = <2>; 377 #pwm-cells = <2>;
329 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 378 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
330 reg = <0x73fb8000 0x4000>; 379 reg = <0x73fb8000 0x4000>;
331 clocks = <&clks 39>, <&clks 40>; 380 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
381 <&clks IMX5_CLK_PWM2_HF_GATE>;
332 clock-names = "ipg", "per"; 382 clock-names = "ipg", "per";
333 interrupts = <94>; 383 interrupts = <94>;
334 }; 384 };
@@ -337,7 +387,8 @@
337 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 387 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
338 reg = <0x73fbc000 0x4000>; 388 reg = <0x73fbc000 0x4000>;
339 interrupts = <31>; 389 interrupts = <31>;
340 clocks = <&clks 28>, <&clks 29>; 390 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
391 <&clks IMX5_CLK_UART1_PER_GATE>;
341 clock-names = "ipg", "per"; 392 clock-names = "ipg", "per";
342 status = "disabled"; 393 status = "disabled";
343 }; 394 };
@@ -346,7 +397,8 @@
346 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 397 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
347 reg = <0x73fc0000 0x4000>; 398 reg = <0x73fc0000 0x4000>;
348 interrupts = <32>; 399 interrupts = <32>;
349 clocks = <&clks 30>, <&clks 31>; 400 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
401 <&clks IMX5_CLK_UART2_PER_GATE>;
350 clock-names = "ipg", "per"; 402 clock-names = "ipg", "per";
351 status = "disabled"; 403 status = "disabled";
352 }; 404 };
@@ -376,14 +428,14 @@
376 compatible = "fsl,imx51-iim", "fsl,imx27-iim"; 428 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
377 reg = <0x83f98000 0x4000>; 429 reg = <0x83f98000 0x4000>;
378 interrupts = <69>; 430 interrupts = <69>;
379 clocks = <&clks 107>; 431 clocks = <&clks IMX5_CLK_IIM_GATE>;
380 }; 432 };
381 433
382 owire: owire@83fa4000 { 434 owire: owire@83fa4000 {
383 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 435 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
384 reg = <0x83fa4000 0x4000>; 436 reg = <0x83fa4000 0x4000>;
385 interrupts = <88>; 437 interrupts = <88>;
386 clocks = <&clks 159>; 438 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
387 status = "disabled"; 439 status = "disabled";
388 }; 440 };
389 441
@@ -393,7 +445,8 @@
393 compatible = "fsl,imx51-ecspi"; 445 compatible = "fsl,imx51-ecspi";
394 reg = <0x83fac000 0x4000>; 446 reg = <0x83fac000 0x4000>;
395 interrupts = <37>; 447 interrupts = <37>;
396 clocks = <&clks 53>, <&clks 54>; 448 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
449 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
397 clock-names = "ipg", "per"; 450 clock-names = "ipg", "per";
398 status = "disabled"; 451 status = "disabled";
399 }; 452 };
@@ -402,7 +455,8 @@
402 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 455 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
403 reg = <0x83fb0000 0x4000>; 456 reg = <0x83fb0000 0x4000>;
404 interrupts = <6>; 457 interrupts = <6>;
405 clocks = <&clks 56>, <&clks 56>; 458 clocks = <&clks IMX5_CLK_SDMA_GATE>,
459 <&clks IMX5_CLK_SDMA_GATE>;
406 clock-names = "ipg", "ahb"; 460 clock-names = "ipg", "ahb";
407 #dma-cells = <3>; 461 #dma-cells = <3>;
408 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 462 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
@@ -414,7 +468,8 @@
414 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 468 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
415 reg = <0x83fc0000 0x4000>; 469 reg = <0x83fc0000 0x4000>;
416 interrupts = <38>; 470 interrupts = <38>;
417 clocks = <&clks 55>, <&clks 55>; 471 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
472 <&clks IMX5_CLK_CSPI_IPG_GATE>;
418 clock-names = "ipg", "per"; 473 clock-names = "ipg", "per";
419 status = "disabled"; 474 status = "disabled";
420 }; 475 };
@@ -425,7 +480,7 @@
425 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 480 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
426 reg = <0x83fc4000 0x4000>; 481 reg = <0x83fc4000 0x4000>;
427 interrupts = <63>; 482 interrupts = <63>;
428 clocks = <&clks 35>; 483 clocks = <&clks IMX5_CLK_I2C2_GATE>;
429 status = "disabled"; 484 status = "disabled";
430 }; 485 };
431 486
@@ -435,7 +490,7 @@
435 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 490 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
436 reg = <0x83fc8000 0x4000>; 491 reg = <0x83fc8000 0x4000>;
437 interrupts = <62>; 492 interrupts = <62>;
438 clocks = <&clks 34>; 493 clocks = <&clks IMX5_CLK_I2C1_GATE>;
439 status = "disabled"; 494 status = "disabled";
440 }; 495 };
441 496
@@ -443,7 +498,7 @@
443 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 498 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
444 reg = <0x83fcc000 0x4000>; 499 reg = <0x83fcc000 0x4000>;
445 interrupts = <29>; 500 interrupts = <29>;
446 clocks = <&clks 48>; 501 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
447 dmas = <&sdma 28 0 0>, 502 dmas = <&sdma 28 0 0>,
448 <&sdma 29 0 0>; 503 <&sdma 29 0 0>;
449 dma-names = "rx", "tx"; 504 dma-names = "rx", "tx";
@@ -455,6 +510,8 @@
455 audmux: audmux@83fd0000 { 510 audmux: audmux@83fd0000 {
456 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 511 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
457 reg = <0x83fd0000 0x4000>; 512 reg = <0x83fd0000 0x4000>;
513 clocks = <&clks IMX5_CLK_DUMMY>;
514 clock-names = "audmux";
458 status = "disabled"; 515 status = "disabled";
459 }; 516 };
460 517
@@ -463,7 +520,7 @@
463 #size-cells = <1>; 520 #size-cells = <1>;
464 compatible = "fsl,imx51-weim"; 521 compatible = "fsl,imx51-weim";
465 reg = <0x83fda000 0x1000>; 522 reg = <0x83fda000 0x1000>;
466 clocks = <&clks 57>; 523 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
467 ranges = < 524 ranges = <
468 0 0 0xb0000000 0x08000000 525 0 0 0xb0000000 0x08000000
469 1 0 0xb8000000 0x08000000 526 1 0 0xb8000000 0x08000000
@@ -479,7 +536,7 @@
479 compatible = "fsl,imx51-nand"; 536 compatible = "fsl,imx51-nand";
480 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 537 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
481 interrupts = <8>; 538 interrupts = <8>;
482 clocks = <&clks 60>; 539 clocks = <&clks IMX5_CLK_NFC_GATE>;
483 status = "disabled"; 540 status = "disabled";
484 }; 541 };
485 542
@@ -487,7 +544,7 @@
487 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 544 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
488 reg = <0x83fe0000 0x4000>; 545 reg = <0x83fe0000 0x4000>;
489 interrupts = <70>; 546 interrupts = <70>;
490 clocks = <&clks 172>; 547 clocks = <&clks IMX5_CLK_PATA_GATE>;
491 status = "disabled"; 548 status = "disabled";
492 }; 549 };
493 550
@@ -495,7 +552,7 @@
495 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 552 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
496 reg = <0x83fe8000 0x4000>; 553 reg = <0x83fe8000 0x4000>;
497 interrupts = <96>; 554 interrupts = <96>;
498 clocks = <&clks 50>; 555 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
499 dmas = <&sdma 46 0 0>, 556 dmas = <&sdma 46 0 0>,
500 <&sdma 47 0 0>; 557 <&sdma 47 0 0>;
501 dma-names = "rx", "tx"; 558 dma-names = "rx", "tx";
@@ -508,336 +565,12 @@
508 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 565 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
509 reg = <0x83fec000 0x4000>; 566 reg = <0x83fec000 0x4000>;
510 interrupts = <87>; 567 interrupts = <87>;
511 clocks = <&clks 42>, <&clks 42>, <&clks 42>; 568 clocks = <&clks IMX5_CLK_FEC_GATE>,
569 <&clks IMX5_CLK_FEC_GATE>,
570 <&clks IMX5_CLK_FEC_GATE>;
512 clock-names = "ipg", "ahb", "ptp"; 571 clock-names = "ipg", "ahb", "ptp";
513 status = "disabled"; 572 status = "disabled";
514 }; 573 };
515 }; 574 };
516 }; 575 };
517}; 576};
518
519&iomuxc {
520 audmux {
521 pinctrl_audmux_1: audmuxgrp-1 {
522 fsl,pins = <
523 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
524 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
525 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
526 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
527 >;
528 };
529 };
530
531 fec {
532 pinctrl_fec_1: fecgrp-1 {
533 fsl,pins = <
534 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
535 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
536 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
537 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
538 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
539 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
540 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
541 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
542 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
543 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
544 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
545 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
546 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
547 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
548 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
549 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
550 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
551 >;
552 };
553
554 pinctrl_fec_2: fecgrp-2 {
555 fsl,pins = <
556 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
557 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
558 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
559 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
560 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
561 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
562 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
563 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
564 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
565 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
566 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
567 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
568 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
569 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
570 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
571 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
572 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
573 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
574 >;
575 };
576 };
577
578 ecspi1 {
579 pinctrl_ecspi1_1: ecspi1grp-1 {
580 fsl,pins = <
581 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
582 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
583 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
584 >;
585 };
586 };
587
588 ecspi2 {
589 pinctrl_ecspi2_1: ecspi2grp-1 {
590 fsl,pins = <
591 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
592 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
593 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
594 >;
595 };
596 };
597
598 esdhc1 {
599 pinctrl_esdhc1_1: esdhc1grp-1 {
600 fsl,pins = <
601 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
602 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
603 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
604 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
605 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
606 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
607 >;
608 };
609 };
610
611 esdhc2 {
612 pinctrl_esdhc2_1: esdhc2grp-1 {
613 fsl,pins = <
614 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
615 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
616 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
617 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
618 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
619 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
620 >;
621 };
622 };
623
624 i2c2 {
625 pinctrl_i2c2_1: i2c2grp-1 {
626 fsl,pins = <
627 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
628 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
629 >;
630 };
631
632 pinctrl_i2c2_2: i2c2grp-2 {
633 fsl,pins = <
634 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
635 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
636 >;
637 };
638
639 pinctrl_i2c2_3: i2c2grp-3 {
640 fsl,pins = <
641 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
642 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
643 >;
644 };
645 };
646
647 ipu_disp1 {
648 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
649 fsl,pins = <
650 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
651 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
652 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
653 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
654 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
655 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
656 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
657 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
658 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
659 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
660 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
661 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
662 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
663 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
664 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
665 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
666 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
667 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
668 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
669 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
670 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
671 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
672 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
673 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
674 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
675 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
676 >;
677 };
678 };
679
680 ipu_disp2 {
681 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
682 fsl,pins = <
683 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
684 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
685 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
686 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
687 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
688 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
689 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
690 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
691 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
692 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
693 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
694 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
695 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
696 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
697 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
698 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
699 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
700 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
701 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
702 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
703 >;
704 };
705 };
706
707 kpp {
708 pinctrl_kpp_1: kppgrp-1 {
709 fsl,pins = <
710 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
711 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
712 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
713 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
714 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
715 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
716 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
717 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
718 >;
719 };
720 };
721
722 pata {
723 pinctrl_pata_1: patagrp-1 {
724 fsl,pins = <
725 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
726 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
727 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
728 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
729 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
730 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
731 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
732 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
733 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
734 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
735 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
736 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
737 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
738 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
739 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
740 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
741 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
742 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
743 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
744 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
745 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
746 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
747 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
748 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
749 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
750 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
751 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
752 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
753 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
754 >;
755 };
756 };
757
758 uart1 {
759 pinctrl_uart1_1: uart1grp-1 {
760 fsl,pins = <
761 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
762 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
763 >;
764 };
765
766 pinctrl_uart1_rtscts_1: uart1rtscts-1 {
767 fsl,pins = <
768 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
769 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
770 >;
771 };
772 };
773
774 uart2 {
775 pinctrl_uart2_1: uart2grp-1 {
776 fsl,pins = <
777 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
778 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
779 >;
780 };
781 };
782
783 uart3 {
784 pinctrl_uart3_1: uart3grp-1 {
785 fsl,pins = <
786 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
787 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
788 >;
789 };
790
791 pinctrl_uart3_rtscts_1: uart3rtscts-1 {
792 fsl,pins = <
793 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
794 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
795 >;
796 };
797
798 pinctrl_uart3_2: uart3grp-2 {
799 fsl,pins = <
800 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
801 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
802 >;
803 };
804 };
805
806 usbh1 {
807 pinctrl_usbh1_1: usbh1grp-1 {
808 fsl,pins = <
809 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
810 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
811 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
812 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
813 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
814 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
815 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
816 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
817 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
818 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
819 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
820 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
821 >;
822 };
823 };
824
825 usbh2 {
826 pinctrl_usbh2_1: usbh2grp-1 {
827 fsl,pins = <
828 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
829 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
830 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
831 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
832 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
833 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
834 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
835 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
836 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
837 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
838 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
839 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
840 >;
841 };
842 };
843};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 07:01:08 -0500