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Diffstat (limited to 'arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts')
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts120
1 files changed, 120 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 5cec4f322096..75e66c9c6144 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -24,6 +24,14 @@
24 model = "Eukrea CPUIMX51"; 24 model = "Eukrea CPUIMX51";
25 compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51"; 25 compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
26 26
27 clocks {
28 clk24M: can_clock {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <24000000>;
32 };
33 };
34
27 gpio_keys { 35 gpio_keys {
28 compatible = "gpio-keys"; 36 compatible = "gpio-keys";
29 pinctrl-names = "default"; 37 pinctrl-names = "default";
@@ -50,6 +58,23 @@
50 }; 58 };
51 }; 59 };
52 60
61 regulators {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <0>;
65
66 reg_can: regulator@0 {
67 compatible = "regulator-fixed";
68 reg = <0>;
69 regulator-name = "CAN_RST";
70 regulator-min-microvolt = <3300000>;
71 regulator-max-microvolt = <3300000>;
72 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
73 startup-delay-us = <20000>;
74 enable-active-high;
75 };
76 };
77
53 sound { 78 sound {
54 compatible = "eukrea,asoc-tlv320"; 79 compatible = "eukrea,asoc-tlv320";
55 eukrea,model = "imx51-eukrea-tlv320aic23"; 80 eukrea,model = "imx51-eukrea-tlv320aic23";
@@ -57,6 +82,20 @@
57 fsl,mux-int-port = <2>; 82 fsl,mux-int-port = <2>;
58 fsl,mux-ext-port = <3>; 83 fsl,mux-ext-port = <3>;
59 }; 84 };
85
86 usbphy {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "simple-bus";
90
91 usbh1phy: usbh1phy@0 {
92 compatible = "usb-nop-xceiv";
93 reg = <0>;
94 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
95 clock-names = "main_clk";
96 clock-frequency = <19200000>;
97 };
98 };
60}; 99};
61 100
62&audmux { 101&audmux {
@@ -72,6 +111,26 @@
72 status = "okay"; 111 status = "okay";
73}; 112};
74 113
114&ecspi1 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_ecspi1>;
117 fsl,spi-num-chipselects = <1>;
118 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
119 status = "okay";
120
121 can0: can@0 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_can>;
124 compatible = "microchip,mcp2515";
125 reg = <0>;
126 clocks = <&clk24M>;
127 spi-max-frequency = <10000000>;
128 interrupt-parent = <&gpio1>;
129 interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
130 vdd-supply = <&reg_can>;
131 };
132};
133
75&i2c1 { 134&i2c1 {
76 tlv320aic23: codec@1a { 135 tlv320aic23: codec@1a {
77 compatible = "ti,tlv320aic23"; 136 compatible = "ti,tlv320aic23";
@@ -90,6 +149,23 @@
90 >; 149 >;
91 }; 150 };
92 151
152
153 pinctrl_can: cangrp {
154 fsl,pins = <
155 MX51_PAD_CSI2_PIXCLK__GPIO4_15 0x80000000 /* nReset */
156 MX51_PAD_GPIO1_1__GPIO1_1 0x80000000 /* IRQ */
157 >;
158 };
159
160 pinctrl_ecspi1: ecspi1grp {
161 fsl,pins = <
162 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
163 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
164 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
165 MX51_PAD_CSPI1_SS0__GPIO4_24 0x80000000 /* CS0 */
166 >;
167 };
168
93 pinctrl_esdhc1: esdhc1grp { 169 pinctrl_esdhc1: esdhc1grp {
94 fsl,pins = < 170 fsl,pins = <
95 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5 171 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
@@ -151,6 +227,29 @@
151 MX51_PAD_CSI1_D9__GPIO3_13 0x1f5 227 MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
152 >; 228 >;
153 }; 229 };
230
231 pinctrl_usbh1: usbh1grp {
232 fsl,pins = <
233 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
234 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
235 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
236 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
237 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
238 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
239 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
240 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
241 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
242 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
243 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
244 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
245 >;
246 };
247
248 pinctrl_usbh1_vbus: usbh1-vbusgrp {
249 fsl,pins = <
250 MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
251 >;
252 };
154 }; 253 };
155}; 254};
156 255
@@ -173,3 +272,24 @@
173 fsl,uart-has-rtscts; 272 fsl,uart-has-rtscts;
174 status = "okay"; 273 status = "okay";
175}; 274};
275
276&usbh1 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_usbh1>;
279 fsl,usbphy = <&usbh1phy>;
280 dr_mode = "host";
281 phy_type = "ulpi";
282 status = "okay";
283};
284
285&usbotg {
286 dr_mode = "otg";
287 phy_type = "utmi_wide";
288 status = "okay";
289};
290
291&usbphy0 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_usbh1_vbus>;
294 reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
295};