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-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts281
1 files changed, 242 insertions, 39 deletions
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index be1407cf5abd..9e9deb244b76 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -21,12 +21,11 @@
21 reg = <0x90000000 0x20000000>; 21 reg = <0x90000000 0x20000000>;
22 }; 22 };
23 23
24 display@di0 { 24 display0: display@di0 {
25 compatible = "fsl,imx-parallel-display"; 25 compatible = "fsl,imx-parallel-display";
26 crtcs = <&ipu 0>;
27 interface-pix-fmt = "rgb24"; 26 interface-pix-fmt = "rgb24";
28 pinctrl-names = "default"; 27 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_ipu_disp1_1>; 28 pinctrl-0 = <&pinctrl_ipu_disp1>;
30 display-timings { 29 display-timings {
31 native-mode = <&timing0>; 30 native-mode = <&timing0>;
32 timing0: dvi { 31 timing0: dvi {
@@ -41,14 +40,19 @@
41 vsync-len = <10>; 40 vsync-len = <10>;
42 }; 41 };
43 }; 42 };
43
44 port {
45 display0_in: endpoint {
46 remote-endpoint = <&ipu_di0_disp0>;
47 };
48 };
44 }; 49 };
45 50
46 display@di1 { 51 display1: display@di1 {
47 compatible = "fsl,imx-parallel-display"; 52 compatible = "fsl,imx-parallel-display";
48 crtcs = <&ipu 1>;
49 interface-pix-fmt = "rgb565"; 53 interface-pix-fmt = "rgb565";
50 pinctrl-names = "default"; 54 pinctrl-names = "default";
51 pinctrl-0 = <&pinctrl_ipu_disp2_1>; 55 pinctrl-0 = <&pinctrl_ipu_disp2>;
52 status = "disabled"; 56 status = "disabled";
53 display-timings { 57 display-timings {
54 native-mode = <&timing1>; 58 native-mode = <&timing1>;
@@ -68,6 +72,12 @@
68 pixelclk-active = <0>; 72 pixelclk-active = <0>;
69 }; 73 };
70 }; 74 };
75
76 port {
77 display1_in: endpoint {
78 remote-endpoint = <&ipu_di1_disp1>;
79 };
80 };
71 }; 81 };
72 82
73 gpio-keys { 83 gpio-keys {
@@ -75,12 +85,23 @@
75 85
76 power { 86 power {
77 label = "Power Button"; 87 label = "Power Button";
78 gpios = <&gpio2 21 0>; 88 gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
79 linux,code = <116>; /* KEY_POWER */ 89 linux,code = <116>; /* KEY_POWER */
80 gpio-key,wakeup; 90 gpio-key,wakeup;
81 }; 91 };
82 }; 92 };
83 93
94 leds {
95 compatible = "gpio-leds";
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_gpio_leds>;
98
99 led-diagnostic {
100 label = "diagnostic";
101 gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
102 };
103 };
104
84 sound { 105 sound {
85 compatible = "fsl,imx51-babbage-sgtl5000", 106 compatible = "fsl,imx51-babbage-sgtl5000",
86 "fsl,imx-audio-sgtl5000"; 107 "fsl,imx-audio-sgtl5000";
@@ -105,14 +126,14 @@
105 reg=<0>; 126 reg=<0>;
106 #clock-cells = <0>; 127 #clock-cells = <0>;
107 clock-frequency = <26000000>; 128 clock-frequency = <26000000>;
108 gpios = <&gpio4 26 1>; 129 gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
109 }; 130 };
110 }; 131 };
111}; 132};
112 133
113&esdhc1 { 134&esdhc1 {
114 pinctrl-names = "default"; 135 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_esdhc1_1>; 136 pinctrl-0 = <&pinctrl_esdhc1>;
116 fsl,cd-controller; 137 fsl,cd-controller;
117 fsl,wp-controller; 138 fsl,wp-controller;
118 status = "okay"; 139 status = "okay";
@@ -120,24 +141,25 @@
120 141
121&esdhc2 { 142&esdhc2 {
122 pinctrl-names = "default"; 143 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_esdhc2_1>; 144 pinctrl-0 = <&pinctrl_esdhc2>;
124 cd-gpios = <&gpio1 6 0>; 145 cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
125 wp-gpios = <&gpio1 5 0>; 146 wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
126 status = "okay"; 147 status = "okay";
127}; 148};
128 149
129&uart3 { 150&uart3 {
130 pinctrl-names = "default"; 151 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>; 152 pinctrl-0 = <&pinctrl_uart3>;
132 fsl,uart-has-rtscts; 153 fsl,uart-has-rtscts;
133 status = "okay"; 154 status = "okay";
134}; 155};
135 156
136&ecspi1 { 157&ecspi1 {
137 pinctrl-names = "default"; 158 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_ecspi1_1>; 159 pinctrl-0 = <&pinctrl_ecspi1>;
139 fsl,spi-num-chipselects = <2>; 160 fsl,spi-num-chipselects = <2>;
140 cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>; 161 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
162 <&gpio4 25 GPIO_ACTIVE_LOW>;
141 status = "okay"; 163 status = "okay";
142 164
143 pmic: mc13892@0 { 165 pmic: mc13892@0 {
@@ -148,7 +170,7 @@
148 spi-cs-high; 170 spi-cs-high;
149 reg = <0>; 171 reg = <0>;
150 interrupt-parent = <&gpio1>; 172 interrupt-parent = <&gpio1>;
151 interrupts = <8 0x4>; 173 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
152 174
153 regulators { 175 regulators {
154 sw1_reg: sw1 { 176 sw1_reg: sw1 {
@@ -258,6 +280,14 @@
258 }; 280 };
259}; 281};
260 282
283&ipu_di0_disp0 {
284 remote-endpoint = <&display0_in>;
285};
286
287&ipu_di1_disp1 {
288 remote-endpoint = <&display1_in>;
289};
290
261&ssi2 { 291&ssi2 {
262 fsl,mode = "i2s-slave"; 292 fsl,mode = "i2s-slave";
263 status = "okay"; 293 status = "okay";
@@ -267,7 +297,7 @@
267 pinctrl-names = "default"; 297 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_hog>; 298 pinctrl-0 = <&pinctrl_hog>;
269 299
270 hog { 300 imx51-babbage {
271 pinctrl_hog: hoggrp { 301 pinctrl_hog: hoggrp {
272 fsl,pins = < 302 fsl,pins = <
273 MX51_PAD_GPIO1_0__SD1_CD 0x20d5 303 MX51_PAD_GPIO1_0__SD1_CD 0x20d5
@@ -280,25 +310,194 @@
280 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000 310 MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
281 >; 311 >;
282 }; 312 };
313
314 pinctrl_audmux: audmuxgrp {
315 fsl,pins = <
316 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
317 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
318 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
319 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
320 >;
321 };
322
323 pinctrl_ecspi1: ecspi1grp {
324 fsl,pins = <
325 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
326 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
327 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
328 >;
329 };
330
331 pinctrl_esdhc1: esdhc1grp {
332 fsl,pins = <
333 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
334 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
335 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
336 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
337 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
338 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
339 >;
340 };
341
342 pinctrl_esdhc2: esdhc2grp {
343 fsl,pins = <
344 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
345 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
346 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
347 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
348 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
349 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
350 >;
351 };
352
353 pinctrl_fec: fecgrp {
354 fsl,pins = <
355 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
356 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
357 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
358 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
359 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
360 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
361 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
362 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
363 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
364 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
365 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
366 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
367 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
368 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
369 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
370 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
371 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
372 MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
373 >;
374 };
375
376 pinctrl_gpio_leds: gpioledsgrp {
377 fsl,pins = <
378 MX51_PAD_EIM_D22__GPIO2_6 0x80000000
379 >;
380 };
381
382 pinctrl_i2c2: i2c2grp {
383 fsl,pins = <
384 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
385 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
386 >;
387 };
388
389 pinctrl_ipu_disp1: ipudisp1grp {
390 fsl,pins = <
391 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
392 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
393 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
394 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
395 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
396 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
397 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
398 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
399 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
400 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
401 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
402 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
403 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
404 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
405 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
406 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
407 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
408 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
409 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
410 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
411 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
412 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
413 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
414 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
415 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
416 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
417 >;
418 };
419
420 pinctrl_ipu_disp2: ipudisp2grp {
421 fsl,pins = <
422 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
423 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
424 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
425 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
426 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
427 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
428 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
429 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
430 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
431 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
432 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
433 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
434 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
435 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
436 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
437 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
438 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5
439 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5
440 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
441 MX51_PAD_DI_GP4__DI2_PIN15 0x5
442 >;
443 };
444
445 pinctrl_kpp: kppgrp {
446 fsl,pins = <
447 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
448 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
449 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
450 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
451 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
452 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
453 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
454 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
455 >;
456 };
457
458 pinctrl_uart1: uart1grp {
459 fsl,pins = <
460 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
461 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
462 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
463 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
464 >;
465 };
466
467 pinctrl_uart2: uart2grp {
468 fsl,pins = <
469 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
470 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
471 >;
472 };
473
474 pinctrl_uart3: uart3grp {
475 fsl,pins = <
476 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
477 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
478 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
479 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
480 >;
481 };
283 }; 482 };
284}; 483};
285 484
286&uart1 { 485&uart1 {
287 pinctrl-names = "default"; 486 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>; 487 pinctrl-0 = <&pinctrl_uart1>;
289 fsl,uart-has-rtscts; 488 fsl,uart-has-rtscts;
290 status = "okay"; 489 status = "okay";
291}; 490};
292 491
293&uart2 { 492&uart2 {
294 pinctrl-names = "default"; 493 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart2_1>; 494 pinctrl-0 = <&pinctrl_uart2>;
296 status = "okay"; 495 status = "okay";
297}; 496};
298 497
299&i2c2 { 498&i2c2 {
300 pinctrl-names = "default"; 499 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c2_1>; 500 pinctrl-0 = <&pinctrl_i2c2>;
302 status = "okay"; 501 status = "okay";
303 502
304 sgtl5000: codec@0a { 503 sgtl5000: codec@0a {
@@ -312,35 +511,39 @@
312 511
313&audmux { 512&audmux {
314 pinctrl-names = "default"; 513 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_audmux_1>; 514 pinctrl-0 = <&pinctrl_audmux>;
316 status = "okay"; 515 status = "okay";
317}; 516};
318 517
319&fec { 518&fec {
320 pinctrl-names = "default"; 519 pinctrl-names = "default";
321 pinctrl-0 = <&pinctrl_fec_1>; 520 pinctrl-0 = <&pinctrl_fec>;
322 phy-mode = "mii"; 521 phy-mode = "mii";
522 phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
523 phy-reset-duration = <1>;
323 status = "okay"; 524 status = "okay";
324}; 525};
325 526
326&kpp { 527&kpp {
327 pinctrl-names = "default"; 528 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_kpp_1>; 529 pinctrl-0 = <&pinctrl_kpp>;
329 linux,keymap = <0x00000067 /* KEY_UP */ 530 linux,keymap = <
330 0x0001006c /* KEY_DOWN */ 531 MATRIX_KEY(0, 0, KEY_UP)
331 0x00020072 /* KEY_VOLUMEDOWN */ 532 MATRIX_KEY(0, 1, KEY_DOWN)
332 0x00030066 /* KEY_HOME */ 533 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
333 0x0100006a /* KEY_RIGHT */ 534 MATRIX_KEY(0, 3, KEY_HOME)
334 0x01010069 /* KEY_LEFT */ 535 MATRIX_KEY(1, 0, KEY_RIGHT)
335 0x0102001c /* KEY_ENTER */ 536 MATRIX_KEY(1, 1, KEY_LEFT)
336 0x01030073 /* KEY_VOLUMEUP */ 537 MATRIX_KEY(1, 2, KEY_ENTER)
337 0x02000040 /* KEY_F6 */ 538 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
338 0x02010042 /* KEY_F8 */ 539 MATRIX_KEY(2, 0, KEY_F6)
339 0x02020043 /* KEY_F9 */ 540 MATRIX_KEY(2, 1, KEY_F8)
340 0x02030044 /* KEY_F10 */ 541 MATRIX_KEY(2, 2, KEY_F9)
341 0x0300003b /* KEY_F1 */ 542 MATRIX_KEY(2, 3, KEY_F10)
342 0x0301003c /* KEY_F2 */ 543 MATRIX_KEY(3, 0, KEY_F1)
343 0x0302003d /* KEY_F3 */ 544 MATRIX_KEY(3, 1, KEY_F2)
344 0x03030074>; /* KEY_POWER */ 545 MATRIX_KEY(3, 2, KEY_F3)
546 MATRIX_KEY(3, 3, KEY_POWER)
547 >;
345 status = "okay"; 548 status = "okay";
346}; 549};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 07:02:00 -0500