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Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi195
1 files changed, 173 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index b69fbcb7dcb8..e38532271ef9 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -47,6 +47,8 @@
47 spi0 = &spi_0; 47 spi0 = &spi_0;
48 spi1 = &spi_1; 48 spi1 = &spi_1;
49 spi2 = &spi_2; 49 spi2 = &spi_2;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
50 }; 52 };
51 53
52 cpus { 54 cpus {
@@ -58,6 +60,7 @@
58 compatible = "arm,cortex-a15"; 60 compatible = "arm,cortex-a15";
59 reg = <0x0>; 61 reg = <0x0>;
60 clock-frequency = <1800000000>; 62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
61 }; 64 };
62 65
63 cpu1: cpu@1 { 66 cpu1: cpu@1 {
@@ -65,6 +68,7 @@
65 compatible = "arm,cortex-a15"; 68 compatible = "arm,cortex-a15";
66 reg = <0x1>; 69 reg = <0x1>;
67 clock-frequency = <1800000000>; 70 clock-frequency = <1800000000>;
71 cci-control-port = <&cci_control1>;
68 }; 72 };
69 73
70 cpu2: cpu@2 { 74 cpu2: cpu@2 {
@@ -72,6 +76,7 @@
72 compatible = "arm,cortex-a15"; 76 compatible = "arm,cortex-a15";
73 reg = <0x2>; 77 reg = <0x2>;
74 clock-frequency = <1800000000>; 78 clock-frequency = <1800000000>;
79 cci-control-port = <&cci_control1>;
75 }; 80 };
76 81
77 cpu3: cpu@3 { 82 cpu3: cpu@3 {
@@ -79,6 +84,7 @@
79 compatible = "arm,cortex-a15"; 84 compatible = "arm,cortex-a15";
80 reg = <0x3>; 85 reg = <0x3>;
81 clock-frequency = <1800000000>; 86 clock-frequency = <1800000000>;
87 cci-control-port = <&cci_control1>;
82 }; 88 };
83 89
84 cpu4: cpu@100 { 90 cpu4: cpu@100 {
@@ -86,6 +92,7 @@
86 compatible = "arm,cortex-a7"; 92 compatible = "arm,cortex-a7";
87 reg = <0x100>; 93 reg = <0x100>;
88 clock-frequency = <1000000000>; 94 clock-frequency = <1000000000>;
95 cci-control-port = <&cci_control0>;
89 }; 96 };
90 97
91 cpu5: cpu@101 { 98 cpu5: cpu@101 {
@@ -93,6 +100,7 @@
93 compatible = "arm,cortex-a7"; 100 compatible = "arm,cortex-a7";
94 reg = <0x101>; 101 reg = <0x101>;
95 clock-frequency = <1000000000>; 102 clock-frequency = <1000000000>;
103 cci-control-port = <&cci_control0>;
96 }; 104 };
97 105
98 cpu6: cpu@102 { 106 cpu6: cpu@102 {
@@ -100,6 +108,7 @@
100 compatible = "arm,cortex-a7"; 108 compatible = "arm,cortex-a7";
101 reg = <0x102>; 109 reg = <0x102>;
102 clock-frequency = <1000000000>; 110 clock-frequency = <1000000000>;
111 cci-control-port = <&cci_control0>;
103 }; 112 };
104 113
105 cpu7: cpu@103 { 114 cpu7: cpu@103 {
@@ -107,6 +116,44 @@
107 compatible = "arm,cortex-a7"; 116 compatible = "arm,cortex-a7";
108 reg = <0x103>; 117 reg = <0x103>;
109 clock-frequency = <1000000000>; 118 clock-frequency = <1000000000>;
119 cci-control-port = <&cci_control0>;
120 };
121 };
122
123 cci@10d20000 {
124 compatible = "arm,cci-400";
125 #address-cells = <1>;
126 #size-cells = <1>;
127 reg = <0x10d20000 0x1000>;
128 ranges = <0x0 0x10d20000 0x6000>;
129
130 cci_control0: slave-if@4000 {
131 compatible = "arm,cci-400-ctrl-if";
132 interface-type = "ace";
133 reg = <0x4000 0x1000>;
134 };
135 cci_control1: slave-if@5000 {
136 compatible = "arm,cci-400-ctrl-if";
137 interface-type = "ace";
138 reg = <0x5000 0x1000>;
139 };
140 };
141
142 sysram@02020000 {
143 compatible = "mmio-sram";
144 reg = <0x02020000 0x54000>;
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0x02020000 0x54000>;
148
149 smp-sysram@0 {
150 compatible = "samsung,exynos4210-sysram";
151 reg = <0x0 0x1000>;
152 };
153
154 smp-sysram@53000 {
155 compatible = "samsung,exynos4210-sysram-ns";
156 reg = <0x53000 0x1000>;
110 }; 157 };
111 }; 158 };
112 159
@@ -125,12 +172,13 @@
125 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 172 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
126 }; 173 };
127 174
128 codec@11000000 { 175 mfc: codec@11000000 {
129 compatible = "samsung,mfc-v7"; 176 compatible = "samsung,mfc-v7";
130 reg = <0x11000000 0x10000>; 177 reg = <0x11000000 0x10000>;
131 interrupts = <0 96 0>; 178 interrupts = <0 96 0>;
132 clocks = <&clock CLK_MFC>; 179 clocks = <&clock CLK_MFC>;
133 clock-names = "mfc"; 180 clock-names = "mfc";
181 samsung,power-domain = <&mfc_pd>;
134 }; 182 };
135 183
136 mmc_0: mmc@12200000 { 184 mmc_0: mmc@12200000 {
@@ -169,7 +217,7 @@
169 status = "disabled"; 217 status = "disabled";
170 }; 218 };
171 219
172 mct@101C0000 { 220 mct: mct@101C0000 {
173 compatible = "samsung,exynos4210-mct"; 221 compatible = "samsung,exynos4210-mct";
174 reg = <0x101C0000 0x800>; 222 reg = <0x101C0000 0x800>;
175 interrupt-controller; 223 interrupt-controller;
@@ -260,7 +308,7 @@
260 interrupts = <0 47 0>; 308 interrupts = <0 47 0>;
261 }; 309 };
262 310
263 rtc@101E0000 { 311 rtc: rtc@101E0000 {
264 clocks = <&clock CLK_RTC>; 312 clocks = <&clock CLK_RTC>;
265 clock-names = "rtc"; 313 clock-names = "rtc";
266 status = "disabled"; 314 status = "disabled";
@@ -427,22 +475,22 @@
427 status = "disabled"; 475 status = "disabled";
428 }; 476 };
429 477
430 serial@12C00000 { 478 uart_0: serial@12C00000 {
431 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 479 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
432 clock-names = "uart", "clk_uart_baud0"; 480 clock-names = "uart", "clk_uart_baud0";
433 }; 481 };
434 482
435 serial@12C10000 { 483 uart_1: serial@12C10000 {
436 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 484 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
437 clock-names = "uart", "clk_uart_baud0"; 485 clock-names = "uart", "clk_uart_baud0";
438 }; 486 };
439 487
440 serial@12C20000 { 488 uart_2: serial@12C20000 {
441 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 489 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
442 clock-names = "uart", "clk_uart_baud0"; 490 clock-names = "uart", "clk_uart_baud0";
443 }; 491 };
444 492
445 serial@12C30000 { 493 uart_3: serial@12C30000 {
446 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 494 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
447 clock-names = "uart", "clk_uart_baud0"; 495 clock-names = "uart", "clk_uart_baud0";
448 }; 496 };
@@ -462,14 +510,14 @@
462 #phy-cells = <0>; 510 #phy-cells = <0>;
463 }; 511 };
464 512
465 dp-controller@145B0000 { 513 dp: dp-controller@145B0000 {
466 clocks = <&clock CLK_DP1>; 514 clocks = <&clock CLK_DP1>;
467 clock-names = "dp"; 515 clock-names = "dp";
468 phys = <&dp_phy>; 516 phys = <&dp_phy>;
469 phy-names = "dp"; 517 phy-names = "dp";
470 }; 518 };
471 519
472 fimd@14400000 { 520 fimd: fimd@14400000 {
473 samsung,power-domain = <&disp_pd>; 521 samsung,power-domain = <&disp_pd>;
474 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 522 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
475 clock-names = "sclk_fimd", "fimd"; 523 clock-names = "sclk_fimd", "fimd";
@@ -546,7 +594,7 @@
546 #size-cells = <0>; 594 #size-cells = <0>;
547 pinctrl-names = "default"; 595 pinctrl-names = "default";
548 pinctrl-0 = <&i2c4_hs_bus>; 596 pinctrl-0 = <&i2c4_hs_bus>;
549 clocks = <&clock CLK_I2C4>; 597 clocks = <&clock CLK_USI0>;
550 clock-names = "hsi2c"; 598 clock-names = "hsi2c";
551 status = "disabled"; 599 status = "disabled";
552 }; 600 };
@@ -559,7 +607,7 @@
559 #size-cells = <0>; 607 #size-cells = <0>;
560 pinctrl-names = "default"; 608 pinctrl-names = "default";
561 pinctrl-0 = <&i2c5_hs_bus>; 609 pinctrl-0 = <&i2c5_hs_bus>;
562 clocks = <&clock CLK_I2C5>; 610 clocks = <&clock CLK_USI1>;
563 clock-names = "hsi2c"; 611 clock-names = "hsi2c";
564 status = "disabled"; 612 status = "disabled";
565 }; 613 };
@@ -572,7 +620,7 @@
572 #size-cells = <0>; 620 #size-cells = <0>;
573 pinctrl-names = "default"; 621 pinctrl-names = "default";
574 pinctrl-0 = <&i2c6_hs_bus>; 622 pinctrl-0 = <&i2c6_hs_bus>;
575 clocks = <&clock CLK_I2C6>; 623 clocks = <&clock CLK_USI2>;
576 clock-names = "hsi2c"; 624 clock-names = "hsi2c";
577 status = "disabled"; 625 status = "disabled";
578 }; 626 };
@@ -585,7 +633,7 @@
585 #size-cells = <0>; 633 #size-cells = <0>;
586 pinctrl-names = "default"; 634 pinctrl-names = "default";
587 pinctrl-0 = <&i2c7_hs_bus>; 635 pinctrl-0 = <&i2c7_hs_bus>;
588 clocks = <&clock CLK_I2C7>; 636 clocks = <&clock CLK_USI3>;
589 clock-names = "hsi2c"; 637 clock-names = "hsi2c";
590 status = "disabled"; 638 status = "disabled";
591 }; 639 };
@@ -598,7 +646,7 @@
598 #size-cells = <0>; 646 #size-cells = <0>;
599 pinctrl-names = "default"; 647 pinctrl-names = "default";
600 pinctrl-0 = <&i2c8_hs_bus>; 648 pinctrl-0 = <&i2c8_hs_bus>;
601 clocks = <&clock CLK_I2C8>; 649 clocks = <&clock CLK_USI4>;
602 clock-names = "hsi2c"; 650 clock-names = "hsi2c";
603 status = "disabled"; 651 status = "disabled";
604 }; 652 };
@@ -611,7 +659,7 @@
611 #size-cells = <0>; 659 #size-cells = <0>;
612 pinctrl-names = "default"; 660 pinctrl-names = "default";
613 pinctrl-0 = <&i2c9_hs_bus>; 661 pinctrl-0 = <&i2c9_hs_bus>;
614 clocks = <&clock CLK_I2C9>; 662 clocks = <&clock CLK_USI5>;
615 clock-names = "hsi2c"; 663 clock-names = "hsi2c";
616 status = "disabled"; 664 status = "disabled";
617 }; 665 };
@@ -624,13 +672,13 @@
624 #size-cells = <0>; 672 #size-cells = <0>;
625 pinctrl-names = "default"; 673 pinctrl-names = "default";
626 pinctrl-0 = <&i2c10_hs_bus>; 674 pinctrl-0 = <&i2c10_hs_bus>;
627 clocks = <&clock CLK_I2C10>; 675 clocks = <&clock CLK_USI6>;
628 clock-names = "hsi2c"; 676 clock-names = "hsi2c";
629 status = "disabled"; 677 status = "disabled";
630 }; 678 };
631 679
632 hdmi@14530000 { 680 hdmi: hdmi@14530000 {
633 compatible = "samsung,exynos4212-hdmi"; 681 compatible = "samsung,exynos5420-hdmi";
634 reg = <0x14530000 0x70000>; 682 reg = <0x14530000 0x70000>;
635 interrupts = <0 95 0>; 683 interrupts = <0 95 0>;
636 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 684 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -638,10 +686,16 @@
638 <&clock CLK_MOUT_HDMI>; 686 <&clock CLK_MOUT_HDMI>;
639 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 687 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
640 "sclk_hdmiphy", "mout_hdmi"; 688 "sclk_hdmiphy", "mout_hdmi";
689 phy = <&hdmiphy>;
690 samsung,syscon-phandle = <&pmu_system_controller>;
641 status = "disabled"; 691 status = "disabled";
642 }; 692 };
643 693
644 mixer@14450000 { 694 hdmiphy: hdmiphy@145D0000 {
695 reg = <0x145D0000 0x20>;
696 };
697
698 mixer: mixer@14450000 {
645 compatible = "samsung,exynos5420-mixer"; 699 compatible = "samsung,exynos5420-mixer";
646 reg = <0x14450000 0x10000>; 700 reg = <0x14450000 0x10000>;
647 interrupts = <0 94 0>; 701 interrupts = <0 94 0>;
@@ -672,6 +726,11 @@
672 reg = <0x10040000 0x5000>; 726 reg = <0x10040000 0x5000>;
673 }; 727 };
674 728
729 sysreg_system_controller: syscon@10050000 {
730 compatible = "samsung,exynos5-sysreg", "syscon";
731 reg = <0x10050000 0x5000>;
732 };
733
675 tmu_cpu0: tmu@10060000 { 734 tmu_cpu0: tmu@10060000 {
676 compatible = "samsung,exynos5420-tmu"; 735 compatible = "samsung,exynos5420-tmu";
677 reg = <0x10060000 0x100>; 736 reg = <0x10060000 0x100>;
@@ -712,7 +771,7 @@
712 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 771 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
713 }; 772 };
714 773
715 watchdog@101D0000 { 774 watchdog: watchdog@101D0000 {
716 compatible = "samsung,exynos5420-wdt"; 775 compatible = "samsung,exynos5420-wdt";
717 reg = <0x101D0000 0x100>; 776 reg = <0x101D0000 0x100>;
718 interrupts = <0 42 0>; 777 interrupts = <0 42 0>;
@@ -721,11 +780,103 @@
721 samsung,syscon-phandle = <&pmu_system_controller>; 780 samsung,syscon-phandle = <&pmu_system_controller>;
722 }; 781 };
723 782
724 sss@10830000 { 783 sss: sss@10830000 {
725 compatible = "samsung,exynos4210-secss"; 784 compatible = "samsung,exynos4210-secss";
726 reg = <0x10830000 0x10000>; 785 reg = <0x10830000 0x10000>;
727 interrupts = <0 112 0>; 786 interrupts = <0 112 0>;
728 clocks = <&clock 471>; 787 clocks = <&clock CLK_SSS>;
729 clock-names = "secss"; 788 clock-names = "secss";
730 }; 789 };
790
791 usbdrd3_0: usb@12000000 {
792 compatible = "samsung,exynos5250-dwusb3";
793 clocks = <&clock CLK_USBD300>;
794 clock-names = "usbdrd30";
795 #address-cells = <1>;
796 #size-cells = <1>;
797 ranges;
798
799 dwc3 {
800 compatible = "snps,dwc3";
801 reg = <0x12000000 0x10000>;
802 interrupts = <0 72 0>;
803 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
804 phy-names = "usb2-phy", "usb3-phy";
805 };
806 };
807
808 usbdrd_phy0: phy@12100000 {
809 compatible = "samsung,exynos5420-usbdrd-phy";
810 reg = <0x12100000 0x100>;
811 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
812 clock-names = "phy", "ref";
813 samsung,pmu-syscon = <&pmu_system_controller>;
814 #phy-cells = <1>;
815 };
816
817 usbdrd3_1: usb@12400000 {
818 compatible = "samsung,exynos5250-dwusb3";
819 clocks = <&clock CLK_USBD301>;
820 clock-names = "usbdrd30";
821 #address-cells = <1>;
822 #size-cells = <1>;
823 ranges;
824
825 dwc3 {
826 compatible = "snps,dwc3";
827 reg = <0x12400000 0x10000>;
828 interrupts = <0 73 0>;
829 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
830 phy-names = "usb2-phy", "usb3-phy";
831 };
832 };
833
834 usbdrd_phy1: phy@12500000 {
835 compatible = "samsung,exynos5420-usbdrd-phy";
836 reg = <0x12500000 0x100>;
837 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
838 clock-names = "phy", "ref";
839 samsung,pmu-syscon = <&pmu_system_controller>;
840 #phy-cells = <1>;
841 };
842
843 usbhost2: usb@12110000 {
844 compatible = "samsung,exynos4210-ehci";
845 reg = <0x12110000 0x100>;
846 interrupts = <0 71 0>;
847
848 clocks = <&clock CLK_USBH20>;
849 clock-names = "usbhost";
850 #address-cells = <1>;
851 #size-cells = <0>;
852 port@0 {
853 reg = <0>;
854 phys = <&usb2_phy 1>;
855 };
856 };
857
858 usbhost1: usb@12120000 {
859 compatible = "samsung,exynos4210-ohci";
860 reg = <0x12120000 0x100>;
861 interrupts = <0 71 0>;
862
863 clocks = <&clock CLK_USBH20>;
864 clock-names = "usbhost";
865 #address-cells = <1>;
866 #size-cells = <0>;
867 port@0 {
868 reg = <0>;
869 phys = <&usb2_phy 1>;
870 };
871 };
872
873 usb2_phy: phy@12130000 {
874 compatible = "samsung,exynos5250-usb2-phy";
875 reg = <0x12130000 0x100>;
876 clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
877 clock-names = "phy", "ref";
878 #phy-cells = <1>;
879 samsung,sysreg-phandle = <&sysreg_system_controller>;
880 samsung,pmureg-phandle = <&pmu_system_controller>;
881 };
731}; 882};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 12:47:58 -0500