diff options
Diffstat (limited to 'arch/arm/boot/dts/exynos5250.dtsi')
-rw-r--r-- | arch/arm/boot/dts/exynos5250.dtsi | 126 |
1 files changed, 63 insertions, 63 deletions
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index fc9fb3d526e2..41cd625b6020 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -17,12 +17,13 @@ | |||
17 | * published by the Free Software Foundation. | 17 | * published by the Free Software Foundation. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | /include/ "skeleton.dtsi" | 20 | #include "exynos5.dtsi" |
21 | /include/ "exynos5250-pinctrl.dtsi" | 21 | #include "exynos5250-pinctrl.dtsi" |
22 | |||
23 | #include <dt-bindings/clk/exynos-audss-clk.h> | ||
22 | 24 | ||
23 | / { | 25 | / { |
24 | compatible = "samsung,exynos5250"; | 26 | compatible = "samsung,exynos5250"; |
25 | interrupt-parent = <&gic>; | ||
26 | 27 | ||
27 | aliases { | 28 | aliases { |
28 | spi0 = &spi_0; | 29 | spi0 = &spi_0; |
@@ -51,9 +52,20 @@ | |||
51 | pinctrl3 = &pinctrl_3; | 52 | pinctrl3 = &pinctrl_3; |
52 | }; | 53 | }; |
53 | 54 | ||
54 | chipid@10000000 { | 55 | cpus { |
55 | compatible = "samsung,exynos4210-chipid"; | 56 | #address-cells = <1>; |
56 | reg = <0x10000000 0x100>; | 57 | #size-cells = <0>; |
58 | |||
59 | cpu@0 { | ||
60 | device_type = "cpu"; | ||
61 | compatible = "arm,cortex-a15"; | ||
62 | reg = <0>; | ||
63 | }; | ||
64 | cpu@1 { | ||
65 | device_type = "cpu"; | ||
66 | compatible = "arm,cortex-a15"; | ||
67 | reg = <1>; | ||
68 | }; | ||
57 | }; | 69 | }; |
58 | 70 | ||
59 | pd_gsc: gsc-power-domain@0x10044000 { | 71 | pd_gsc: gsc-power-domain@0x10044000 { |
@@ -72,15 +84,10 @@ | |||
72 | #clock-cells = <1>; | 84 | #clock-cells = <1>; |
73 | }; | 85 | }; |
74 | 86 | ||
75 | gic:interrupt-controller@10481000 { | 87 | clock_audss: audss-clock-controller@3810000 { |
76 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | 88 | compatible = "samsung,exynos5250-audss-clock"; |
77 | #interrupt-cells = <3>; | 89 | reg = <0x03810000 0x0C>; |
78 | interrupt-controller; | 90 | #clock-cells = <1>; |
79 | reg = <0x10481000 0x1000>, | ||
80 | <0x10482000 0x1000>, | ||
81 | <0x10484000 0x2000>, | ||
82 | <0x10486000 0x2000>; | ||
83 | interrupts = <1 9 0xf04>; | ||
84 | }; | 91 | }; |
85 | 92 | ||
86 | timer { | 93 | timer { |
@@ -91,22 +98,6 @@ | |||
91 | <1 10 0xf08>; | 98 | <1 10 0xf08>; |
92 | }; | 99 | }; |
93 | 100 | ||
94 | combiner:interrupt-controller@10440000 { | ||
95 | compatible = "samsung,exynos4210-combiner"; | ||
96 | #interrupt-cells = <2>; | ||
97 | interrupt-controller; | ||
98 | samsung,combiner-nr = <32>; | ||
99 | reg = <0x10440000 0x1000>; | ||
100 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
101 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
102 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
103 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, | ||
104 | <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, | ||
105 | <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, | ||
106 | <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, | ||
107 | <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; | ||
108 | }; | ||
109 | |||
110 | mct@101C0000 { | 101 | mct@101C0000 { |
111 | compatible = "samsung,exynos4210-mct"; | 102 | compatible = "samsung,exynos4210-mct"; |
112 | reg = <0x101C0000 0x800>; | 103 | reg = <0x101C0000 0x800>; |
@@ -168,9 +159,6 @@ | |||
168 | }; | 159 | }; |
169 | 160 | ||
170 | watchdog { | 161 | watchdog { |
171 | compatible = "samsung,s3c2410-wdt"; | ||
172 | reg = <0x101D0000 0x100>; | ||
173 | interrupts = <0 42 0>; | ||
174 | clocks = <&clock 336>; | 162 | clocks = <&clock 336>; |
175 | clock-names = "watchdog"; | 163 | clock-names = "watchdog"; |
176 | }; | 164 | }; |
@@ -183,12 +171,8 @@ | |||
183 | }; | 171 | }; |
184 | 172 | ||
185 | rtc { | 173 | rtc { |
186 | compatible = "samsung,s3c6410-rtc"; | ||
187 | reg = <0x101E0000 0x100>; | ||
188 | interrupts = <0 43 0>, <0 44 0>; | ||
189 | clocks = <&clock 337>; | 174 | clocks = <&clock 337>; |
190 | clock-names = "rtc"; | 175 | clock-names = "rtc"; |
191 | status = "disabled"; | ||
192 | }; | 176 | }; |
193 | 177 | ||
194 | tmu@10060000 { | 178 | tmu@10060000 { |
@@ -200,33 +184,21 @@ | |||
200 | }; | 184 | }; |
201 | 185 | ||
202 | serial@12C00000 { | 186 | serial@12C00000 { |
203 | compatible = "samsung,exynos4210-uart"; | ||
204 | reg = <0x12C00000 0x100>; | ||
205 | interrupts = <0 51 0>; | ||
206 | clocks = <&clock 289>, <&clock 146>; | 187 | clocks = <&clock 289>, <&clock 146>; |
207 | clock-names = "uart", "clk_uart_baud0"; | 188 | clock-names = "uart", "clk_uart_baud0"; |
208 | }; | 189 | }; |
209 | 190 | ||
210 | serial@12C10000 { | 191 | serial@12C10000 { |
211 | compatible = "samsung,exynos4210-uart"; | ||
212 | reg = <0x12C10000 0x100>; | ||
213 | interrupts = <0 52 0>; | ||
214 | clocks = <&clock 290>, <&clock 147>; | 192 | clocks = <&clock 290>, <&clock 147>; |
215 | clock-names = "uart", "clk_uart_baud0"; | 193 | clock-names = "uart", "clk_uart_baud0"; |
216 | }; | 194 | }; |
217 | 195 | ||
218 | serial@12C20000 { | 196 | serial@12C20000 { |
219 | compatible = "samsung,exynos4210-uart"; | ||
220 | reg = <0x12C20000 0x100>; | ||
221 | interrupts = <0 53 0>; | ||
222 | clocks = <&clock 291>, <&clock 148>; | 197 | clocks = <&clock 291>, <&clock 148>; |
223 | clock-names = "uart", "clk_uart_baud0"; | 198 | clock-names = "uart", "clk_uart_baud0"; |
224 | }; | 199 | }; |
225 | 200 | ||
226 | serial@12C30000 { | 201 | serial@12C30000 { |
227 | compatible = "samsung,exynos4210-uart"; | ||
228 | reg = <0x12C30000 0x100>; | ||
229 | interrupts = <0 54 0>; | ||
230 | clocks = <&clock 292>, <&clock 149>; | 202 | clocks = <&clock 292>, <&clock 149>; |
231 | clock-names = "uart", "clk_uart_baud0"; | 203 | clock-names = "uart", "clk_uart_baud0"; |
232 | }; | 204 | }; |
@@ -405,31 +377,19 @@ | |||
405 | }; | 377 | }; |
406 | 378 | ||
407 | dwmmc_0: dwmmc0@12200000 { | 379 | dwmmc_0: dwmmc0@12200000 { |
408 | compatible = "samsung,exynos5250-dw-mshc"; | ||
409 | reg = <0x12200000 0x1000>; | 380 | reg = <0x12200000 0x1000>; |
410 | interrupts = <0 75 0>; | ||
411 | #address-cells = <1>; | ||
412 | #size-cells = <0>; | ||
413 | clocks = <&clock 280>, <&clock 139>; | 381 | clocks = <&clock 280>, <&clock 139>; |
414 | clock-names = "biu", "ciu"; | 382 | clock-names = "biu", "ciu"; |
415 | }; | 383 | }; |
416 | 384 | ||
417 | dwmmc_1: dwmmc1@12210000 { | 385 | dwmmc_1: dwmmc1@12210000 { |
418 | compatible = "samsung,exynos5250-dw-mshc"; | ||
419 | reg = <0x12210000 0x1000>; | 386 | reg = <0x12210000 0x1000>; |
420 | interrupts = <0 76 0>; | ||
421 | #address-cells = <1>; | ||
422 | #size-cells = <0>; | ||
423 | clocks = <&clock 281>, <&clock 140>; | 387 | clocks = <&clock 281>, <&clock 140>; |
424 | clock-names = "biu", "ciu"; | 388 | clock-names = "biu", "ciu"; |
425 | }; | 389 | }; |
426 | 390 | ||
427 | dwmmc_2: dwmmc2@12220000 { | 391 | dwmmc_2: dwmmc2@12220000 { |
428 | compatible = "samsung,exynos5250-dw-mshc"; | ||
429 | reg = <0x12220000 0x1000>; | 392 | reg = <0x12220000 0x1000>; |
430 | interrupts = <0 77 0>; | ||
431 | #address-cells = <1>; | ||
432 | #size-cells = <0>; | ||
433 | clocks = <&clock 282>, <&clock 141>; | 393 | clocks = <&clock 282>, <&clock 141>; |
434 | clock-names = "biu", "ciu"; | 394 | clock-names = "biu", "ciu"; |
435 | }; | 395 | }; |
@@ -451,6 +411,10 @@ | |||
451 | &pdma0 9 | 411 | &pdma0 9 |
452 | &pdma0 8>; | 412 | &pdma0 8>; |
453 | dma-names = "tx", "rx", "tx-sec"; | 413 | dma-names = "tx", "rx", "tx-sec"; |
414 | clocks = <&clock_audss EXYNOS_I2S_BUS>, | ||
415 | <&clock_audss EXYNOS_I2S_BUS>, | ||
416 | <&clock_audss EXYNOS_SCLK_I2S>; | ||
417 | clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; | ||
454 | samsung,supports-6ch; | 418 | samsung,supports-6ch; |
455 | samsung,supports-rstclr; | 419 | samsung,supports-rstclr; |
456 | samsung,supports-secdai; | 420 | samsung,supports-secdai; |
@@ -465,6 +429,8 @@ | |||
465 | dmas = <&pdma1 12 | 429 | dmas = <&pdma1 12 |
466 | &pdma1 11>; | 430 | &pdma1 11>; |
467 | dma-names = "tx", "rx"; | 431 | dma-names = "tx", "rx"; |
432 | clocks = <&clock 307>, <&clock 157>; | ||
433 | clock-names = "iis", "i2s_opclk0"; | ||
468 | pinctrl-names = "default"; | 434 | pinctrl-names = "default"; |
469 | pinctrl-0 = <&i2s1_bus>; | 435 | pinctrl-0 = <&i2s1_bus>; |
470 | }; | 436 | }; |
@@ -475,10 +441,42 @@ | |||
475 | dmas = <&pdma0 12 | 441 | dmas = <&pdma0 12 |
476 | &pdma0 11>; | 442 | &pdma0 11>; |
477 | dma-names = "tx", "rx"; | 443 | dma-names = "tx", "rx"; |
444 | clocks = <&clock 308>, <&clock 158>; | ||
445 | clock-names = "iis", "i2s_opclk0"; | ||
478 | pinctrl-names = "default"; | 446 | pinctrl-names = "default"; |
479 | pinctrl-0 = <&i2s2_bus>; | 447 | pinctrl-0 = <&i2s2_bus>; |
480 | }; | 448 | }; |
481 | 449 | ||
450 | usb@12000000 { | ||
451 | compatible = "samsung,exynos5250-dwusb3"; | ||
452 | clocks = <&clock 286>; | ||
453 | clock-names = "usbdrd30"; | ||
454 | #address-cells = <1>; | ||
455 | #size-cells = <1>; | ||
456 | ranges; | ||
457 | |||
458 | dwc3 { | ||
459 | compatible = "synopsys,dwc3"; | ||
460 | reg = <0x12000000 0x10000>; | ||
461 | interrupts = <0 72 0>; | ||
462 | usb-phy = <&usb2_phy &usb3_phy>; | ||
463 | }; | ||
464 | }; | ||
465 | |||
466 | usb3_phy: usbphy@12100000 { | ||
467 | compatible = "samsung,exynos5250-usb3phy"; | ||
468 | reg = <0x12100000 0x100>; | ||
469 | clocks = <&clock 1>, <&clock 286>; | ||
470 | clock-names = "ext_xtal", "usbdrd30"; | ||
471 | #address-cells = <1>; | ||
472 | #size-cells = <1>; | ||
473 | ranges; | ||
474 | |||
475 | usbphy-sys { | ||
476 | reg = <0x10040704 0x8>; | ||
477 | }; | ||
478 | }; | ||
479 | |||
482 | usb@12110000 { | 480 | usb@12110000 { |
483 | compatible = "samsung,exynos4210-ehci"; | 481 | compatible = "samsung,exynos4210-ehci"; |
484 | reg = <0x12110000 0x100>; | 482 | reg = <0x12110000 0x100>; |
@@ -497,7 +495,7 @@ | |||
497 | clock-names = "usbhost"; | 495 | clock-names = "usbhost"; |
498 | }; | 496 | }; |
499 | 497 | ||
500 | usbphy@12130000 { | 498 | usb2_phy: usbphy@12130000 { |
501 | compatible = "samsung,exynos5250-usb2phy"; | 499 | compatible = "samsung,exynos5250-usb2phy"; |
502 | reg = <0x12130000 0x100>; | 500 | reg = <0x12130000 0x100>; |
503 | clocks = <&clock 1>, <&clock 285>; | 501 | clocks = <&clock 1>, <&clock 285>; |
@@ -621,6 +619,8 @@ | |||
621 | reg = <0x145b0000 0x1000>; | 619 | reg = <0x145b0000 0x1000>; |
622 | interrupts = <10 3>; | 620 | interrupts = <10 3>; |
623 | interrupt-parent = <&combiner>; | 621 | interrupt-parent = <&combiner>; |
622 | clocks = <&clock 342>; | ||
623 | clock-names = "dp"; | ||
624 | #address-cells = <1>; | 624 | #address-cells = <1>; |
625 | #size-cells = <0>; | 625 | #size-cells = <0>; |
626 | 626 | ||