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-rw-r--r--arch/arm/boot/dts/dra7.dtsi151
1 files changed, 151 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1fd75aa4639d..9e3caf3d19fb 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -47,6 +47,11 @@
47 1000000 1060000 47 1000000 1060000
48 1176000 1160000 48 1176000 1160000
49 >; 49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
50 }; 55 };
51 cpu@1 { 56 cpu@1 {
52 device_type = "cpu"; 57 device_type = "cpu";
@@ -464,6 +469,20 @@
464 ti,hwmods = "wd_timer2"; 469 ti,hwmods = "wd_timer2";
465 }; 470 };
466 471
472 hwspinlock: spinlock@4a0f6000 {
473 compatible = "ti,omap4-hwspinlock";
474 reg = <0x4a0f6000 0x1000>;
475 ti,hwmods = "spinlock";
476 #hwlock-cells = <1>;
477 };
478
479 dmm@4e000000 {
480 compatible = "ti,omap5-dmm";
481 reg = <0x4e000000 0x800>;
482 interrupts = <0 113 0x4>;
483 ti,hwmods = "dmm";
484 };
485
467 i2c1: i2c@48070000 { 486 i2c1: i2c@48070000 {
468 compatible = "ti,omap4-i2c"; 487 compatible = "ti,omap4-i2c";
469 reg = <0x48070000 0x100>; 488 reg = <0x48070000 0x100>;
@@ -559,6 +578,138 @@
559 status = "disabled"; 578 status = "disabled";
560 }; 579 };
561 580
581 abb_mpu: regulator-abb-mpu {
582 compatible = "ti,abb-v3";
583 regulator-name = "abb_mpu";
584 #address-cells = <0>;
585 #size-cells = <0>;
586 clocks = <&sys_clkin1>;
587 ti,settling-time = <50>;
588 ti,clock-cycles = <16>;
589
590 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
591 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
592 <0x4ae0c158 0x4>;
593 reg-names = "setup-address", "control-address",
594 "int-address", "efuse-address",
595 "ldo-address";
596 ti,tranxdone-status-mask = <0x80>;
597 /* LDOVBBMPU_FBB_MUX_CTRL */
598 ti,ldovbb-override-mask = <0x400>;
599 /* LDOVBBMPU_FBB_VSET_OUT */
600 ti,ldovbb-vset-mask = <0x1F>;
601
602 /*
603 * NOTE: only FBB mode used but actual vset will
604 * determine final biasing
605 */
606 ti,abb_info = <
607 /*uV ABB efuse rbb_m fbb_m vset_m*/
608 1060000 0 0x0 0 0x02000000 0x01F00000
609 1160000 0 0x4 0 0x02000000 0x01F00000
610 1210000 0 0x8 0 0x02000000 0x01F00000
611 >;
612 };
613
614 abb_ivahd: regulator-abb-ivahd {
615 compatible = "ti,abb-v3";
616 regulator-name = "abb_ivahd";
617 #address-cells = <0>;
618 #size-cells = <0>;
619 clocks = <&sys_clkin1>;
620 ti,settling-time = <50>;
621 ti,clock-cycles = <16>;
622
623 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
624 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
625 <0x4a002470 0x4>;
626 reg-names = "setup-address", "control-address",
627 "int-address", "efuse-address",
628 "ldo-address";
629 ti,tranxdone-status-mask = <0x40000000>;
630 /* LDOVBBIVA_FBB_MUX_CTRL */
631 ti,ldovbb-override-mask = <0x400>;
632 /* LDOVBBIVA_FBB_VSET_OUT */
633 ti,ldovbb-vset-mask = <0x1F>;
634
635 /*
636 * NOTE: only FBB mode used but actual vset will
637 * determine final biasing
638 */
639 ti,abb_info = <
640 /*uV ABB efuse rbb_m fbb_m vset_m*/
641 1055000 0 0x0 0 0x02000000 0x01F00000
642 1150000 0 0x4 0 0x02000000 0x01F00000
643 1250000 0 0x8 0 0x02000000 0x01F00000
644 >;
645 };
646
647 abb_dspeve: regulator-abb-dspeve {
648 compatible = "ti,abb-v3";
649 regulator-name = "abb_dspeve";
650 #address-cells = <0>;
651 #size-cells = <0>;
652 clocks = <&sys_clkin1>;
653 ti,settling-time = <50>;
654 ti,clock-cycles = <16>;
655
656 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
657 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
658 <0x4a00246c 0x4>;
659 reg-names = "setup-address", "control-address",
660 "int-address", "efuse-address",
661 "ldo-address";
662 ti,tranxdone-status-mask = <0x20000000>;
663 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
664 ti,ldovbb-override-mask = <0x400>;
665 /* LDOVBBDSPEVE_FBB_VSET_OUT */
666 ti,ldovbb-vset-mask = <0x1F>;
667
668 /*
669 * NOTE: only FBB mode used but actual vset will
670 * determine final biasing
671 */
672 ti,abb_info = <
673 /*uV ABB efuse rbb_m fbb_m vset_m*/
674 1055000 0 0x0 0 0x02000000 0x01F00000
675 1150000 0 0x4 0 0x02000000 0x01F00000
676 1250000 0 0x8 0 0x02000000 0x01F00000
677 >;
678 };
679
680 abb_gpu: regulator-abb-gpu {
681 compatible = "ti,abb-v3";
682 regulator-name = "abb_gpu";
683 #address-cells = <0>;
684 #size-cells = <0>;
685 clocks = <&sys_clkin1>;
686 ti,settling-time = <50>;
687 ti,clock-cycles = <16>;
688
689 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
690 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
691 <0x4ae0c154 0x4>;
692 reg-names = "setup-address", "control-address",
693 "int-address", "efuse-address",
694 "ldo-address";
695 ti,tranxdone-status-mask = <0x10000000>;
696 /* LDOVBBGPU_FBB_MUX_CTRL */
697 ti,ldovbb-override-mask = <0x400>;
698 /* LDOVBBGPU_FBB_VSET_OUT */
699 ti,ldovbb-vset-mask = <0x1F>;
700
701 /*
702 * NOTE: only FBB mode used but actual vset will
703 * determine final biasing
704 */
705 ti,abb_info = <
706 /*uV ABB efuse rbb_m fbb_m vset_m*/
707 1090000 0 0x0 0 0x02000000 0x01F00000
708 1210000 0 0x4 0 0x02000000 0x01F00000
709 1280000 0 0x8 0 0x02000000 0x01F00000
710 >;
711 };
712
562 mcspi1: spi@48098000 { 713 mcspi1: spi@48098000 {
563 compatible = "ti,omap4-mcspi"; 714 compatible = "ti,omap4-mcspi";
564 reg = <0x48098000 0x200>; 715 reg = <0x48098000 0x200>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 04:23:06 -0500