aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/dove.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/dove.dtsi')
-rw-r--r--arch/arm/boot/dts/dove.dtsi81
1 files changed, 78 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 5a00022383e7..f3f7e9d8adca 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -4,6 +4,12 @@
4 compatible = "marvell,dove"; 4 compatible = "marvell,dove";
5 model = "Marvell Armada 88AP510 SoC"; 5 model = "Marvell Armada 88AP510 SoC";
6 6
7 aliases {
8 gpio0 = &gpio0;
9 gpio1 = &gpio1;
10 gpio2 = &gpio2;
11 };
12
7 soc@f1000000 { 13 soc@f1000000 {
8 compatible = "simple-bus"; 14 compatible = "simple-bus";
9 #address-cells = <1>; 15 #address-cells = <1>;
@@ -31,6 +37,19 @@
31 reg = <0x20204 0x04>, <0x20214 0x04>; 37 reg = <0x20204 0x04>, <0x20214 0x04>;
32 }; 38 };
33 39
40 core_clk: core-clocks@d0214 {
41 compatible = "marvell,dove-core-clock";
42 reg = <0xd0214 0x4>;
43 #clock-cells = <1>;
44 };
45
46 gate_clk: clock-gating-control@d0038 {
47 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>;
50 #clock-cells = <1>;
51 };
52
34 uart0: serial@12000 { 53 uart0: serial@12000 {
35 compatible = "ns16550a"; 54 compatible = "ns16550a";
36 reg = <0x12000 0x100>; 55 reg = <0x12000 0x100>;
@@ -72,7 +91,8 @@
72 #gpio-cells = <2>; 91 #gpio-cells = <2>;
73 gpio-controller; 92 gpio-controller;
74 reg = <0xd0400 0x20>; 93 reg = <0xd0400 0x20>;
75 ngpio = <32>; 94 ngpios = <32>;
95 interrupt-controller;
76 interrupts = <12>, <13>, <14>, <60>; 96 interrupts = <12>, <13>, <14>, <60>;
77 }; 97 };
78 98
@@ -81,7 +101,8 @@
81 #gpio-cells = <2>; 101 #gpio-cells = <2>;
82 gpio-controller; 102 gpio-controller;
83 reg = <0xd0420 0x20>; 103 reg = <0xd0420 0x20>;
84 ngpio = <32>; 104 ngpios = <32>;
105 interrupt-controller;
85 interrupts = <61>; 106 interrupts = <61>;
86 }; 107 };
87 108
@@ -90,7 +111,12 @@
90 #gpio-cells = <2>; 111 #gpio-cells = <2>;
91 gpio-controller; 112 gpio-controller;
92 reg = <0xe8400 0x0c>; 113 reg = <0xe8400 0x0c>;
93 ngpio = <8>; 114 ngpios = <8>;
115 };
116
117 pinctrl: pinctrl@d0200 {
118 compatible = "marvell,dove-pinctrl";
119 reg = <0xd0200 0x10>;
94 }; 120 };
95 121
96 spi0: spi@10600 { 122 spi0: spi@10600 {
@@ -100,6 +126,7 @@
100 cell-index = <0>; 126 cell-index = <0>;
101 interrupts = <6>; 127 interrupts = <6>;
102 reg = <0x10600 0x28>; 128 reg = <0x10600 0x28>;
129 clocks = <&core_clk 0>;
103 status = "disabled"; 130 status = "disabled";
104 }; 131 };
105 132
@@ -110,6 +137,7 @@
110 cell-index = <1>; 137 cell-index = <1>;
111 interrupts = <5>; 138 interrupts = <5>;
112 reg = <0x14600 0x28>; 139 reg = <0x14600 0x28>;
140 clocks = <&core_clk 0>;
113 status = "disabled"; 141 status = "disabled";
114 }; 142 };
115 143
@@ -121,6 +149,7 @@
121 interrupts = <11>; 149 interrupts = <11>;
122 clock-frequency = <400000>; 150 clock-frequency = <400000>;
123 timeout-ms = <1000>; 151 timeout-ms = <1000>;
152 clocks = <&core_clk 0>;
124 status = "disabled"; 153 status = "disabled";
125 }; 154 };
126 155
@@ -128,6 +157,7 @@
128 compatible = "marvell,dove-sdhci"; 157 compatible = "marvell,dove-sdhci";
129 reg = <0x92000 0x100>; 158 reg = <0x92000 0x100>;
130 interrupts = <35>, <37>; 159 interrupts = <35>, <37>;
160 clocks = <&gate_clk 8>;
131 status = "disabled"; 161 status = "disabled";
132 }; 162 };
133 163
@@ -135,6 +165,7 @@
135 compatible = "marvell,dove-sdhci"; 165 compatible = "marvell,dove-sdhci";
136 reg = <0x90000 0x100>; 166 reg = <0x90000 0x100>;
137 interrupts = <36>, <38>; 167 interrupts = <36>, <38>;
168 clocks = <&gate_clk 9>;
138 status = "disabled"; 169 status = "disabled";
139 }; 170 };
140 171
@@ -142,6 +173,7 @@
142 compatible = "marvell,orion-sata"; 173 compatible = "marvell,orion-sata";
143 reg = <0xa0000 0x2400>; 174 reg = <0xa0000 0x2400>;
144 interrupts = <62>; 175 interrupts = <62>;
176 clocks = <&gate_clk 3>;
145 nr-ports = <1>; 177 nr-ports = <1>;
146 status = "disabled"; 178 status = "disabled";
147 }; 179 };
@@ -152,7 +184,50 @@
152 <0xc8000000 0x800>; 184 <0xc8000000 0x800>;
153 reg-names = "regs", "sram"; 185 reg-names = "regs", "sram";
154 interrupts = <31>; 186 interrupts = <31>;
187 clocks = <&gate_clk 15>;
188 status = "okay";
189 };
190
191 xor0: dma-engine@60800 {
192 compatible = "marvell,orion-xor";
193 reg = <0x60800 0x100
194 0x60a00 0x100>;
195 clocks = <&gate_clk 23>;
196 status = "okay";
197
198 channel0 {
199 interrupts = <39>;
200 dmacap,memcpy;
201 dmacap,xor;
202 };
203
204 channel1 {
205 interrupts = <40>;
206 dmacap,memset;
207 dmacap,memcpy;
208 dmacap,xor;
209 };
210 };
211
212 xor1: dma-engine@60900 {
213 compatible = "marvell,orion-xor";
214 reg = <0x60900 0x100
215 0x60b00 0x100>;
216 clocks = <&gate_clk 24>;
155 status = "okay"; 217 status = "okay";
218
219 channel0 {
220 interrupts = <42>;
221 dmacap,memcpy;
222 dmacap,xor;
223 };
224
225 channel1 {
226 interrupts = <43>;
227 dmacap,memset;
228 dmacap,memcpy;
229 dmacap,xor;
230 };
156 }; 231 };
157 }; 232 };
158}; 233};