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-rw-r--r--arch/arm/boot/dts/berlin2cd.dtsi167
1 files changed, 138 insertions, 29 deletions
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 094968c27533..cc1df65da504 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -12,6 +12,7 @@
12 */ 12 */
13 13
14#include "skeleton.dtsi" 14#include "skeleton.dtsi"
15#include <dt-bindings/clock/berlin2.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h>
16 17
17/ { 18/ {
@@ -30,24 +31,10 @@
30 }; 31 };
31 }; 32 };
32 33
33 clocks { 34 refclk: oscillator {
34 smclk: sysmgr-clock { 35 compatible = "fixed-clock";
35 compatible = "fixed-clock"; 36 #clock-cells = <0>;
36 #clock-cells = <0>; 37 clock-frequency = <25000000>;
37 clock-frequency = <25000000>;
38 };
39
40 cfgclk: cfg-clock {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <75000000>;
44 };
45
46 sysclk: system-clock {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <300000000>;
50 };
51 }; 38 };
52 39
53 soc { 40 soc {
@@ -76,7 +63,7 @@
76 compatible = "arm,cortex-a9-twd-timer"; 63 compatible = "arm,cortex-a9-twd-timer";
77 reg = <0xad0600 0x20>; 64 reg = <0xad0600 0x20>;
78 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; 65 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
79 clocks = <&sysclk>; 66 clocks = <&chip CLKID_TWD>;
80 }; 67 };
81 68
82 apb@e80000 { 69 apb@e80000 {
@@ -87,11 +74,83 @@
87 ranges = <0 0xe80000 0x10000>; 74 ranges = <0 0xe80000 0x10000>;
88 interrupt-parent = <&aic>; 75 interrupt-parent = <&aic>;
89 76
77 gpio0: gpio@0400 {
78 compatible = "snps,dw-apb-gpio";
79 reg = <0x0400 0x400>;
80 #address-cells = <1>;
81 #size-cells = <0>;
82
83 porta: gpio-port@0 {
84 compatible = "snps,dw-apb-gpio-port";
85 gpio-controller;
86 #gpio-cells = <2>;
87 snps,nr-gpios = <8>;
88 reg = <0>;
89 interrupt-controller;
90 #interrupt-cells = <2>;
91 interrupts = <0>;
92 };
93 };
94
95 gpio1: gpio@0800 {
96 compatible = "snps,dw-apb-gpio";
97 reg = <0x0800 0x400>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100
101 portb: gpio-port@1 {
102 compatible = "snps,dw-apb-gpio-port";
103 gpio-controller;
104 #gpio-cells = <2>;
105 snps,nr-gpios = <8>;
106 reg = <0>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 interrupts = <1>;
110 };
111 };
112
113 gpio2: gpio@0c00 {
114 compatible = "snps,dw-apb-gpio";
115 reg = <0x0c00 0x400>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 portc: gpio-port@2 {
120 compatible = "snps,dw-apb-gpio-port";
121 gpio-controller;
122 #gpio-cells = <2>;
123 snps,nr-gpios = <8>;
124 reg = <0>;
125 interrupt-controller;
126 #interrupt-cells = <2>;
127 interrupts = <2>;
128 };
129 };
130
131 gpio3: gpio@1000 {
132 compatible = "snps,dw-apb-gpio";
133 reg = <0x1000 0x400>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 portd: gpio-port@3 {
138 compatible = "snps,dw-apb-gpio-port";
139 gpio-controller;
140 #gpio-cells = <2>;
141 snps,nr-gpios = <8>;
142 reg = <0>;
143 interrupt-controller;
144 #interrupt-cells = <2>;
145 interrupts = <3>;
146 };
147 };
148
90 timer0: timer@2c00 { 149 timer0: timer@2c00 {
91 compatible = "snps,dw-apb-timer"; 150 compatible = "snps,dw-apb-timer";
92 reg = <0x2c00 0x14>; 151 reg = <0x2c00 0x14>;
93 interrupts = <8>; 152 interrupts = <8>;
94 clocks = <&cfgclk>; 153 clocks = <&chip CLKID_CFG>;
95 clock-names = "timer"; 154 clock-names = "timer";
96 status = "okay"; 155 status = "okay";
97 }; 156 };
@@ -100,7 +159,7 @@
100 compatible = "snps,dw-apb-timer"; 159 compatible = "snps,dw-apb-timer";
101 reg = <0x2c14 0x14>; 160 reg = <0x2c14 0x14>;
102 interrupts = <9>; 161 interrupts = <9>;
103 clocks = <&cfgclk>; 162 clocks = <&chip CLKID_CFG>;
104 clock-names = "timer"; 163 clock-names = "timer";
105 status = "okay"; 164 status = "okay";
106 }; 165 };
@@ -109,7 +168,7 @@
109 compatible = "snps,dw-apb-timer"; 168 compatible = "snps,dw-apb-timer";
110 reg = <0x2c28 0x14>; 169 reg = <0x2c28 0x14>;
111 interrupts = <10>; 170 interrupts = <10>;
112 clocks = <&cfgclk>; 171 clocks = <&chip CLKID_CFG>;
113 clock-names = "timer"; 172 clock-names = "timer";
114 status = "disabled"; 173 status = "disabled";
115 }; 174 };
@@ -118,7 +177,7 @@
118 compatible = "snps,dw-apb-timer"; 177 compatible = "snps,dw-apb-timer";
119 reg = <0x2c3c 0x14>; 178 reg = <0x2c3c 0x14>;
120 interrupts = <11>; 179 interrupts = <11>;
121 clocks = <&cfgclk>; 180 clocks = <&chip CLKID_CFG>;
122 clock-names = "timer"; 181 clock-names = "timer";
123 status = "disabled"; 182 status = "disabled";
124 }; 183 };
@@ -127,7 +186,7 @@
127 compatible = "snps,dw-apb-timer"; 186 compatible = "snps,dw-apb-timer";
128 reg = <0x2c50 0x14>; 187 reg = <0x2c50 0x14>;
129 interrupts = <12>; 188 interrupts = <12>;
130 clocks = <&cfgclk>; 189 clocks = <&chip CLKID_CFG>;
131 clock-names = "timer"; 190 clock-names = "timer";
132 status = "disabled"; 191 status = "disabled";
133 }; 192 };
@@ -136,7 +195,7 @@
136 compatible = "snps,dw-apb-timer"; 195 compatible = "snps,dw-apb-timer";
137 reg = <0x2c64 0x14>; 196 reg = <0x2c64 0x14>;
138 interrupts = <13>; 197 interrupts = <13>;
139 clocks = <&cfgclk>; 198 clocks = <&chip CLKID_CFG>;
140 clock-names = "timer"; 199 clock-names = "timer";
141 status = "disabled"; 200 status = "disabled";
142 }; 201 };
@@ -145,7 +204,7 @@
145 compatible = "snps,dw-apb-timer"; 204 compatible = "snps,dw-apb-timer";
146 reg = <0x2c78 0x14>; 205 reg = <0x2c78 0x14>;
147 interrupts = <14>; 206 interrupts = <14>;
148 clocks = <&cfgclk>; 207 clocks = <&chip CLKID_CFG>;
149 clock-names = "timer"; 208 clock-names = "timer";
150 status = "disabled"; 209 status = "disabled";
151 }; 210 };
@@ -154,7 +213,7 @@
154 compatible = "snps,dw-apb-timer"; 213 compatible = "snps,dw-apb-timer";
155 reg = <0x2c8c 0x14>; 214 reg = <0x2c8c 0x14>;
156 interrupts = <15>; 215 interrupts = <15>;
157 clocks = <&cfgclk>; 216 clocks = <&chip CLKID_CFG>;
158 clock-names = "timer"; 217 clock-names = "timer";
159 status = "disabled"; 218 status = "disabled";
160 }; 219 };
@@ -169,6 +228,19 @@
169 }; 228 };
170 }; 229 };
171 230
231 chip: chip-control@ea0000 {
232 compatible = "marvell,berlin2cd-chip-ctrl";
233 #clock-cells = <1>;
234 reg = <0xea0000 0x400>;
235 clocks = <&refclk>;
236 clock-names = "refclk";
237
238 uart0_pmux: uart0-pmux {
239 groups = "G6";
240 function = "uart0";
241 };
242 };
243
172 apb@fc0000 { 244 apb@fc0000 {
173 compatible = "simple-bus"; 245 compatible = "simple-bus";
174 #address-cells = <1>; 246 #address-cells = <1>;
@@ -177,13 +249,45 @@
177 ranges = <0 0xfc0000 0x10000>; 249 ranges = <0 0xfc0000 0x10000>;
178 interrupt-parent = <&sic>; 250 interrupt-parent = <&sic>;
179 251
252 sm_gpio1: gpio@5000 {
253 compatible = "snps,dw-apb-gpio";
254 reg = <0x5000 0x400>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 portf: gpio-port@5 {
259 compatible = "snps,dw-apb-gpio-port";
260 gpio-controller;
261 #gpio-cells = <2>;
262 snps,nr-gpios = <8>;
263 reg = <0>;
264 };
265 };
266
267 sm_gpio0: gpio@c000 {
268 compatible = "snps,dw-apb-gpio";
269 reg = <0xc000 0x400>;
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 porte: gpio-port@4 {
274 compatible = "snps,dw-apb-gpio-port";
275 gpio-controller;
276 #gpio-cells = <2>;
277 snps,nr-gpios = <8>;
278 reg = <0>;
279 };
280 };
281
180 uart0: serial@9000 { 282 uart0: serial@9000 {
181 compatible = "snps,dw-apb-uart"; 283 compatible = "snps,dw-apb-uart";
182 reg = <0x9000 0x100>; 284 reg = <0x9000 0x100>;
183 reg-shift = <2>; 285 reg-shift = <2>;
184 reg-io-width = <1>; 286 reg-io-width = <1>;
185 interrupts = <8>; 287 interrupts = <8>;
186 clocks = <&smclk>; 288 clocks = <&refclk>;
289 pinctrl-0 = <&uart0_pmux>;
290 pinctrl-names = "default";
187 status = "disabled"; 291 status = "disabled";
188 }; 292 };
189 293
@@ -193,10 +297,15 @@
193 reg-shift = <2>; 297 reg-shift = <2>;
194 reg-io-width = <1>; 298 reg-io-width = <1>;
195 interrupts = <9>; 299 interrupts = <9>;
196 clocks = <&smclk>; 300 clocks = <&refclk>;
197 status = "disabled"; 301 status = "disabled";
198 }; 302 };
199 303
304 sysctrl: system-controller@d000 {
305 compatible = "marvell,berlin2cd-system-ctrl";
306 reg = <0xd000 0x100>;
307 };
308
200 sic: interrupt-controller@e000 { 309 sic: interrupt-controller@e000 {
201 compatible = "snps,dw-apb-ictl"; 310 compatible = "snps,dw-apb-ictl";
202 reg = <0xe000 0x400>; 311 reg = <0xe000 0x400>;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 23:23:26 -0500