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Diffstat (limited to 'arch/arm/boot/dts/at91sam9x5.dtsi')
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi278
1 files changed, 245 insertions, 33 deletions
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 03fc136421c5..617ede541ca2 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -30,6 +30,7 @@
30 i2c0 = &i2c0; 30 i2c0 = &i2c0;
31 i2c1 = &i2c1; 31 i2c1 = &i2c1;
32 i2c2 = &i2c2; 32 i2c2 = &i2c2;
33 ssc0 = &ssc0;
33 }; 34 };
34 cpus { 35 cpus {
35 cpu@0 { 36 cpu@0 {
@@ -87,6 +88,13 @@
87 interrupts = <1 4 7>; 88 interrupts = <1 4 7>;
88 }; 89 };
89 90
91 ssc0: ssc@f0010000 {
92 compatible = "atmel,at91sam9g45-ssc";
93 reg = <0xf0010000 0x4000>;
94 interrupts = <28 4 5>;
95 status = "disable";
96 };
97
90 tcb0: timer@f8008000 { 98 tcb0: timer@f8008000 {
91 compatible = "atmel,at91sam9x5-tcb"; 99 compatible = "atmel,at91sam9x5-tcb";
92 reg = <0xf8008000 0x100>; 100 reg = <0xf8008000 0x100>;
@@ -111,50 +119,244 @@
111 interrupts = <21 4 0>; 119 interrupts = <21 4 0>;
112 }; 120 };
113 121
114 pioA: gpio@fffff400 { 122 pinctrl@fffff400 {
115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 123 #address-cells = <1>;
116 reg = <0xfffff400 0x100>; 124 #size-cells = <1>;
117 interrupts = <2 4 1>; 125 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
118 #gpio-cells = <2>; 126 ranges = <0xfffff400 0xfffff400 0x800>;
119 gpio-controller; 127
120 interrupt-controller; 128 /* shared pinctrl settings */
121 #interrupt-cells = <2>; 129 dbgu {
122 }; 130 pinctrl_dbgu: dbgu-0 {
131 atmel,pins =
132 <0 9 0x1 0x0 /* PA9 periph A */
133 0 10 0x1 0x1>; /* PA10 periph A with pullup */
134 };
135 };
123 136
124 pioB: gpio@fffff600 { 137 usart0 {
125 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 138 pinctrl_usart0: usart0-0 {
126 reg = <0xfffff600 0x100>; 139 atmel,pins =
127 interrupts = <2 4 1>; 140 <0 0 0x1 0x1 /* PA0 periph A with pullup */
128 #gpio-cells = <2>; 141 0 1 0x1 0x0>; /* PA1 periph A */
129 gpio-controller; 142 };
130 interrupt-controller; 143
131 #interrupt-cells = <2>; 144 pinctrl_usart0_rts: usart0_rts-0 {
145 atmel,pins =
146 <0 2 0x1 0x0>; /* PA2 periph A */
147 };
148
149 pinctrl_usart0_cts: usart0_cts-0 {
150 atmel,pins =
151 <0 3 0x1 0x0>; /* PA3 periph A */
152 };
153 };
154
155 usart1 {
156 pinctrl_usart1: usart1-0 {
157 atmel,pins =
158 <0 5 0x1 0x1 /* PA5 periph A with pullup */
159 0 6 0x1 0x0>; /* PA6 periph A */
160 };
161
162 pinctrl_usart1_rts: usart1_rts-0 {
163 atmel,pins =
164 <3 27 0x3 0x0>; /* PC27 periph C */
165 };
166
167 pinctrl_usart1_cts: usart1_cts-0 {
168 atmel,pins =
169 <3 28 0x3 0x0>; /* PC28 periph C */
170 };
171 };
172
173 usart2 {
174 pinctrl_usart2: usart2-0 {
175 atmel,pins =
176 <0 7 0x1 0x1 /* PA7 periph A with pullup */
177 0 8 0x1 0x0>; /* PA8 periph A */
178 };
179
180 pinctrl_uart2_rts: uart2_rts-0 {
181 atmel,pins =
182 <0 0 0x2 0x0>; /* PB0 periph B */
183 };
184
185 pinctrl_uart2_cts: uart2_cts-0 {
186 atmel,pins =
187 <0 1 0x2 0x0>; /* PB1 periph B */
188 };
189 };
190
191 usart3 {
192 pinctrl_uart3: usart3-0 {
193 atmel,pins =
194 <3 23 0x2 0x1 /* PC22 periph B with pullup */
195 3 23 0x2 0x0>; /* PC23 periph B */
196 };
197
198 pinctrl_usart3_rts: usart3_rts-0 {
199 atmel,pins =
200 <3 24 0x2 0x0>; /* PC24 periph B */
201 };
202
203 pinctrl_usart3_cts: usart3_cts-0 {
204 atmel,pins =
205 <3 25 0x2 0x0>; /* PC25 periph B */
206 };
207 };
208
209 uart0 {
210 pinctrl_uart0: uart0-0 {
211 atmel,pins =
212 <3 8 0x3 0x0 /* PC8 periph C */
213 3 9 0x3 0x1>; /* PC9 periph C with pullup */
214 };
215 };
216
217 uart1 {
218 pinctrl_uart1: uart1-0 {
219 atmel,pins =
220 <3 16 0x3 0x0 /* PC16 periph C */
221 3 17 0x3 0x1>; /* PC17 periph C with pullup */
222 };
223 };
224
225 nand {
226 pinctrl_nand: nand-0 {
227 atmel,pins =
228 <3 4 0x0 0x1 /* PD5 gpio RDY pin pull_up */
229 3 5 0x0 0x1>; /* PD4 gpio enable pin pull_up */
230 };
231 };
232
233 macb0 {
234 pinctrl_macb0_rmii: macb0_rmii-0 {
235 atmel,pins =
236 <1 0 0x1 0x0 /* PB0 periph A */
237 1 1 0x1 0x0 /* PB1 periph A */
238 1 2 0x1 0x0 /* PB2 periph A */
239 1 3 0x1 0x0 /* PB3 periph A */
240 1 4 0x1 0x0 /* PB4 periph A */
241 1 5 0x1 0x0 /* PB5 periph A */
242 1 6 0x1 0x0 /* PB6 periph A */
243 1 7 0x1 0x0 /* PB7 periph A */
244 1 9 0x1 0x0 /* PB9 periph A */
245 1 10 0x1 0x0>; /* PB10 periph A */
246 };
247
248 pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
249 atmel,pins =
250 <1 8 0x1 0x0 /* PA8 periph A */
251 1 11 0x1 0x0 /* PA11 periph A */
252 1 12 0x1 0x0 /* PA12 periph A */
253 1 13 0x1 0x0 /* PA13 periph A */
254 1 14 0x1 0x0 /* PA14 periph A */
255 1 15 0x1 0x0 /* PA15 periph A */
256 1 16 0x1 0x0 /* PA16 periph A */
257 1 17 0x1 0x0>; /* PA17 periph A */
258 };
259 };
260
261 mmc0 {
262 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
263 atmel,pins =
264 <0 17 0x1 0x0 /* PA17 periph A */
265 0 16 0x1 0x1 /* PA16 periph A with pullup */
266 0 15 0x1 0x1>; /* PA15 periph A with pullup */
267 };
268
269 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
270 atmel,pins =
271 <0 18 0x1 0x1 /* PA18 periph A with pullup */
272 0 19 0x1 0x1 /* PA19 periph A with pullup */
273 0 20 0x1 0x1>; /* PA20 periph A with pullup */
274 };
275 };
276
277 mmc1 {
278 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
279 atmel,pins =
280 <0 13 0x2 0x0 /* PA13 periph B */
281 0 12 0x2 0x1 /* PA12 periph B with pullup */
282 0 11 0x2 0x1>; /* PA11 periph B with pullup */
283 };
284
285 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
286 atmel,pins =
287 <0 2 0x2 0x1 /* PA2 periph B with pullup */
288 0 3 0x2 0x1 /* PA3 periph B with pullup */
289 0 4 0x2 0x1>; /* PA4 periph B with pullup */
290 };
291 };
292
293 pioA: gpio@fffff400 {
294 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
295 reg = <0xfffff400 0x200>;
296 interrupts = <2 4 1>;
297 #gpio-cells = <2>;
298 gpio-controller;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 pioB: gpio@fffff600 {
304 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
305 reg = <0xfffff600 0x200>;
306 interrupts = <2 4 1>;
307 #gpio-cells = <2>;
308 gpio-controller;
309 #gpio-lines = <19>;
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 pioC: gpio@fffff800 {
315 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
316 reg = <0xfffff800 0x200>;
317 interrupts = <3 4 1>;
318 #gpio-cells = <2>;
319 gpio-controller;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 };
323
324 pioD: gpio@fffffa00 {
325 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
326 reg = <0xfffffa00 0x200>;
327 interrupts = <3 4 1>;
328 #gpio-cells = <2>;
329 gpio-controller;
330 #gpio-lines = <22>;
331 interrupt-controller;
332 #interrupt-cells = <2>;
333 };
132 }; 334 };
133 335
134 pioC: gpio@fffff800 { 336 mmc0: mmc@f0008000 {
135 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 337 compatible = "atmel,hsmci";
136 reg = <0xfffff800 0x100>; 338 reg = <0xf0008000 0x600>;
137 interrupts = <3 4 1>; 339 interrupts = <12 4 0>;
138 #gpio-cells = <2>; 340 #address-cells = <1>;
139 gpio-controller; 341 #size-cells = <0>;
140 interrupt-controller; 342 status = "disabled";
141 #interrupt-cells = <2>;
142 }; 343 };
143 344
144 pioD: gpio@fffffa00 { 345 mmc1: mmc@f000c000 {
145 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 346 compatible = "atmel,hsmci";
146 reg = <0xfffffa00 0x100>; 347 reg = <0xf000c000 0x600>;
147 interrupts = <3 4 1>; 348 interrupts = <26 4 0>;
148 #gpio-cells = <2>; 349 #address-cells = <1>;
149 gpio-controller; 350 #size-cells = <0>;
150 interrupt-controller; 351 status = "disabled";
151 #interrupt-cells = <2>;
152 }; 352 };
153 353
154 dbgu: serial@fffff200 { 354 dbgu: serial@fffff200 {
155 compatible = "atmel,at91sam9260-usart"; 355 compatible = "atmel,at91sam9260-usart";
156 reg = <0xfffff200 0x200>; 356 reg = <0xfffff200 0x200>;
157 interrupts = <1 4 7>; 357 interrupts = <1 4 7>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_dbgu>;
158 status = "disabled"; 360 status = "disabled";
159 }; 361 };
160 362
@@ -164,6 +366,8 @@
164 interrupts = <5 4 5>; 366 interrupts = <5 4 5>;
165 atmel,use-dma-rx; 367 atmel,use-dma-rx;
166 atmel,use-dma-tx; 368 atmel,use-dma-tx;
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_usart0>;
167 status = "disabled"; 371 status = "disabled";
168 }; 372 };
169 373
@@ -173,6 +377,8 @@
173 interrupts = <6 4 5>; 377 interrupts = <6 4 5>;
174 atmel,use-dma-rx; 378 atmel,use-dma-rx;
175 atmel,use-dma-tx; 379 atmel,use-dma-tx;
380 pinctrl-names = "default";
381 pinctrl-0 = <&pinctrl_usart1>;
176 status = "disabled"; 382 status = "disabled";
177 }; 383 };
178 384
@@ -182,6 +388,8 @@
182 interrupts = <7 4 5>; 388 interrupts = <7 4 5>;
183 atmel,use-dma-rx; 389 atmel,use-dma-rx;
184 atmel,use-dma-tx; 390 atmel,use-dma-tx;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_usart2>;
185 status = "disabled"; 393 status = "disabled";
186 }; 394 };
187 395
@@ -189,6 +397,8 @@
189 compatible = "cdns,at32ap7000-macb", "cdns,macb"; 397 compatible = "cdns,at32ap7000-macb", "cdns,macb";
190 reg = <0xf802c000 0x100>; 398 reg = <0xf802c000 0x100>;
191 interrupts = <24 4 3>; 399 interrupts = <24 4 3>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_macb0_rmii>;
192 status = "disabled"; 402 status = "disabled";
193 }; 403 };
194 404
@@ -273,6 +483,8 @@
273 >; 483 >;
274 atmel,nand-addr-offset = <21>; 484 atmel,nand-addr-offset = <21>;
275 atmel,nand-cmd-offset = <22>; 485 atmel,nand-cmd-offset = <22>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_nand>;
276 gpios = <&pioD 5 0 488 gpios = <&pioD 5 0
277 &pioD 4 0 489 &pioD 4 0
278 0 490 0