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Diffstat (limited to 'arch/arm/boot/dts/armada-xp-mv78460.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi58
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index b9da5b8ae288..ce4f80a82854 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -62,7 +62,7 @@
62 soc { 62 soc {
63 pinctrl { 63 pinctrl {
64 compatible = "marvell,mv78460-pinctrl"; 64 compatible = "marvell,mv78460-pinctrl";
65 reg = <0xd0018000 0x38>; 65 reg = <0x18000 0x38>;
66 66
67 sdio_pins: sdio-pins { 67 sdio_pins: sdio-pins {
68 marvell,pins = "mpp30", "mpp31", "mpp32", 68 marvell,pins = "mpp30", "mpp31", "mpp32",
@@ -71,9 +71,9 @@
71 }; 71 };
72 }; 72 };
73 73
74 gpio0: gpio@d0018100 { 74 gpio0: gpio@18100 {
75 compatible = "marvell,orion-gpio"; 75 compatible = "marvell,orion-gpio";
76 reg = <0xd0018100 0x40>; 76 reg = <0x18100 0x40>;
77 ngpios = <32>; 77 ngpios = <32>;
78 gpio-controller; 78 gpio-controller;
79 #gpio-cells = <2>; 79 #gpio-cells = <2>;
@@ -82,9 +82,9 @@
82 interrupts = <82>, <83>, <84>, <85>; 82 interrupts = <82>, <83>, <84>, <85>;
83 }; 83 };
84 84
85 gpio1: gpio@d0018140 { 85 gpio1: gpio@18140 {
86 compatible = "marvell,orion-gpio"; 86 compatible = "marvell,orion-gpio";
87 reg = <0xd0018140 0x40>; 87 reg = <0x18140 0x40>;
88 ngpios = <32>; 88 ngpios = <32>;
89 gpio-controller; 89 gpio-controller;
90 #gpio-cells = <2>; 90 #gpio-cells = <2>;
@@ -93,9 +93,9 @@
93 interrupts = <87>, <88>, <89>, <90>; 93 interrupts = <87>, <88>, <89>, <90>;
94 }; 94 };
95 95
96 gpio2: gpio@d0018180 { 96 gpio2: gpio@18180 {
97 compatible = "marvell,orion-gpio"; 97 compatible = "marvell,orion-gpio";
98 reg = <0xd0018180 0x40>; 98 reg = <0x18180 0x40>;
99 ngpios = <3>; 99 ngpios = <3>;
100 gpio-controller; 100 gpio-controller;
101 #gpio-cells = <2>; 101 #gpio-cells = <2>;
@@ -104,9 +104,9 @@
104 interrupts = <91>; 104 interrupts = <91>;
105 }; 105 };
106 106
107 ethernet@d0034000 { 107 ethernet@34000 {
108 compatible = "marvell,armada-370-neta"; 108 compatible = "marvell,armada-370-neta";
109 reg = <0xd0034000 0x2500>; 109 reg = <0x34000 0x2500>;
110 interrupts = <14>; 110 interrupts = <14>;
111 clocks = <&gateclk 1>; 111 clocks = <&gateclk 1>;
112 status = "disabled"; 112 status = "disabled";
@@ -127,22 +127,22 @@
127 127
128 bus-range = <0x00 0xff>; 128 bus-range = <0x00 0xff>;
129 129
130 ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */ 130 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
131 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */ 131 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
132 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */ 132 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
133 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */ 133 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
134 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */ 134 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
135 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */ 135 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
136 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */ 136 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
137 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */ 137 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
138 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */ 138 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
139 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */ 139 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 140 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ 141 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
142 142
143 pcie@1,0 { 143 pcie@1,0 {
144 device_type = "pci"; 144 device_type = "pci";
145 assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>; 145 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
146 reg = <0x0800 0 0 0 0>; 146 reg = <0x0800 0 0 0 0>;
147 #address-cells = <3>; 147 #address-cells = <3>;
148 #size-cells = <2>; 148 #size-cells = <2>;
@@ -158,7 +158,7 @@
158 158
159 pcie@2,0 { 159 pcie@2,0 {
160 device_type = "pci"; 160 device_type = "pci";
161 assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>; 161 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
162 reg = <0x1000 0 0 0 0>; 162 reg = <0x1000 0 0 0 0>;
163 #address-cells = <3>; 163 #address-cells = <3>;
164 #size-cells = <2>; 164 #size-cells = <2>;
@@ -174,7 +174,7 @@
174 174
175 pcie@3,0 { 175 pcie@3,0 {
176 device_type = "pci"; 176 device_type = "pci";
177 assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>; 177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
178 reg = <0x1800 0 0 0 0>; 178 reg = <0x1800 0 0 0 0>;
179 #address-cells = <3>; 179 #address-cells = <3>;
180 #size-cells = <2>; 180 #size-cells = <2>;
@@ -190,7 +190,7 @@
190 190
191 pcie@4,0 { 191 pcie@4,0 {
192 device_type = "pci"; 192 device_type = "pci";
193 assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>; 193 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
194 reg = <0x2000 0 0 0 0>; 194 reg = <0x2000 0 0 0 0>;
195 #address-cells = <3>; 195 #address-cells = <3>;
196 #size-cells = <2>; 196 #size-cells = <2>;
@@ -206,7 +206,7 @@
206 206
207 pcie@5,0 { 207 pcie@5,0 {
208 device_type = "pci"; 208 device_type = "pci";
209 assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>; 209 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
210 reg = <0x2800 0 0 0 0>; 210 reg = <0x2800 0 0 0 0>;
211 #address-cells = <3>; 211 #address-cells = <3>;
212 #size-cells = <2>; 212 #size-cells = <2>;
@@ -222,7 +222,7 @@
222 222
223 pcie@6,0 { 223 pcie@6,0 {
224 device_type = "pci"; 224 device_type = "pci";
225 assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>; 225 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
226 reg = <0x3000 0 0 0 0>; 226 reg = <0x3000 0 0 0 0>;
227 #address-cells = <3>; 227 #address-cells = <3>;
228 #size-cells = <2>; 228 #size-cells = <2>;
@@ -238,7 +238,7 @@
238 238
239 pcie@7,0 { 239 pcie@7,0 {
240 device_type = "pci"; 240 device_type = "pci";
241 assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>; 241 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
242 reg = <0x3800 0 0 0 0>; 242 reg = <0x3800 0 0 0 0>;
243 #address-cells = <3>; 243 #address-cells = <3>;
244 #size-cells = <2>; 244 #size-cells = <2>;
@@ -254,7 +254,7 @@
254 254
255 pcie@8,0 { 255 pcie@8,0 {
256 device_type = "pci"; 256 device_type = "pci";
257 assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>; 257 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
258 reg = <0x4000 0 0 0 0>; 258 reg = <0x4000 0 0 0 0>;
259 #address-cells = <3>; 259 #address-cells = <3>;
260 #size-cells = <2>; 260 #size-cells = <2>;
@@ -269,7 +269,7 @@
269 }; 269 };
270 pcie@9,0 { 270 pcie@9,0 {
271 device_type = "pci"; 271 device_type = "pci";
272 assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>; 272 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
273 reg = <0x4800 0 0 0 0>; 273 reg = <0x4800 0 0 0 0>;
274 #address-cells = <3>; 274 #address-cells = <3>;
275 #size-cells = <2>; 275 #size-cells = <2>;
@@ -285,7 +285,7 @@
285 285
286 pcie@10,0 { 286 pcie@10,0 {
287 device_type = "pci"; 287 device_type = "pci";
288 assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>; 288 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
289 reg = <0x5000 0 0 0 0>; 289 reg = <0x5000 0 0 0 0>;
290 #address-cells = <3>; 290 #address-cells = <3>;
291 #size-cells = <2>; 291 #size-cells = <2>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 22:18:12 -0500