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Diffstat (limited to 'arch/arm/boot/dts/armada-xp-mv78230.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi228
1 files changed, 121 insertions, 107 deletions
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..0358a33cba48 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78230 SoC"; 19 model = "Marvell Armada XP MV78230 SoC";
@@ -44,6 +44,124 @@
44 }; 44 };
45 45
46 soc { 46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1.
51 */
52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 bus-range = <0x00 0xff>;
61
62 ranges =
63 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
64 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
69 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
70 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
71 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
72 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
73 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
74 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
75 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
76 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
77 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
78
79 pcie@1,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
82 reg = <0x0800 0 0 0 0>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85 #interrupt-cells = <1>;
86 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
87 0x81000000 0 0 0x81000000 0x1 0 1 0>;
88 interrupt-map-mask = <0 0 0 0>;
89 interrupt-map = <0 0 0 0 &mpic 58>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94 };
95
96 pcie@2,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
99 reg = <0x1000 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 59>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <1>;
109 clocks = <&gateclk 6>;
110 status = "disabled";
111 };
112
113 pcie@3,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
116 reg = <0x1800 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
121 0x81000000 0 0 0x81000000 0x3 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 60>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <2>;
126 clocks = <&gateclk 7>;
127 status = "disabled";
128 };
129
130 pcie@4,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
133 reg = <0x2000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
138 0x81000000 0 0 0x81000000 0x4 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 61>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <3>;
143 clocks = <&gateclk 8>;
144 status = "disabled";
145 };
146
147 pcie@9,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
150 reg = <0x4800 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
155 0x81000000 0 0 0x81000000 0x9 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 99>;
158 marvell,pcie-port = <2>;
159 marvell,pcie-lane = <0>;
160 clocks = <&gateclk 26>;
161 status = "disabled";
162 };
163 };
164
47 internal-regs { 165 internal-regs {
48 pinctrl { 166 pinctrl {
49 compatible = "marvell,mv78230-pinctrl"; 167 compatible = "marvell,mv78230-pinctrl";
@@ -63,7 +181,7 @@
63 gpio-controller; 181 gpio-controller;
64 #gpio-cells = <2>; 182 #gpio-cells = <2>;
65 interrupt-controller; 183 interrupt-controller;
66 #interrupts-cells = <2>; 184 #interrupt-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 185 interrupts = <82>, <83>, <84>, <85>;
68 }; 186 };
69 187
@@ -74,113 +192,9 @@
74 gpio-controller; 192 gpio-controller;
75 #gpio-cells = <2>; 193 #gpio-cells = <2>;
76 interrupt-controller; 194 interrupt-controller;
77 #interrupts-cells = <2>; 195 #interrupt-cells = <2>;
78 interrupts = <87>, <88>, <89>; 196 interrupts = <87>, <88>, <89>;
79 }; 197 };
80
81 /*
82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
83 * configured as x4 or quad x1 lanes. One unit is
84 * x4/x1.
85 */
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
88 status = "disabled";
89 device_type = "pci";
90
91#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
183 };
184 }; 198 };
185 }; 199 };
186}; 200};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 04:41:44 -0500