1 files changed, 50 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 1c8afe2ffebc..04f28a712b98 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -109,5 +109,55 @@
                                 spi-max-frequency = <108000000>;
                         };
                 };
+
+                devbus-bootcs@d0010400 {
+                        status = "okay";
+                        ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
+
+                        /* Device Bus parameters are required */
+
+                        /* Read parameters */
+                        devbus,bus-width    = <8>;
+                        devbus,turn-off-ps  = <60000>;
+                        devbus,badr-skew-ps = <0>;
+                        devbus,acc-first-ps = <124000>;
+                        devbus,acc-next-ps  = <248000>;
+                        devbus,rd-setup-ps  = <0>;
+                        devbus,rd-hold-ps   = <0>;
+
+                        /* Write parameters */
+                        devbus,sync-enable = <0>;
+                        devbus,wr-high-ps  = <60000>;
+                        devbus,wr-low-ps   = <60000>;
+                        devbus,ale-wr-ps   = <60000>;
+
+                        /* NOR 16 MiB */
+                        nor@0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0x1000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        /*
+                         * The 3 slots are physically present as
+                         * standard PCIe slots on the board.
+                         */
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@9,0 {
+                                /* Port 2, Lane 0 */
+                                status = "okay";
+                        };
+                        pcie@10,0 {
+                                /* Port 3, Lane 0 */
+                                status = "okay";
+                        };
+                };
         };
 };