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Diffstat (limited to 'arch/arm/boot/dts/am437x-gp-evm.dts')
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts229
1 files changed, 229 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index a055f7f0f14a..c25d15837ce9 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -27,6 +27,17 @@
27 enable-active-high; 27 enable-active-high;
28 }; 28 };
29 29
30 vtt_fixed: fixedregulator-vtt {
31 compatible = "regulator-fixed";
32 regulator-name = "vtt_fixed";
33 regulator-min-microvolt = <1500000>;
34 regulator-max-microvolt = <1500000>;
35 regulator-always-on;
36 regulator-boot-on;
37 enable-active-high;
38 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
39 };
40
30 backlight { 41 backlight {
31 compatible = "pwm-backlight"; 42 compatible = "pwm-backlight";
32 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 43 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@@ -81,6 +92,85 @@
81 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 92 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
82 >; 93 >;
83 }; 94 };
95
96 pixcir_ts_pins: pixcir_ts_pins {
97 pinctrl-single,pins = <
98 0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
99 >;
100 };
101
102 cpsw_default: cpsw_default {
103 pinctrl-single,pins = <
104 /* Slave 1 */
105 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
106 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
107 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
108 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
109 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
110 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
111 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
112 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
113 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
114 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
115 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
116 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
117 >;
118 };
119
120 cpsw_sleep: cpsw_sleep {
121 pinctrl-single,pins = <
122 /* Slave 1 reset value */
123 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 >;
136 };
137
138 davinci_mdio_default: davinci_mdio_default {
139 pinctrl-single,pins = <
140 /* MDIO */
141 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
142 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
143 >;
144 };
145
146 davinci_mdio_sleep: davinci_mdio_sleep {
147 pinctrl-single,pins = <
148 /* MDIO reset value */
149 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
151 >;
152 };
153
154 nand_flash_x8: nand_flash_x8 {
155 pinctrl-single,pins = <
156 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
157 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
158 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
159 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
160 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
161 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
162 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
163 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
164 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
165 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
166 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
167 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
168 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
169 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
170 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
171 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
172 >;
173 };
84}; 174};
85 175
86&i2c0 { 176&i2c0 {
@@ -93,6 +183,20 @@
93 status = "okay"; 183 status = "okay";
94 pinctrl-names = "default"; 184 pinctrl-names = "default";
95 pinctrl-0 = <&i2c1_pins>; 185 pinctrl-0 = <&i2c1_pins>;
186
187 pixcir_ts@5c {
188 compatible = "pixcir,pixcir_tangoc";
189 pinctrl-names = "default";
190 pinctrl-0 = <&pixcir_ts_pins>;
191 reg = <0x5c>;
192 interrupt-parent = <&gpio3>;
193 interrupts = <22 0>;
194
195 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
196
197 x-size = <1024>;
198 y-size = <600>;
199 };
96}; 200};
97 201
98&epwmss0 { 202&epwmss0 {
@@ -130,3 +234,128 @@
130 pinctrl-0 = <&mmc1_pins>; 234 pinctrl-0 = <&mmc1_pins>;
131 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 235 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
132}; 236};
237
238&usb2_phy1 {
239 status = "okay";
240};
241
242&usb1 {
243 dr_mode = "peripheral";
244 status = "okay";
245};
246
247&usb2_phy2 {
248 status = "okay";
249};
250
251&usb2 {
252 dr_mode = "host";
253 status = "okay";
254};
255
256&mac {
257 slaves = <1>;
258 pinctrl-names = "default", "sleep";
259 pinctrl-0 = <&cpsw_default>;
260 pinctrl-1 = <&cpsw_sleep>;
261 status = "okay";
262};
263
264&davinci_mdio {
265 pinctrl-names = "default", "sleep";
266 pinctrl-0 = <&davinci_mdio_default>;
267 pinctrl-1 = <&davinci_mdio_sleep>;
268 status = "okay";
269};
270
271&cpsw_emac0 {
272 phy_id = <&davinci_mdio>, <0>;
273 phy-mode = "rgmii";
274};
275
276&elm {
277 status = "okay";
278};
279
280&gpmc {
281 status = "okay";
282 pinctrl-names = "default";
283 pinctrl-0 = <&nand_flash_x8>;
284 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
285 nand@0,0 {
286 reg = <0 0 4>; /* device IO registers */
287 ti,nand-ecc-opt = "bch8";
288 ti,elm-id = <&elm>;
289 nand-bus-width = <8>;
290 gpmc,device-width = <1>;
291 gpmc,sync-clk-ps = <0>;
292 gpmc,cs-on-ns = <0>;
293 gpmc,cs-rd-off-ns = <40>;
294 gpmc,cs-wr-off-ns = <40>;
295 gpmc,adv-on-ns = <0>;
296 gpmc,adv-rd-off-ns = <25>;
297 gpmc,adv-wr-off-ns = <25>;
298 gpmc,we-on-ns = <0>;
299 gpmc,we-off-ns = <20>;
300 gpmc,oe-on-ns = <3>;
301 gpmc,oe-off-ns = <30>;
302 gpmc,access-ns = <30>;
303 gpmc,rd-cycle-ns = <40>;
304 gpmc,wr-cycle-ns = <40>;
305 gpmc,wait-pin = <0>;
306 gpmc,wait-on-read;
307 gpmc,wait-on-write;
308 gpmc,bus-turnaround-ns = <0>;
309 gpmc,cycle2cycle-delay-ns = <0>;
310 gpmc,clk-activation-ns = <0>;
311 gpmc,wait-monitoring-ns = <0>;
312 gpmc,wr-access-ns = <40>;
313 gpmc,wr-data-mux-bus-ns = <0>;
314 /* MTD partition table */
315 /* All SPL-* partitions are sized to minimal length
316 * which can be independently programmable. For
317 * NAND flash this is equal to size of erase-block */
318 #address-cells = <1>;
319 #size-cells = <1>;
320 partition@0 {
321 label = "NAND.SPL";
322 reg = <0x00000000 0x00040000>;
323 };
324 partition@1 {
325 label = "NAND.SPL.backup1";
326 reg = <0x00040000 0x00040000>;
327 };
328 partition@2 {
329 label = "NAND.SPL.backup2";
330 reg = <0x00080000 0x00040000>;
331 };
332 partition@3 {
333 label = "NAND.SPL.backup3";
334 reg = <0x000c0000 0x00040000>;
335 };
336 partition@4 {
337 label = "NAND.u-boot-spl-os";
338 reg = <0x00100000 0x00080000>;
339 };
340 partition@5 {
341 label = "NAND.u-boot";
342 reg = <0x00180000 0x00100000>;
343 };
344 partition@6 {
345 label = "NAND.u-boot-env";
346 reg = <0x00280000 0x00040000>;
347 };
348 partition@7 {
349 label = "NAND.u-boot-env.backup1";
350 reg = <0x002c0000 0x00040000>;
351 };
352 partition@8 {
353 label = "NAND.kernel";
354 reg = <0x00300000 0x00700000>;
355 };
356 partition@9 {
357 label = "NAND.file-system";
358 reg = <0x00a00000 0x1f600000>;
359 };
360 };
361};
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 22:05:44 -0400