diff options
Diffstat (limited to 'arch/arm/boot/dts/am33xx-clocks.dtsi')
-rw-r--r-- | arch/arm/boot/dts/am33xx-clocks.dtsi | 30 |
1 files changed, 6 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 9ccfe508dea2..712edce7d6fb 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi | |||
@@ -96,47 +96,29 @@ | |||
96 | clock-div = <1>; | 96 | clock-div = <1>; |
97 | }; | 97 | }; |
98 | 98 | ||
99 | ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { | 99 | ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { |
100 | #clock-cells = <0>; | 100 | #clock-cells = <0>; |
101 | compatible = "ti,composite-no-wait-gate-clock"; | 101 | compatible = "ti,gate-clock"; |
102 | clocks = <&dpll_per_m2_ck>; | 102 | clocks = <&dpll_per_m2_ck>; |
103 | ti,bit-shift = <0>; | 103 | ti,bit-shift = <0>; |
104 | reg = <0x0664>; | 104 | reg = <0x0664>; |
105 | }; | 105 | }; |
106 | 106 | ||
107 | ehrpwm0_tbclk: ehrpwm0_tbclk { | 107 | ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { |
108 | #clock-cells = <0>; | ||
109 | compatible = "ti,composite-clock"; | ||
110 | clocks = <&ehrpwm0_gate_tbclk>; | ||
111 | }; | ||
112 | |||
113 | ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { | ||
114 | #clock-cells = <0>; | 108 | #clock-cells = <0>; |
115 | compatible = "ti,composite-no-wait-gate-clock"; | 109 | compatible = "ti,gate-clock"; |
116 | clocks = <&dpll_per_m2_ck>; | 110 | clocks = <&dpll_per_m2_ck>; |
117 | ti,bit-shift = <1>; | 111 | ti,bit-shift = <1>; |
118 | reg = <0x0664>; | 112 | reg = <0x0664>; |
119 | }; | 113 | }; |
120 | 114 | ||
121 | ehrpwm1_tbclk: ehrpwm1_tbclk { | 115 | ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { |
122 | #clock-cells = <0>; | ||
123 | compatible = "ti,composite-clock"; | ||
124 | clocks = <&ehrpwm1_gate_tbclk>; | ||
125 | }; | ||
126 | |||
127 | ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { | ||
128 | #clock-cells = <0>; | 116 | #clock-cells = <0>; |
129 | compatible = "ti,composite-no-wait-gate-clock"; | 117 | compatible = "ti,gate-clock"; |
130 | clocks = <&dpll_per_m2_ck>; | 118 | clocks = <&dpll_per_m2_ck>; |
131 | ti,bit-shift = <2>; | 119 | ti,bit-shift = <2>; |
132 | reg = <0x0664>; | 120 | reg = <0x0664>; |
133 | }; | 121 | }; |
134 | |||
135 | ehrpwm2_tbclk: ehrpwm2_tbclk { | ||
136 | #clock-cells = <0>; | ||
137 | compatible = "ti,composite-clock"; | ||
138 | clocks = <&ehrpwm2_gate_tbclk>; | ||
139 | }; | ||
140 | }; | 122 | }; |
141 | &prcm_clocks { | 123 | &prcm_clocks { |
142 | clk_32768_ck: clk_32768_ck { | 124 | clk_32768_ck: clk_32768_ck { |