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-rw-r--r--arch/arm/boot/compressed/Makefile4
-rw-r--r--arch/arm/boot/compressed/head-clps7500.S86
-rw-r--r--arch/arm/boot/compressed/head.S20
-rw-r--r--arch/arm/boot/compressed/misc.c2
4 files changed, 18 insertions, 94 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index c47f2a3f8f8f..fbe5eef1f6c9 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -23,10 +23,6 @@ ifeq ($(CONFIG_ARCH_L7200),y)
23OBJS += head-l7200.o 23OBJS += head-l7200.o
24endif 24endif
25 25
26ifeq ($(CONFIG_ARCH_CLPS7500),y)
27HEAD = head-clps7500.o
28endif
29
30ifeq ($(CONFIG_ARCH_P720T),y) 26ifeq ($(CONFIG_ARCH_P720T),y)
31# Borrow this code from SA1100 27# Borrow this code from SA1100
32OBJS += head-sa1100.o 28OBJS += head-sa1100.o
diff --git a/arch/arm/boot/compressed/head-clps7500.S b/arch/arm/boot/compressed/head-clps7500.S
deleted file mode 100644
index 4f3c78ac30a0..000000000000
--- a/arch/arm/boot/compressed/head-clps7500.S
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * linux/arch/arm/boot/compressed/head-clps7500.S
3 *
4 * Copyright (C) 1999, 2000, 2001 Nexus Electronics Ltd
5 */
6
7
8 /* There are three different ways the kernel can be
9 booted on a 7500 system: from Angel (loaded in RAM), from
10 16-bit ROM or from 32-bit Flash. Luckily, a single kernel
11 image does for them all. */
12 /* This branch is taken if the CPU memory width matches the
13 actual device in use. The default at power on is 16 bits
14 so we must be prepared for a mismatch. */
15 .section ".start", "ax"
162:
17 b 1f
18 .word 0xffff
19 .word 0xb632 @ mov r11, #0x03200000
20 .word 0xe3a0
21 .word 0x0000 @ mov r0, #0
22 .word 0xe3a0
23 .word 0x0080 @ strb r0, [r11, #0x80]
24 .word 0xe5cb
25 .word 0xf000 @ mov pc, #0
26 .word 0xe3a0
271:
28 adr r1, 2b
29 teq r1, #0
30 bne .Langel
31 /* This is a direct-from-ROM boot. Copy the kernel into
32 RAM and run it there. */
33 mov r0, #0x30
34 mcr p15, 0, r0, c1, c0, 0
35 mov r0, #0x13
36 msr cpsr_cxsf, r0
37 mov r12, #0x03000000 @ point to LEDs
38 orr r12, r12, #0x00020000
39 orr r12, r12, #0xba00
40 mov r0, #0x5500
41 str r0, [r12]
42 mov r0, #0x10000000
43 orr r0, r0, #0x8000
44 mov r4, r0
45 ldr r2, =_end
462:
47 ldr r3, [r1], #4
48 str r3, [r0], #4
49 teq r0, r2
50 bne 2b
51 mov r0, #0xff00
52 str r0, [r12]
531:
54 mov r12, #0x03000000 @ point to LEDs
55 orr r12, r12, #0x00020000
56 orr r12, r12, #0xba00
57 mov r0, #0xfe00
58 str r0, [r12]
59
60 adr lr, 1f
61 mov r0, #0
62 mov r1, #14 /* MACH_TYPE_CLPS7500 */
63 mov pc, lr
64.Langel:
65#ifdef CONFIG_ANGELBOOT
66 /* Call Angel to switch into SVC mode. */
67 mov r0, #0x17
68 swi 0x123456
69#endif
70 /* Ensure all interrupts are off and MMU disabled */
71 mrs r0, cpsr
72 orr r0, r0, #0xc0
73 msr cpsr_cxsf, r0
74
75 adr lr, 1b
76 orr lr, lr, #0x10000000
77 mov r0, #0x30 @ MMU off
78 mcr p15, 0, r0, c1, c0, 0
79 mov r0, r0
80 mov pc, lr
81
82 .ltorg
83
841:
85/* And the rest */
86#include "head.S"
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 84a1e0496a3c..77d614232d81 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -624,6 +624,12 @@ proc_types:
624 b __armv4_mmu_cache_off 624 b __armv4_mmu_cache_off
625 b __armv4_mmu_cache_flush 625 b __armv4_mmu_cache_flush
626 626
627 .word 0x56056930
628 .word 0xff0ffff0 @ PXA935
629 b __armv4_mmu_cache_on
630 b __armv4_mmu_cache_off
631 b __armv4_mmu_cache_flush
632
627 .word 0x56050000 @ Feroceon 633 .word 0x56050000 @ Feroceon
628 .word 0xff0f0000 634 .word 0xff0f0000
629 b __armv4_mmu_cache_on 635 b __armv4_mmu_cache_on
@@ -717,6 +723,9 @@ __armv7_mmu_cache_off:
717 bl __armv7_mmu_cache_flush 723 bl __armv7_mmu_cache_flush
718 mov r0, #0 724 mov r0, #0
719 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 725 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
726 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
727 mcr p15, 0, r0, c7, c10, 4 @ DSB
728 mcr p15, 0, r0, c7, c5, 4 @ ISB
720 mov pc, r12 729 mov pc, r12
721 730
722__arm6_mmu_cache_off: 731__arm6_mmu_cache_off:
@@ -778,12 +787,13 @@ __armv6_mmu_cache_flush:
778__armv7_mmu_cache_flush: 787__armv7_mmu_cache_flush:
779 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 788 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
780 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 789 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
781 beq hierarchical
782 mov r10, #0 790 mov r10, #0
791 beq hierarchical
783 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 792 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
784 b iflush 793 b iflush
785hierarchical: 794hierarchical:
786 stmfd sp!, {r0-r5, r7, r9-r11} 795 mcr p15, 0, r10, c7, c10, 5 @ DMB
796 stmfd sp!, {r0-r5, r7, r9, r11}
787 mrc p15, 1, r0, c0, c0, 1 @ read clidr 797 mrc p15, 1, r0, c0, c0, 1 @ read clidr
788 ands r3, r0, #0x7000000 @ extract loc from clidr 798 ands r3, r0, #0x7000000 @ extract loc from clidr
789 mov r3, r3, lsr #23 @ left align loc bit field 799 mov r3, r3, lsr #23 @ left align loc bit field
@@ -820,12 +830,14 @@ skip:
820 cmp r3, r10 830 cmp r3, r10
821 bgt loop1 831 bgt loop1
822finished: 832finished:
833 ldmfd sp!, {r0-r5, r7, r9, r11}
823 mov r10, #0 @ swith back to cache level 0 834 mov r10, #0 @ swith back to cache level 0
824 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 835 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
825 ldmfd sp!, {r0-r5, r7, r9-r11}
826iflush: 836iflush:
837 mcr p15, 0, r10, c7, c10, 4 @ DSB
827 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 838 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
828 mcr p15, 0, r10, c7, c10, 4 @ drain WB 839 mcr p15, 0, r10, c7, c10, 4 @ DSB
840 mcr p15, 0, r10, c7, c5, 4 @ ISB
829 mov pc, lr 841 mov pc, lr
830 842
831__armv5tej_mmu_cache_flush: 843__armv5tej_mmu_cache_flush:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 65ce8fff29db..3fc08413fff0 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -86,6 +86,8 @@ static void putstr(const char *ptr)
86 86
87#define __ptr_t void * 87#define __ptr_t void *
88 88
89#define memzero(s,n) __memzero(s,n)
90
89/* 91/*
90 * Optimised C version of memzero for the ARM. 92 * Optimised C version of memzero for the ARM.
91 */ 93 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 15:05:55 -0500