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-rw-r--r--arch/arm/boot/compressed/head.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b8c64b80bafc..81769c1341fa 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
659#ifdef CONFIG_CPU_ENDIAN_BE8 659#ifdef CONFIG_CPU_ENDIAN_BE8
660 orr r0, r0, #1 << 25 @ big-endian page tables 660 orr r0, r0, #1 << 25 @ big-endian page tables
661#endif 661#endif
662 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
662 orrne r0, r0, #1 @ MMU enabled 663 orrne r0, r0, #1 @ MMU enabled
663 movne r1, #0xfffffffd @ domain 0 = client 664 movne r1, #0xfffffffd @ domain 0 = client
665 bic r6, r6, #1 << 31 @ 32-bit translation system
666 bic r6, r6, #3 << 0 @ use only ttbr0
664 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 667 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
665 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 668 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
669 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
666#endif 670#endif
667 mcr p15, 0, r0, c7, c5, 4 @ ISB 671 mcr p15, 0, r0, c7, c5, 4 @ ISB
668 mcr p15, 0, r0, c1, c0, 0 @ load control register 672 mcr p15, 0, r0, c1, c0, 0 @ load control register