diff options
Diffstat (limited to 'arch/arm/boot/compressed/head.S')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index b371fba1b954..01d49be3b2ca 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -438,6 +438,9 @@ __armv4_mmu_cache_on: | |||
| 438 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | 438 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 439 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | 439 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement |
| 440 | orr r0, r0, #0x0030 | 440 | orr r0, r0, #0x0030 |
| 441 | #ifdef CONFIG_CPU_ENDIAN_BE8 | ||
| 442 | orr r0, r0, #1 << 25 @ big-endian page tables | ||
| 443 | #endif | ||
| 441 | bl __common_mmu_cache_on | 444 | bl __common_mmu_cache_on |
| 442 | mov r0, #0 | 445 | mov r0, #0 |
| 443 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | 446 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs |
| @@ -455,6 +458,9 @@ __armv7_mmu_cache_on: | |||
| 455 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | 458 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
| 456 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | 459 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement |
| 457 | orr r0, r0, #0x003c @ write buffer | 460 | orr r0, r0, #0x003c @ write buffer |
| 461 | #ifdef CONFIG_CPU_ENDIAN_BE8 | ||
| 462 | orr r0, r0, #1 << 25 @ big-endian page tables | ||
| 463 | #endif | ||
| 458 | orrne r0, r0, #1 @ MMU enabled | 464 | orrne r0, r0, #1 @ MMU enabled |
| 459 | movne r1, #-1 | 465 | movne r1, #-1 |
| 460 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | 466 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer |