1 files changed, 29 insertions, 11 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1532e8..abf4d65acf62 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
 
                 .text
                 adr     r0, LC0
- ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
+ ARM(           ldmia   r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(         ldmia   r0, {r1, r2, r3, r5, r6, r11, ip}       )
  THUMB(         ldr     sp, [r0, #32]                           )
+#ifdef CONFIG_AUTO_ZRELADDR
+                @ determine final kernel image address
+                and     r4, pc, #0xf8000000
+                add     r4, r4, #TEXT_OFFSET
+#else
+                ldr     r4, =CONFIG_ZRELADDR
+#endif
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite:	mov	r0, r4
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
                 .word   _end                    @ r3
-                .word   zreladdr                @ r4
                 .word   _start                  @ r5
                 .word   _image_size             @ r6
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
-                .word   user_stack+4096         @ sp
+                .word   user_stack_end          @ sp
 LC1:            .word   reloc_end - reloc_start
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
                 .globl  params
-params:         ldr     r0, =params_phys
+params:         ldr     r0, =0x10000100         @ params_phys for RPC
                 mov     pc, lr
                 .ltorg
                 .align
@@ -339,9 +345,8 @@ params:		ldr	r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
 
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                /*
+                 * ?? ARMv3 MMU does not allow reading the control register,
+                 * does this really work on ARMv3 MPU?
+                 */
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                                                 @ .... .... .... WC.M
                 orr     r0, r0, #0x000d         @ .... .... .... 11.1
+                /* ?? this overwrites the value constructed above? */
                 mov     r0, #0
                 mcr     p15, 0, r0, c1, c0, 0   @ write control reg
 
+                /* ?? invalidate for the second time? */
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
@@ -771,8 +782,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
                 .align  5
 cache_off:      mov     r3, #12                 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
@@ -988,7 +1001,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
                 mov     r1, #0
-                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
 /*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:           adr     r3, phexbuf
                 mov     r2, #0
                 strb    r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex:		adr	r3, phexbuf
                 strb    r2, [r3, r1]
                 b       1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:           loadsp  r3, r1
 1:              ldrb    r2, [r0], #1
                 teq     r2, #0
@@ -1029,12 +1044,14 @@ puts:		loadsp	r3, r1
                 teq     r0, #0
                 bne     1b
                 mov     pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
                 mov     r2, r0
                 mov     r0, #0
                 loadsp  r3, r1
                 b       2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:        mov     r12, r0
                 mov     r10, lr
                 mov     r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
                 .align
                 .section ".stack", "w"
 user_stack:     .space  4096
+user_stack_end: