diff options
Diffstat (limited to 'arch/arm/Kconfig')
-rw-r--r-- | arch/arm/Kconfig | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 76efd438a140..7a0c31a6669e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -371,7 +371,6 @@ config ARCH_CNS3XXX | |||
371 | config ARCH_CLPS711X | 371 | config ARCH_CLPS711X |
372 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" | 372 | bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" |
373 | select ARCH_REQUIRE_GPIOLIB | 373 | select ARCH_REQUIRE_GPIOLIB |
374 | select ARCH_USES_GETTIMEOFFSET | ||
375 | select AUTO_ZRELADDR | 374 | select AUTO_ZRELADDR |
376 | select CLKDEV_LOOKUP | 375 | select CLKDEV_LOOKUP |
377 | select COMMON_CLK | 376 | select COMMON_CLK |
@@ -938,17 +937,24 @@ config ARCH_DAVINCI | |||
938 | help | 937 | help |
939 | Support for TI's DaVinci platform. | 938 | Support for TI's DaVinci platform. |
940 | 939 | ||
941 | config ARCH_OMAP | 940 | config ARCH_OMAP1 |
942 | bool "TI OMAP" | 941 | bool "TI OMAP1" |
943 | depends on MMU | 942 | depends on MMU |
944 | select ARCH_HAS_CPUFREQ | 943 | select ARCH_HAS_CPUFREQ |
945 | select ARCH_HAS_HOLES_MEMORYMODEL | 944 | select ARCH_HAS_HOLES_MEMORYMODEL |
945 | select ARCH_OMAP | ||
946 | select ARCH_REQUIRE_GPIOLIB | 946 | select ARCH_REQUIRE_GPIOLIB |
947 | select CLKDEV_LOOKUP | ||
947 | select CLKSRC_MMIO | 948 | select CLKSRC_MMIO |
948 | select GENERIC_CLOCKEVENTS | 949 | select GENERIC_CLOCKEVENTS |
950 | select GENERIC_IRQ_CHIP | ||
949 | select HAVE_CLK | 951 | select HAVE_CLK |
952 | select HAVE_IDE | ||
953 | select IRQ_DOMAIN | ||
954 | select NEED_MACH_IO_H if PCCARD | ||
955 | select NEED_MACH_MEMORY_H | ||
950 | help | 956 | help |
951 | Support for TI's OMAP platform (OMAP1/2/3/4). | 957 | Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) |
952 | 958 | ||
953 | endchoice | 959 | endchoice |
954 | 960 | ||
@@ -1214,6 +1220,7 @@ config ARM_ERRATA_430973 | |||
1214 | config ARM_ERRATA_458693 | 1220 | config ARM_ERRATA_458693 |
1215 | bool "ARM errata: Processor deadlock when a false hazard is created" | 1221 | bool "ARM errata: Processor deadlock when a false hazard is created" |
1216 | depends on CPU_V7 | 1222 | depends on CPU_V7 |
1223 | depends on !ARCH_MULTIPLATFORM | ||
1217 | help | 1224 | help |
1218 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) | 1225 | This option enables the workaround for the 458693 Cortex-A8 (r2p0) |
1219 | erratum. For very specific sequences of memory operations, it is | 1226 | erratum. For very specific sequences of memory operations, it is |
@@ -1227,6 +1234,7 @@ config ARM_ERRATA_458693 | |||
1227 | config ARM_ERRATA_460075 | 1234 | config ARM_ERRATA_460075 |
1228 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" | 1235 | bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" |
1229 | depends on CPU_V7 | 1236 | depends on CPU_V7 |
1237 | depends on !ARCH_MULTIPLATFORM | ||
1230 | help | 1238 | help |
1231 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) | 1239 | This option enables the workaround for the 460075 Cortex-A8 (r2p0) |
1232 | erratum. Any asynchronous access to the L2 cache may encounter a | 1240 | erratum. Any asynchronous access to the L2 cache may encounter a |
@@ -1239,6 +1247,7 @@ config ARM_ERRATA_460075 | |||
1239 | config ARM_ERRATA_742230 | 1247 | config ARM_ERRATA_742230 |
1240 | bool "ARM errata: DMB operation may be faulty" | 1248 | bool "ARM errata: DMB operation may be faulty" |
1241 | depends on CPU_V7 && SMP | 1249 | depends on CPU_V7 && SMP |
1250 | depends on !ARCH_MULTIPLATFORM | ||
1242 | help | 1251 | help |
1243 | This option enables the workaround for the 742230 Cortex-A9 | 1252 | This option enables the workaround for the 742230 Cortex-A9 |
1244 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction | 1253 | (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction |
@@ -1251,6 +1260,7 @@ config ARM_ERRATA_742230 | |||
1251 | config ARM_ERRATA_742231 | 1260 | config ARM_ERRATA_742231 |
1252 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" | 1261 | bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" |
1253 | depends on CPU_V7 && SMP | 1262 | depends on CPU_V7 && SMP |
1263 | depends on !ARCH_MULTIPLATFORM | ||
1254 | help | 1264 | help |
1255 | This option enables the workaround for the 742231 Cortex-A9 | 1265 | This option enables the workaround for the 742231 Cortex-A9 |
1256 | (r2p0..r2p2) erratum. Under certain conditions, specific to the | 1266 | (r2p0..r2p2) erratum. Under certain conditions, specific to the |
@@ -1301,6 +1311,7 @@ config PL310_ERRATA_727915 | |||
1301 | config ARM_ERRATA_743622 | 1311 | config ARM_ERRATA_743622 |
1302 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" | 1312 | bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" |
1303 | depends on CPU_V7 | 1313 | depends on CPU_V7 |
1314 | depends on !ARCH_MULTIPLATFORM | ||
1304 | help | 1315 | help |
1305 | This option enables the workaround for the 743622 Cortex-A9 | 1316 | This option enables the workaround for the 743622 Cortex-A9 |
1306 | (r2p*) erratum. Under very rare conditions, a faulty | 1317 | (r2p*) erratum. Under very rare conditions, a faulty |
@@ -1314,6 +1325,7 @@ config ARM_ERRATA_743622 | |||
1314 | config ARM_ERRATA_751472 | 1325 | config ARM_ERRATA_751472 |
1315 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" | 1326 | bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" |
1316 | depends on CPU_V7 | 1327 | depends on CPU_V7 |
1328 | depends on !ARCH_MULTIPLATFORM | ||
1317 | help | 1329 | help |
1318 | This option enables the workaround for the 751472 Cortex-A9 (prior | 1330 | This option enables the workaround for the 751472 Cortex-A9 (prior |
1319 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the | 1331 | to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the |