1 files changed, 52 insertions, 8 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e02b893fb909..9faccc411c2a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -486,8 +486,6 @@ config ARCH_PXA
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
-        select HAVE_CLK
-        select COMMON_CLKDEV
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
@@ -585,6 +583,8 @@ config ARCH_DAVINCI
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select ZONE_DMA
+        select HAVE_IDE
+        select COMMON_CLKDEV
         help
           Support for TI's DaVinci platform.
 
@@ -740,6 +740,56 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_411920
+        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
+        depends on CPU_V6 && !SMP
+        help
+          Invalidation of the Instruction Cache operation can
+          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
+          It does not affect the MPCore. This option enables the ARM Ltd.
+          recommended workaround.
+
+config ARM_ERRATA_430973
+        bool "ARM errata: Stale prediction on replaced interworking branch"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 430973 Cortex-A8
+          (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
+          interworking branch is replaced with another code sequence at the
+          same virtual address, whether due to self-modifying code or virtual
+          to physical address re-mapping, Cortex-A8 does not recover from the
+          stale interworking branch prediction. This results in Cortex-A8
+          executing the new code sequence in the incorrect ARM or Thumb state.
+          The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
+          and also flushes the branch target cache at every context switch.
+          Note that setting specific bits in the ACTLR register may not be
+          available in non-secure mode.
+
+config ARM_ERRATA_458693
+        bool "ARM errata: Processor deadlock when a false hazard is created"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 458693 Cortex-A8 (r2p0)
+          erratum. For very specific sequences of memory operations, it is
+          possible for a hazard condition intended for a cache line to instead
+          be incorrectly associated with a different cache line. This false
+          hazard might then cause a processor deadlock. The workaround enables
+          the L1 caching of the NEON accesses and disables the PLD instruction
+          in the ACTLR register. Note that setting specific bits in the ACTLR
+          register may not be available in non-secure mode.
+
+config ARM_ERRATA_460075
+        bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 460075 Cortex-A8 (r2p0)
+          erratum. Any asynchronous access to the L2 cache may encounter a
+          situation in which recent store transactions to the L2 cache are lost
+          and overwritten with stale memory contents from external memory. The
+          workaround disables the write-allocate mode for the L2 cache via the
+          ACTLR register. Note that setting specific bits in the ACTLR register
+          may not be available in non-secure mode.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1171,12 +1221,6 @@ config CPU_FREQ_IMX
 
           If in doubt, say N.
 
-config CPU_FREQ_PXA
-        bool
-        depends on CPU_FREQ && ARCH_PXA && PXA25x
-        default y
-        select CPU_FREQ_DEFAULT_GOV_USERSPACE
-
 endif
 
 source "drivers/cpuidle/Kconfig"