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-rw-r--r--arch/arm/Kconfig50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fb2a51b0ec15..e4a765438ee3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARM
12 select HAVE_IDE 12 select HAVE_IDE
13 select RTC_LIB 13 select RTC_LIB
14 select SYS_SUPPORTS_APM_EMULATION 14 select SYS_SUPPORTS_APM_EMULATION
15 select GENERIC_ATOMIC64 if (!CPU_32v6K)
15 select HAVE_OPROFILE 16 select HAVE_OPROFILE
16 select HAVE_ARCH_KGDB 17 select HAVE_ARCH_KGDB
17 select HAVE_KPROBES if (!XIP_KERNEL) 18 select HAVE_KPROBES if (!XIP_KERNEL)
@@ -20,6 +21,8 @@ config ARM
20 select HAVE_GENERIC_DMA_COHERENT 21 select HAVE_GENERIC_DMA_COHERENT
21 select HAVE_KERNEL_GZIP 22 select HAVE_KERNEL_GZIP
22 select HAVE_KERNEL_LZO 23 select HAVE_KERNEL_LZO
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
23 help 26 help
24 The ARM series is a line of low-power-consumption RISC chip designs 27 The ARM series is a line of low-power-consumption RISC chip designs
25 licensed by ARM Ltd and targeted at embedded applications and 28 licensed by ARM Ltd and targeted at embedded applications and
@@ -52,6 +55,9 @@ config HAVE_TCM
52 bool 55 bool
53 select GENERIC_ALLOCATOR 56 select GENERIC_ALLOCATOR
54 57
58config HAVE_PROC_CPU
59 bool
60
55config NO_IOPORT 61config NO_IOPORT
56 bool 62 bool
57 63
@@ -161,6 +167,11 @@ config ARCH_MTD_XIP
161config GENERIC_HARDIRQS_NO__DO_IRQ 167config GENERIC_HARDIRQS_NO__DO_IRQ
162 def_bool y 168 def_bool y
163 169
170config ARM_L1_CACHE_SHIFT_6
171 bool
172 help
173 Setting ARM L1 cache line size to 64 Bytes.
174
164if OPROFILE 175if OPROFILE
165 176
166config OPROFILE_ARMV6 177config OPROFILE_ARMV6
@@ -550,6 +561,15 @@ config ARCH_W90X900
550 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 561 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
551 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 562 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
552 563
564config ARCH_NUC93X
565 bool "Nuvoton NUC93X CPU"
566 select CPU_ARM926T
567 select HAVE_CLK
568 select COMMON_CLKDEV
569 help
570 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
571 low-power and high performance MPEG-4/JPEG multimedia controller chip.
572
553config ARCH_PNX4008 573config ARCH_PNX4008
554 bool "Philips Nexperia PNX4008 Mobile" 574 bool "Philips Nexperia PNX4008 Mobile"
555 select CPU_ARM926T 575 select CPU_ARM926T
@@ -639,6 +659,7 @@ config ARCH_S5PC1XX
639 select GENERIC_GPIO 659 select GENERIC_GPIO
640 select HAVE_CLK 660 select HAVE_CLK
641 select CPU_V7 661 select CPU_V7
662 select ARM_L1_CACHE_SHIFT_6
642 help 663 help
643 Samsung S5PC1XX series based systems 664 Samsung S5PC1XX series based systems
644 665
@@ -785,6 +806,8 @@ source "arch/arm/plat-nomadik/Kconfig"
785 806
786source "arch/arm/mach-ns9xxx/Kconfig" 807source "arch/arm/mach-ns9xxx/Kconfig"
787 808
809source "arch/arm/mach-nuc93x/Kconfig"
810
788source "arch/arm/plat-omap/Kconfig" 811source "arch/arm/plat-omap/Kconfig"
789 812
790source "arch/arm/mach-omap1/Kconfig" 813source "arch/arm/mach-omap1/Kconfig"
@@ -867,6 +890,11 @@ config XSCALE_PMU
867 depends on CPU_XSCALE && !XSCALE_PMU_TIMER 890 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
868 default y 891 default y
869 892
893config CPU_HAS_PMU
894 depends on CPU_V6 || CPU_V7 || XSCALE_PMU
895 default y
896 bool
897
870if !MMU 898if !MMU
871source "arch/arm/Kconfig-nommu" 899source "arch/arm/Kconfig-nommu"
872endif 900endif
@@ -921,6 +949,19 @@ config ARM_ERRATA_460075
921 ACTLR register. Note that setting specific bits in the ACTLR register 949 ACTLR register. Note that setting specific bits in the ACTLR register
922 may not be available in non-secure mode. 950 may not be available in non-secure mode.
923 951
952config PL310_ERRATA_588369
953 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
954 depends on CACHE_L2X0 && ARCH_OMAP4
955 help
956 The PL310 L2 cache controller implements three types of Clean &
957 Invalidate maintenance operations: by Physical Address
958 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
959 They are architecturally defined to behave as the execution of a
960 clean operation followed immediately by an invalidate operation,
961 both performing to the same memory location. This functionality
962 is not correctly implemented in PL310 as clean lines are not
963 invalidated as a result of these operations. Note that this errata
964 uses Texas Instrument's secure monitor api.
924endmenu 965endmenu
925 966
926source "arch/arm/common/Kconfig" 967source "arch/arm/common/Kconfig"
@@ -1171,6 +1212,14 @@ config HIGHPTE
1171 depends on HIGHMEM 1212 depends on HIGHMEM
1172 depends on !OUTER_CACHE 1213 depends on !OUTER_CACHE
1173 1214
1215config HW_PERF_EVENTS
1216 bool "Enable hardware performance counter support for perf events"
1217 depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
1218 default y
1219 help
1220 Enable hardware performance counter support for perf events. If
1221 disabled, perf events will use software events only.
1222
1174source "mm/Kconfig" 1223source "mm/Kconfig"
1175 1224
1176config LEDS 1225config LEDS
@@ -1230,6 +1279,7 @@ config ALIGNMENT_TRAP
1230 bool 1279 bool
1231 depends on CPU_CP15_MMU 1280 depends on CPU_CP15_MMU
1232 default y if !ARCH_EBSA110 1281 default y if !ARCH_EBSA110
1282 select HAVE_PROC_CPU if PROC_FS
1233 help 1283 help
1234 ARM processors cannot fetch/store information which is not 1284 ARM processors cannot fetch/store information which is not
1235 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1285 naturally aligned on the bus, i.e., a 4 byte fetch must start at an